© 2012 Fairchild Semiconductor Corporation
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FEBFAN9611_S01U300A
• Rev. 0.0.1
10.6.
Phase Management
Figure 37 and Figure 38 show the phase-shedding waveforms. As observed, when the
gate drive signal of Channel 2 is disabled, the duty cycle of Channel 1 gate drive signal is
doubled to minimize the line current glitch and guarantee smooth transient.
CH1: Gate Drive 1 Voltage (20V/div), CH2: Gate Drive 2 Voltage (20V/div),
CH3: Inductor L1 Current (1A/div), CH4: Inductor L2 Current (1A/div), Time (5ms/div)
Figure 37. Phase-Shedding Operation
CH1: Gate Drive 1 Voltage (20V/div), CH2: Gate Drive 2 Voltage (20V/div),
CH3: Inductor L1 Current (1A/div), CH4: Inductor L2 Current (1A/div), Time (5µs/div)
Figure 38. Phase-Shedding Operation (Zoomed-in Timescale)
DRV1
DRV2
I
L1
I
L2
DRV1
DRV2
I
L1
I
L2
