© 2012 Fairchild Semiconductor Corporation
19
FEBFAN9611_S01U300A
• Rev. 0.0.1
Figure 19 and Figure 20 show the startup operation at 230V
AC
line voltage for no-load
and full-load conditions, respectively. Due to the closed-loop soft-start, almost no
overshoot is observed for no-load startup and full-load startup.
CH1: Gate Drive 1 Voltage (20V/div), CH2: COMP Voltage (2V/div),
CH3: Output Voltage (200V/div), CH4: Line Current (10A/div), Time (100ms/div)
Figure 19. No-Load Startup at 230V
AC
CH1: Gate Drive 1 Voltage (20V/div), CH2: COMP Voltage (2V/div),
CH3: Output Voltage (200V/div), CH4: Line Current (10A/div), Time (100ms/div)
Figure 20. Full-Load Startup at 230V
AC
DRV1
V
OUT
Line
Current
DRV1
V
OUT
Line
Current
COMP
COMP
