© 2012 Fairchild Semiconductor Corporation
18
FEBFAN9611_S01U300A
• Rev. 0.0.1
10.
Test Results
10.1.
Startup
Figure 17 and Figure 18 show the startup operation at 115V
AC
line voltage for no-load
and full-load condition, respectively. Due to the closed-loop soft-start, almost no
overshoot is observed for no-load startup and full-load startup.
CH1: Gate Drive 1 Voltage (20V/div), CH2: COMP Voltage (2V/div),
CH3: Output Voltage (200V/div), CH4: Line Current (5A/div), Time (100ms/div)
Figure 17. No-Load Startup at 115V
AC
CH1: Gate Drive 1 Voltage (20V/div), CH2: COMP Voltage (2V/div),
CH3: Output Voltage (200V/div), CH4: Line Current (5A/div), Time (200ms/div)
Figure 18. Full-Load Startup at 115V
AC
DRV1
V
OUT
Line
Current
DRV1
V
OUT
Line
Current
COMP
COMP
