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©2002 Fairchild Semiconductor Corporation

Application Note 7511 Rev. A1

It’s impractical, however, to rate an inverter based on locked-
rotor current. You can avoid this necessity by adjusting the
switching regulator’s output voltage and by providing a fixed
output-current limit slightly higher than the maximum full-
load current. This way, the current requirements during start-
up will never exceed the current capability of an efficiently
sized inverter.

For example, consider a 2-hp, 3-phase induction motor spec-
ifying V

L

 at 230V RMS and full-load current (I

LFL

) at 6.2A

RMS. For the peak current of 8.766A, you can select IGT
type D94FR4. This device has a reverse-breakdown SOA
(RBSOA) of 10A, 500V for a clamped inductive load at a
junction temperature of 150

o

C. A 400V IGT could also do the

job, but the 500V choice gives an additional derating safety
margin. You must set the current limit at 9A to limit the in-
rush current during start-up. Note that thanks to the IGT’s
adequate RBSOA, you don’t need turn-off snubbers.

FIGURE 11A. PROVIDING PROPERLY TIMED DRIVE TO THE IGTS, THE CIRCUIT USES PIEZO COUPLING TO THE UPPER POWER 

DEVICE. THE 3-TRANSISTOR DELAY CIRCUIT PROVIDES THE NEEDED 15

o

 LAG TO THE LOWER IGT TO AVOID

CROSS CONDUCTION.

FIGURE 11B. THE TIMING DIAGRAM SHOWS THE 555’S 108-KHz DRIVE TO THE PIEZO DEVICE AND THE LATTER’S SLOW

RESPONSE.

1N914

NE555

4

7

8 3

2

1

5

6

2N3903

VCO &

TIMING

LOGIC

1000pF

2.7k

3.3k

1k

5V

0.001

µ

F

5V

A 4.7k

470

Q

7

B

1N914

4.7k

C

Q

8

2N3903

2N3903

Q

8

470

470

1N914

1N914

2N3903

1N914

D33030

D29E10

1N914

D94FR4

D94FR4

PIEZOCOUPLER

24V

24V

Q

3

Q

4

Q

5

Q

1

Q

2

4.7k

4.7k

10

10

22

µ

F

C

1

DC BUS

φ

A

E

F

D

3

PZT61343

1k

470

2.5k

VOLTS

24V

F

24V

E

24V

D

C

B

A

TIME

TIME

TIME

TIME

TIME

5V

5V

5V

100kHz

Application Note 7511

Summary of Contents for AN-7511

Page 1: ... sum of R3 and the parallel combination of R1 and R2 sets the turn on time Drive circuit requirements however are more complex in the common collector configuration Figure 1B In this floating gate supply floating control drive scheme R1 controls the gate supply s power loss R2 governs the turn off time and the sum of R1 and R2 sets the turn on time Figure 1C shows another common collector configur...

Page 2: ...ler drive along with its transient response In some applications the photovoltaic element can charge a storage capacitor that s subsequently switched with a phototransistor isolator This isolator technique similar to that used in bootstrap circuits provides rapid turn on and turn off while maintaining small size good isolation and low cost In common collector applications involving high voltage re...

Page 3: ...NTROL INPUT ON OFF GFOE1A1 EMITTER DISCONNECTED DETECTOR CONNECTED 10M 30FT QSF2000C W CONNECTORS GFOD1A1 1N914 R1 2N5354 C Q1 R2 R3 IGT FIGURE 4 ELIMINATE EMI IN HIGH FLUX OR NOISE ENVI RONMENTS BY USING FIBER OPTIC COMPO NENTS THESE PARTS ALSO ALLEVIATE PROBLEMS ARISING FROM CAPACITIVE COU PLING IN ISOLATION ELEMENTS Piezos Pare Prices OUTPUT VOLTAGE ACOUSTIC WAVE OSCILLATOR IGT 4 7k 1N914 1N914...

Page 4: ...GH ISOLATION AT LOW COST PULSE TRANSFORMERS ARE IDEAL FOR DRIVING THE IGT AT SUFFICIENTLY HIGH FREQUENCIES C1 CAN BE THE IGT S GATE EMITTERCAPACITANCE ALONE FIGURE 6B A HIGH FREQUENCY OSCILLATOR IN THE TRANS FORMER S PRIMARY YIELDS UNLIMITED ON TIME CAPABILITY In the pulse on pulse off method Figure 6A C1 stores a positive pulse holding the IGT on At moderate frequencies several hundred Hertz and ...

Page 5: ...ransformer reasonably small The volt age doubler circuitry improves the turn on time and also pro vides long on time capability Although this design uses only a 5V supply on the primary side of a standard trigger trans former it provides 15V gate to emitter voltage FIGURE 7 THIS DRIVING METHOD FOR LOW FREQUENCY SWITCHING PROVIDES 15V TO THE IGT S GATE OSCILLATOR 1 2 1N914 0 001µF 4 7k 0 001 µF IGT...

Page 6: ...r to shut off The inverter s power out put circuit is shown in Figure 9A the corresponding timing diagrams show resistive load current waveforms that indi cate the 3 phase power Figure 9B and waveforms of the out put line voltage and current Figure 9C In Figure 9 s circuit it appears that IGTs Q1 through Q6 will conduct for 180o However in a practical situation it s neces sary to provide some time...

Page 7: ... could also do the job but the 500V choice gives an additional derating safety margin You must set the current limit at 9A to limit the in rush current during start up Note that thanks to the IGT s adequate RBSOA you don t need turn off snubbers FIGURE 11A PROVIDING PROPERLY TIMED DRIVE TO THE IGTS THE CIRCUIT USES PIEZO COUPLING TO THE UPPER POWER DEVICE THE 3 TRANSISTOR DELAY CIRCUIT PROVIDES TH...

Page 8: ...65o Conduction Prevents Shoot Through Consider however using Figure 11A s novel low cost cir cuit It uses a piezo coupler to drive the isolated IGT As noted the coupler needs a high frequency square wave to induce mechanical oscillations in its primary side The 555 oscillator provides the necessary 108 kHz waveform its out put is gated according to the required timing logic and then applied to the...

Page 9: ...f the power switch and the circuit s bias conditions The IGT is very rugged during turn on and conduction but it requires time to dissipate minority carriers when turning off high currents and voltages An analysis of the possible malfunction condition FIGURE 14 THE LOWEST COST SENSOR IMAGINABLE A PIECE OF COPPER WIRE SERVES AS THE CURRENT MONITOR IN THIS SYS TEM THE CHOPPED AND AMPLIFIED VOLTAGE D...

Page 10: ...5V 5µF 25V 220k 2 2k 0 001 µF H11F3 H11F3 TO CONTROL CIRCUIT 39 470 pF 390 20A 2k 2mΩ 1 24 AWG COPPER POWER SUPPLY CURRENT SENSE AND CHOPPER AC AMPLIFIER LATCHING FAST COMPARATOR 10ms RESET IGT POWER SWITCHES A139M 50µH 10k 180k 47k 39k 0 001 µF 1k 2N5306 C203B 0 02 µF 22k H11AV2 TO PZO SHUTDOWN H11AV2 TO HI V SHUTDOWN 22 0 2µF 2 1 TO DRIVE DT230F TO MOTOR TIMER 555 1 3 CHOPPER DRIVE TO PIEZO DRIV...

Page 11: ...ich the IGT latches on while in forward conduction is typically three to four times the device s maximum rated collector current When the collector current drops below the value that provokes Q2 turn on normal operation resumes if chip temperature is still within ratings If the gate to emitter resistance is too low the Q2 Q3 parasitic SCR can cause the IGT to latch up during turn off During this p...

Page 12: ...EAT ER THAN THAT OF THE IGT S GATE DRIVE SO THE IGT UNDER TEST IS SWITCHED THROUGH Q1 WHEN REVERSE BIAS LATCH UP OCCURS PULSE GENERATOR PULSE GENERATOR TRIGGER 1000pF A114A A114A 1k 100 100 50 10 D38H1 D44D6 Q1 D66EV7 Q2 DUT D94FQ4 DS0026x2 5V 1N914 10V PE 63385 A114A 15V D66EV7 Q1 RGE 1 10k VCE A139M 10 VCC VCLAMP 400V MAX 0 02µF 10µF A139P L 100µH 2k Q2 Application Note 7511 ...

Page 13: ...support device or system or to affect its safety or effectiveness PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Preliminary No Identification Needed Obsolete This datasheet contains the design specifications for product development Specifications may change in any manner without notice This datasheet contains preliminary data ...

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