User Guide — EP9134_UG V0.7
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7
2.3 Pin Description
Unless otherwise stated, unused input pins must be tied to ground, and unused output pins left open.
Table 2-1 IIC Pins
NAME
IN /
OUT
DESCRIPTION
SCL1
IN
IIC SCL signal for receiver port DDC
SDA1
IO
IIC SDA signal for receiver port DDC (open drain)
SCL2
OUT
IIC SCL signal for EE interface (open drain)
SDA2
IO
IIC SDA signal for EE interface (open drain)
SCL3
IN
IIC SCL signal for internal registers access
SDA3
IO
IIC SDA signal for internal registers access (open drain)
A2, A1, A0
IN
Determine the lowest 3-bit of the IIC address for IIC Port 3 (SCL3/SDA3)
Table 2-2 Misc. Pins
NAME
IN /
OUT
DESCRIPTION
EXT_RSTb
IN
External Reset (Active LOW). A HIGH level indicates normal operation and a
LOW level causes all the logic on the chip to be reset.
M0_RDY
OUT
HDCP M0 Ready Signalling Output. This pin is set to HIGH while the AKSV is
written to receiver.
reserved
IN
Must be tied LOW for normal operation.
Table 2-3 Receiver Pins
NAME
IN /
OUT
DESCRIPTION
RX0-
RX0+
RX1-
RX1+
RX2-
RX2+
Analog
Differential Data Input Pairs for receiver port
RXC-
RXC+
Differential Clock Input Pairs for receiver port
EXT_RES
Analog
DVI/HDMI External Termination Resistor.
Table 2-4 Transmitter Pins
NAME
IN /
OUT
DESCRIPTION
TX00-
TX00+
TX10-
TX10+
TX20-
TX20+
Analog
Differential Data Output Pairs for transmitter port 0
TXC0-
TXC0+
Differential Clock Output Pairs for transmitter port 0
HTPLG0
IN
Hot Plug Input
This pin is used to monitor the "HOT PLUG" signal for transmitter port 0. Note:
This input is only 3.3V tolerant and has no internal debouncer circuit.
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