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User Guide — EP9134_UG V0.7

Explore Confidential Proprietary

NON-DISCLOSURE AGREEMENT REQUIRED

3.3.1 Register Descriptions

Detailed usage of these IIC registers is described in the following section.

3.3.1.1 TMDS Control Register 0

Table 3-2 TMDS Control Register 0

$05

bit

TMDS_SAMP[5:0]

Reset:

TMDS_SAMP[5:0] — TMDS Sampling Logic Control Parameters

This register is recommended to be programmed with the value 0x09 after the power on sequence if the
expected supported TMDS clock frequency is up to 225MHz (1080p, 12 bits deep color). The
TMDS_SAMP[0] is fixed to 1 always.

$6A

RX_SHA-1_HASH_10

XXh

$6B

RX_SHA-1_HASH_11

XXh

$6C

RX_SHA-1_HASH_12

XXh

$6D

RX_SHA-1_HASH_13

XXh

$6E

RX_SHA-1_HASH_14

XXh

$6F

RX_SHA-1_HASH_15

XXh

$70

RX_SHA-1_HASH_16

XXh

$71

RX_SHA-1_HASH_17

XXh

$72

RX_SHA-1_HASH_18

XXh

$73

RX_SHA-1_HASH_19

XXh

$80 ~

$CF

RX_KSV_FIFO

XXh

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Summary of Contents for EP9134

Page 1: ...uyer purchase or use Explore products for any such unintended or unauthorized application Buyer shall indemnify and hold Explore and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthor...

Page 2: ...ckage type to E PAD LQFP 0 4 Jul 23 2009 Ether Lai Remove redundant register descriptions Clarify HDMI version specification and CTS Revise Package Diagram 0 5 Aug 18 2009 Ether Lai Revise Package Diagram to E PAD 0 6 Oct 23 2009 Ether Lai Fix Typo in EXT_SWING pin descriptions 0 7 Nov 23 2009 Ether Lai Fix Typo in DC Analogue Specification and Figure 2 3 Fix typo in section 3 1 section 3 2 1 sect...

Page 3: ...I 1 3a specification and HDMI 1 3c Compliance Test Specification CTS Integrated HDCP decryption encryption engines which are compliant with HDCP Rev 1 2 specification Encrypted HDCP keys store in external serial EE Wide Frequency Range 25MHz 225MHz Support 12 bit Deep Color up to 1080p Supports 1 DVI HDMI input port and 4 DVI HDMI output ports Supports conversion of HDMI signaling to DVI signaling...

Page 4: ... EP9134_UG V0 7 Explore Confidential Proprietary NON DISCLOSURE AGREEMENT REQUIRED 4 E x p l o r e M i c r o e l e c t r o n i c s I n c C o n f i d e n t i a l f o r 南京东平电子 o r I n t e r n a l U s e O n l y ...

Page 5: ...eys DVI HDMI Transmitter HDCP Keys TX00 TX10 TX20 TXC0 TX01 TX11 TX21 TXC1 HDCP Keys DVI HDMI Transmitter HDCP Keys DVI HDMI Transmitter TX02 TX12 TX22 TXC0 TX03 TX13 TX23 TXC1 E x p l o r e TX00 TX00 X1 M i c r o e l e c t r o n e c e c e l r o er M i M i e l e l e e l e e r o n i c s o n c s o n i 0 0 I n c c e I n C o n f i d e n t i a l C o r n n C o C o f o r r 南京东平电子子子 TX T TX20 TX20 ...

Page 6: ..._RES 80 AVDD 81 RXC 82 RXC 83 AVSS 84 RX0 85 86 RX0 87 AVSS 88 89 AVDD 90 AVSS 91 RX1 92 RX1 93 AVDD 94 RX2 95 RX2 96 AVSS 97 _AVSS 98 _AVSS 99 _AVSS 100 _AVSS 101 _AVSS 102 103 104 105 106 107 108 109 110 111 112 113 114 TX03 115 AVSS 116 AVSS 117 TX13 118 TX13 119 AVDD 120 AVDD 121 TX23 122 TX23 123 AVSS 124 AVSS 125 PVSS 126 127 128 PVSS PVDD PVDD EXT_SWING23 AVSS HTPLG2 40 TX10 AVSS AVSS TX20 ...

Page 7: ...or normal operation Table 2 3 Receiver Pins NAME IN OUT DESCRIPTION RX0 RX0 RX1 RX1 RX2 RX2 Analog Differential Data Input Pairs for receiver port RXC RXC Differential Clock Input Pairs for receiver port EXT_RES Analog DVI HDMI External Termination Resistor Table 2 4 Transmitter Pins NAME IN OUT DESCRIPTION TX00 TX00 TX10 TX10 TX20 TX20 Analog Differential Data Output Pairs for transmitter port 0 ...

Page 8: ...rential Clock Output Pairs for transmitter port 3 HTPLG3 IN Hot Plug Input This pin is used to monitor the HOT PLUG signal for transmitter port 3 Note This input is only 3 3V tolerant and has no internal debouncer circuit EXT_SWING23 Analog Voltage Swing Adjust for Port 2 3 A resistor should tie this pin to AVDD This resistance determines the amplitude of the voltage swing Table 2 5 Power and Grou...

Page 9: ...prietary NON DISCLOSURE AGREEMENT REQUIRED 9 _AVSS GND Analog Ground Table 2 5 Power and Ground Pins NAME IN OUT DESCRIPTION E x p l o r e M i c r o e l e c t r o n i c s I n c C o n f i d e n t i a l f o r 南京东平电子 o r I n t e r n a l U s e O n l y ...

Page 10: ...nditions Symbol Parameter Min Typ Max Units Vcc33 3 3V Supply Voltage 3 14 3 3 3 6 V Vcc18 1 8V Supply Voltage 1 71 1 8 1 98 V VCCN Supply Voltage Noise1 0 3 100 mVp p TA Ambient Temperature with power applied 0 25 70 qC 1 Guaranteed by design DC Digital I O Specifications under normal operating conditions unless otherwise specified Symbol Parameter Conditions Min Typ Max Units VIH High level Inpu...

Page 11: ...tial Input Skew 1 Guaranteed by design 1 0 4 Tbit TCCS Channel to Channel Differential Input Skew1 1 0 Tpixel TIJIT Differential Input Clock Jitter Tolerance2 3 2 Jitter defines as per DVI 1 0 Specification Section 4 6 Jitter Specification 3 Jitter measured with Clock Recovery Unit as per DVI 1 0 Specification Section 4 7 Electronical Measurement Procedures 0 3 Tbit TPDL Delay from OUT_EN Low to H...

Page 12: ...00 ohm 170 200 230 ps SHLT Differential Swing High to Low Transition Time CLOAD 5pF RLOAD 50 ohm REXT_SWING 300 ohm 170 200 230 ps Figure 2 3 Differential Output Timing Definition SLHT SHLT 80 VOD 20 VOD AVDD TX TX 5pF 50ohm VOD ABS TX TX 4 Measured when transmitter was powered down E x p l o r e M i c r o e l e c t r o n i c o n i c s c s s s i c I n c I n I n C o n f i d e n t i a ng Defi g Defi...

Page 13: ...OP sequence Data on SDA must change only when SCL is LOW The standard IIC traffic protocol is illustrated in the following Figure Figure 3 1 IIC Bus Transmission Protocol SCL SDA Start Signal Ack Bit 1 2 3 4 5 6 7 8 MSB LSB 1 2 3 4 5 6 7 8 MSB LSB Stop Signal No SCL SDA 1 2 3 4 5 6 7 8 MSB LSB 1 2 5 6 7 8 MSB LSB Repeated 3 4 9 9 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R W XXX D7 D6 D5 D4 D3 D2 D1 D0 Calling ...

Page 14: ...read from the control registers of the chip in a similar manner Reading requires two data transfer operations The base address must be written with the R W bit of the slave address byte LOW to set up a sequential read operation Reading the R W bit of the slave address byte HIGH begins at the previously established base address The address of the read register auto increments after each byte is tra...

Page 15: ...e Address Byte R W bit LOW Base Address Byte Repeated START Signal Slave Address Byte R W HIGH Data Byte from Base Address STOP Signal Read from Multiple Control Registers START Signal Slave Address Byte R W bit LOW Base Address Byte Repeated START Signal Slave Address Byte R W HIGH Data Byte from Base Address Data Byte from Base Address 1 Data Byte from Base Address 2 Data Byte from Base Address ...

Page 16: ... W TX_AKSV_RDY TX_ENC_ON TX_RPTR TX_RI_RDY TX_ENC_EN 00h 10 R W TX_BKSV_1 XXh 11 R W TX_BKSV_2 XXh 12 R W TX_BKSV_3 XXh 13 R W TX_BKSV_4 XXh 14 R W TX_BKSV_5 XXh 15 R W TX_AN_1 XXh 16 R W TX_AN_2 XXh 17 R W TX_AN_3 XXh 18 R W TX_AN_4 XXh 19 R W TX_AN_5 XXh 1A R W TX_AN_6 XXh 1B R W TX_AN_7 XXh 1C R W TX_AN_8 XXh 1D R TX_AKSV_1 XXh 1E R TX_AKSV_2 XXh 1F R TX_AKSV_3 XXh 20 R TX_AKSV_4 XXh E x p l o ...

Page 17: ...Bcaps 91h 51 W RX_Bstatus 7 0 00h 52 W RX_Bstatus 11 8 00h 60 W RX_SHA 1_HASH_0 XXh 61 W RX_SHA 1_HASH_1 XXh 62 W RX_SHA 1_HASH_2 XXh 63 W RX_SHA 1_HASH_3 XXh 64 W RX_SHA 1_HASH_4 XXh 65 W RX_SHA 1_HASH_5 XXh 66 W RX_SHA 1_HASH_6 XXh 67 W RX_SHA 1_HASH_7 XXh 68 W RX_SHA 1_HASH_8 XXh 69 W RX_SHA 1_HASH_9 XXh E x p l o r e r r e r r e l o E x p M i M i c r o e l e c t r o n i c RX RX n i c s RX_M0_ ...

Page 18: ...d TMDS clock frequency is up to 225MHz 1080p 12 bits deep color The TMDS_SAMP 0 is fixed to 1 always 6A W RX_SHA 1_HASH_10 XXh 6B W RX_SHA 1_HASH_11 XXh 6C W RX_SHA 1_HASH_12 XXh 6D W RX_SHA 1_HASH_13 XXh 6E W RX_SHA 1_HASH_14 XXh 6F W RX_SHA 1_HASH_15 XXh 70 W RX_SHA 1_HASH_16 XXh 71 W RX_SHA 1_HASH_17 XXh 72 W RX_SHA 1_HASH_18 XXh 73 W RX_SHA 1_HASH_19 XXh 80 CF W RX_KSV_FIFO XXh E x p l o o o r...

Page 19: ...mphasis is ON 0 Transmitter Clock Channel Pre emphasis is OFF RX_EQ HDMI Receiver Equalizer Bias Current Control 1 EQ Bias Current is 125uA 0 EQ Bias Current is 100uA RX_BW HDMI Receiver Bandwidth Control 1 2MHz 0 4MHz RX_TERM HDMI Receiver Clock Channel Termination Control 1 Receiver Clock Channel Termination is 100 0 Receiver Clock Channel Termination is 50 This register is recommended to be pro...

Page 20: ...r HDMI signal 1 HDMI 0 DVI RX_ENC_ON Receiver Decryption On This bit indicates whether the HDCP decryption is active at the receiver port 1 HDCP decryption at the receiver port is active 0 HDCP decryption at the receiver port is not active RX_PU Receiver Power Down Control Bit This bit controls the power of the receiver port 1 Normal operation 0 Power down Mode TX_SEL 1 0 Transmitter Port Select f...

Page 21: ...tion 0 Put the selected transmitter port in power down mode 3 3 1 5 Control Register 2 Table 3 6 Control Register 2 09 bit 7 6 5 4 3 2 1 0 R TX_RSEN TX_HTPLG W Reset TX_RSEN Transmitter Analog Output Status Bit The TX_RSEN bit indicates the analog output status at the selected transmitter port 1 The selected transmitter analog outputs are connected to the receiver 0 The selected transmitter analog...

Page 22: ... is selected 3 3 1 7 Control Register 4 Table 3 8 Control Register 4 0E bit 7 6 5 4 3 2 1 0 R TX_EESS TX_HDMI W Reset 0 1 TX_EESS Enable Enhanced Encryption Signalling for the selected transmitter port 1 Using Enhanced Encryption Signalling for the selected transmitter port 0 Using Original Encryption Signalling for the selected transmitter port This is only valid if the selected transmitter is wo...

Page 23: ... be set if the receiver side which is connected to the selected transmitter port is a repeater It should be cleared otherwise 1 The selected transmitter port is connecting to a repeater 0 The selected transmitter port is not connecting to a repeater TX_RI_RDY Transmitter RI Ready This bit indicates that the first Ri value is available for the selected transmitter port This bit is read only 1 First...

Page 24: ... TX_AN_1 is the LSB and TX_AN_8 is the MSB 3 3 1 11 TX_AKSV Registers 1D 21 TX_AKSV_1 TX_AKSV_5 Table 3 12 TX_AKSV Registers 1D 21 bit 7 6 5 4 3 2 1 0 R TX_AKSV1 7 0 TX_AKSV5 7 0 W Reset These 5 registers are read only which hold transmitter s Key Selection Vector for the selected transmitter port TX_AKSV_1 is the LSB and TX_AKSV_5 is the MSB All five bytes should be read from here and then writte...

Page 25: ...ch calculated from HDCP engine These values will be used for SHA calculation 3 3 1 14 RX_M0_RDY Register Table 3 15 RX_M0_RDY Register 40 bit 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 RX_M0_RDY Reset 0 0 0 0 0 0 0 0 The RX_M0_RDY bit will be set to 1 while the last byte of AKSV is written and the HDCP engine completes the M0 calculation 3 3 1 15 RX_M0 Registers 41 48 RX_M0_1 RX_M0_8 Table 3 16 RX_M0 Registe...

Page 26: ...Y READY Bit in HDCP Bcaps register Value written into this bit will reflect to the HDCP Bcaps register bit 5 READY bit FAST FAST Bit in HDCP Bcaps register Value written into this bit will reflect to the HDCP Bcaps register bit 4 FAST bit 1 1_FEATURE 1 1_FEATURE Bit in HDCP Bcaps register Value written into this bit will reflect to the HDCP Bcaps register bit 1 1 1_FEATURE bit This bit shall set t...

Page 27: ...lect to the HDCP Bstatus register bit 10 bit 8 DEPTH 2 0 bit 3 3 1 18 RX_SHA 1_HASH Registers 60 73 These 20 bytes registers are write only The value writes to this register can be read by the upstream source through the DDC link while the HDCP is invoked Table 3 20 HDCP SHA 1 Hash Value Registers Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reset 0x60 RX_SHA 1_HASH_0 xxh 0x61 RX_SHA 1_HASH_1 x...

Page 28: ... xxh 0x82 5 X 1 KSVx 23 16 xxh 0x83 5 X 1 KSVx 31 24 xxh 0x84 5 X 1 KSVx 39 32 xxh NOTE X downstream device count 0x6D RX_SHA 1_HASH_13 xxh 0x6E RX_SHA 1_HASH_14 xxh 0x6F RX_SHA 1_HASH_15 xxh 0x70 RX_SHA 1_HASH_16 xxh 0x71 RX_SHA 1_HASH_17 xxh 0x72 RX_SHA 1_HASH_18 xxh 0x73 RX_SHA 1_HASH_19 xxh Table 3 20 HDCP SHA 1 Hash Value Registers Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reset E x p l...

Page 29: ...0 REF T 0 3 5 7 NOTES 1 DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION ALLOWABLE PROTRUSION IS 0 25mm PER SIDE D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH 7 11 REF 7 11 REF E x E E x p 0 E x p l o 1 35 l o r e 5 e e e r e e r e l o x p E x M M i c NO M i c r o e l e c t r o n i c s c o n i c s n i c n i o o o n o n o n o n n i n i o n n i n i i r o o c t r c t c...

Page 30: ...ide PACKAGE Explore Confidential Proprietary NON DISCLOSURE AGREEMENT REQUIRED 30 E x p l o r e M i c r o e l e c t r o n i c s I n c C o n f i d e n t i a l f o r 南京东平电子 o r I n t e r n a l U s e O n l y ...

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