User Guide — EP9134_UG V0.7
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14
3.2.1 Basic Protocol
For EP9134, there are six components to serial bus operation:
•
START Signal
•
Slave Address Byte
•
Base Register Address Byte
•
Data Byte for Read/Write
•
STOP Signal
•
Repeated Start Signal
When the serial interface is inactive (SCL and SDA are HIGH), communication are initiated by a START
signal which is a HIGH-to-LOW transition on SDA while SCL is HIGH. The first eight bits of data
transferred after a START signal comprising a seven bit slave address (the seven MSB bits) and a single
R/W bit (the LSB bit). The R/W bit indicates the direction of data transfer, "1" means read from device and
"0" means write to device. If the transmitted slave address matches the address of the device, the EP9134
sends the acknowledge by asserting SDA Low on the ninth SCL pulse. Else, the EP9134 does not assert the
acknowledge.
Writing data to specific control registers of the chip requires that the 8-bits address of the control register
is written after the slave address has been acknowledged. This control register address is the base address
for the subsequent write operations. The base address auto-increments by one for each byte of data written
after the data byte intended for the base address. The acknowledge bit will be sent on the ninth SCL pulse
after every 8-bits data received.
Data are read from the control registers of the chip in a similar manner. Reading requires two data transfer
operations:
The base address must be written with the R/W bit of the slave address byte LOW to set up a
sequential read operation.
Reading (the R/W bit of the slave address byte HIGH) begins at the previously established base
address. The address of the read register auto-increments after each byte is transferred.
To terminate a read/write sequence to the chip, a STOP signal must be sent. A STOP signal comprises a
LOW-to-HIGH transition of SDA while SCL is HIGH.
A repeated start signal occurs when the master device driving the serial interface generates a START signal
without first generating a STOP signal to terminate the current read/write sequence. This can be used to
change the mode of communication (read, write) between the slave and master without releasing the bus.
3.2.2 Examples of the read/write sequence
Write to One Control Register
•
START Signal
•
Slave Address Byte (R/W bit = LOW)
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