xr
PRELIMINARY
XRT86VL38
REV. P1.0.6
OCTAL T1/E1/J1 FRAMER/LIU COMBO
56
sor should continue to hold the "Write Strobe" (WR*/R/W*) input pin "low" until it detects the "RDY*/
DTACK* output pin toggling high.
7.
After waiting the appropriate amount of time, for the data (on the bi-directional data bus) to stabilize and
can be safely accepted by the microprocessor. At this time, the XRT86VL38 device will indicate that this
data can be latched into the "target" address location, by toggling the RDY*/DTACK* output pin "low".
8.
After the microprocessor detects the RDY*/DTACK* signal (from the XRT86VL38 device) toggling "low", it
can then terminate the Write Cycle by toggling the WR*/R/W* (Write Strobe) input pin "high".
N
OTE
: Once the user toggles the "WR*/R/W* (Write Strobe) input pin "high", then the Microprocessor Interface (of the
XRT86VL38 device) will latch the contents of the bi-directional data bus (D[7:0]) into the "target" address location
within the chip.
Figure 4presents a timing diagram that illustrates the behavior of the Microprocessor Interface signals, during
an "Intel-Asynchronous" Mode Write Operation.
Figure 5and Table 5present timing information of the XRT86VL38 when the device is configured in Intel
Asychronous mode.
F
IGURE
4. I
NTEL
µP I
NTERFACE
S
IGNALS
D
URING
W
RITE
O
PERATIONS
ALE/AS
A[14:0]
CS*
D[7:0]
WR*/R/W*
Data to be Written
Address of Target Register
RD*/DS*
RDY*/DTACK*
Microprocessor places “target”
Address value on A[14:0]
Microprocessor Interface latches contents on
A[14:0] upon falling edge of ALE
Address Decoding
Circuitry asserts
CS*
Write Operation begins
Here
RDY* toggles “low” to indicates
That valid data can be latched into
“target” Address location of chip
Write Operation is
Terminated Here
RDY* toggles “high” after
Completion of Write
Operation
