XRT86VL38
PRELIMINARY
xr
OCTAL T1/E1/J1 FRAMER/LIU COMBO
REV. P1.0.6
57
3.2
Operating the Microprocessor Interface in the Motorola-Asynchronous Mode
If the Microprocessor Interface has been configured to operate in the Motorola-Asynchronous Mode, then the
following Microprocessor Interface pins will assume the role that is described below in Table below.
F
IGURE
5. I
NTEL
µP I
NTERFACE
T
IMING
D
URING
P
ROGRAMMED
I/O R
EAD
AND
W
RITE
O
PERATIONS
T
ABLE
5: I
NTEL
M
ICROPROCESSOR
I
NTERFACE
T
IMING
S
PECIFICATIONS
S
YMBOL
P
ARAMETER
M
IN
M
AX
U
NITS
t
0
Valid Address to CS Falling Edge
0
-
ns
t
1
CS Falling Edge to RD Assert
65
-
ns
t
2
RD Assert to RDY Assert
-
90
ns
NA
RD Pulse Width (t
2
)
90
-
ns
t
3
CS Falling Edge to WR Assert
65
-
ns
t
4
WR Assert to RDY Assert
-
90
ns
NA
WR Pulse Width (t
4
)
90
-
ns
CS
ADDR[14:0]
ALE = 1
DATA[7:0]
RD
WR
RDY
Valid Data for Readback
Data Available to Write Into the LIU
READ OPERATION
WRITE OPERATION
t
0
t
0
t
1
t
4
t
2
t
3
Valid Address
Valid Address
