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XRT83SL38/L38EVAL User Manual

Page 10 of 23

Figure 11 XRT83SL38/L38EVAL Layout Plot-Ground Plane

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Summary of Contents for XRT83SL38/L38EVAL

Page 1: ...XRT83SL38 L38EVAL User Manual Page 1 of 23 XRT83SL38 L38EVAL EVALUATION SYSTEM USER MANUAL...

Page 2: ...long haul short haul line interface unit for T1 E1 or J1 applications This application board combines a proven PC board layout with optimized analog and digital interface circuitry The XRT83SL38 L38E...

Page 3: ...ied block diagram of the CPLD interface CPLD XRT83SL38 XRT83L38 LIU 25 DIN Connector 5 Parallel Port Cable A 7 0 D 7 0 INT PCLK ALE RST HW HOSTB CS WR RD RDY PC Figure 2 Simplified Block Diagram of th...

Page 4: ...83SL38 L38 LIU 100 1 2 1 1 Figure 4 Simplified Block Diagram of the External Mode T1 J1 External Impedance Mode E1 2 048MHz 75ohm or 120ohm The XRT83SL38 L38EVAL can be programmed for external impedan...

Page 5: ...2 R2 470 TAOS0 CLKSEL0 TxTSEL R3 470 TxON4 3V_SUP 3V_RVDD CODES0 TAOS3 TxON7 TxON5 P1 DB25 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 C3 0 1uF RxTSEL TEST EXAR AD Infinitum TxO...

Page 6: ...163 162 169 170 171 172 RLOS0 RLOS1 RLOS2 RLOS3 RCLK0 RCLK1 RCLK2 RCLK3 RNEG0_LCV0 RNEG1_LCV1 RNEG2_LCV2 RNEG3_LCV3 RPOS0 RPOS1 RPOS2 RPOS3 RTIP0 RTIP1 RTIP2 RTIP3 RRING0 RRING1 RRING2 RRING3 TTIP0 TT...

Page 7: ...9 1 J12 RJ48 1 2 3 4 5 6 7 8 9 10 Tx 1 2 Rx 1 1 CODES4 U1C XRT83SL38 L38 55 31 126 102 54 32 125 103 53 33 124 104 52 34 123 105 50 36 121 107 49 37 120 108 46 40 117 111 44 42 115 113 57 60 97 100 56...

Page 8: ...XRT83SL38 L38EVAL User Manual Page 8 of 23 Figure 9 XRT83SL38 L38EVAL Layout Plot Top Silk Screen...

Page 9: ...XRT83SL38 L38EVAL User Manual Page 9 of 23 Figure 10 XRT83SL38 L38EVAL Layout Plot Top Layer...

Page 10: ...XRT83SL38 L38EVAL User Manual Page 10 of 23 Figure 11 XRT83SL38 L38EVAL Layout Plot Ground Plane...

Page 11: ...XRT83SL38 L38EVAL User Manual Page 11 of 23 Figure 12 XRT83SL38 L38EVAL Layout Plot Power Plane...

Page 12: ...XRT83SL38 L38EVAL User Manual Page 12 of 23 Figure 13 XRT83SL38 L38EVAL Layout Plot Bottom Layer...

Page 13: ...38 Evaluation Board to the PC When the XRT83SL38 L38 Evaluation Board is operating in the Host Mode the user will exercise command and control over the Evaluation Board via a PC which is executing the...

Page 14: ...ard GUI Software the PC monitor should be display the Start up Window as depicted below in Figure 14 Figure 14 The Start Up Window within the XRT83SL38 L38 Evaluation Board GUI Software Figure 14 indi...

Page 15: ...Each of these options are discussed in detail below Port Setup The Port Setup option permits the user to select the address where the parallel port is located The default address is 0x378 A check mark...

Page 16: ...pull down menu fully visible Figure 16 Illustration of the Tests Pull down Menu Figure 16 indicates that the Tests option only consists of the Evaluation Board Test option Once the user selects this...

Page 17: ...XRT83SL38 L38EVAL User Manual Page 17 of 23 Figure 17 Illustration of Host Mode Test Dialog Box Figure 18 Illustration of Host Mode Test Dialog Box...

Page 18: ...down Menu Figure 19 presents an illustration of the Start up window with the Help pull down menu fully visible Figure 19 Illustration of the Help Pull down Menu Figure 19 indicates that the Help opti...

Page 19: ...the Host Mode Test Dialog Box The following sections explain the options and features associated with the Host Mode Test Dialog Box Figure 20 Illustration of the Host Mode Test Dialog Box Figure 20 i...

Page 20: ...and external line termination modes for the receiver Tx Termination selects between the internal and external line termination modes for the transmitter Transformer Ratio in external termination mode...

Page 21: ...or loop down code AIS indicates an All Ones Signal is detected by the receiver RLOS indicates that the receive input signal is lost QRPD indicates the receiver is currently in synchronization with QRS...

Page 22: ...ia the Hardware Mode Test Dialog Box The following sections explain the options and features associated with the Host Mode Test Dialog Box Figure 21 Illustration of the Hardware Mode Test Dialog Box F...

Page 23: ...d the place the Jitter Attenuator in Transmit Receive Path or to disable it Rx Resistor setting allows the user to set the external Receive fixed resistor to one of te following values none 60 ohms 52...

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