EUROCOM D220S, Service Manual, Page: 90 / 113

Schematic Diagrams
650-3 (HyperZip/VGA/Misc) - 3 of 4 (71-M2200-D06) B - 9
Schematic Diagrams
650-3 (HyperZip/VGA/Misc) - 3 of 4
+5VS
+3VS
+1.8VS
+1.8VS
+3VS
+3VS
+1.8VS
+1.8VS +1.8VS +1.8VS
+5VS +5VS
+3VS
+3VS
+5VS +5VS
INTA# [10,11]
ZAD[0..15] [11]
ZSTB[0..1] [11]
ZSTB-[0..1] [11]
PCIRST#[10,11,15,16,17,18,19,20,21]
PWRGD[12,13]
REFCLK0 [3]
ZCLK0 [3]
ZUREQ [11]
ZDREQ [11]
AUXOK [12,20,26,27]
REFCLK0
GOUT
BOUT
Z0801 HSYNC
Z0802 VSYNC
DDC1CLK
DDC1DATA
INTA#
Z1XAVDD
DDC1DATA
CSYNC
RSYNC
LSYNC
ZSTB[0..1]
ZSTB-[0..1]
ZAD[0..15]
RSYNC PWRGD
AUXOK
ENTEST
FGRN
Z0804
Z0803
Z0805
VS
DDC1CLK
GOUT
ZAD10
ZSTB0
ZAD12
ZAD6
ZSTB-0
ZAD8
ZSTB-1
ZCMP_P
ZAD15
ZCLK0
ZAD14
ZAD9
ZAD1
ZAD0
ZUREQ
ZDREQ
ZAD7
ZVREF
ZAD2
ZAD13
ZAD11
ZAD5
ZAD3
ZSTB1
ZAD4
HS
DDCDC
TRAP1
TRAP0
TMODE2
TMODE1
TMODE0
DLLEN-
ENTEST
ECLKAVSS
ECLKAVDD
DCLKAVDD
VVBWN
DACAVSS
VRSET
DACAVDD
VCOMP
GOUT
BOUT
HS DDCDC VS
Z0803
Z1XAVSS
Z4XAVSS
Z4XAVDD
DDCDA
DDCDA
TZ0802
TZ0801
ZCMP_N
VDDZCMP
VSSZCMP
Z0803
Z0803
Z0803
HSYNC
VSYNC
FRED
ROUT
ROUT
ROUT
FBLU
BOUT
L2 BK2125HS121
L3 BK2125HS121
L5 BK2125HS121
L4 BK2125HS121
L7 BK2125HS121
L6 BK2125HS121
L8 BK2125HS121
N5
L23
BK1608HS121
1 2
C114
0.01UF
C111
0.01UF
D1 RB751V
A C
N1
L11
BK1608HS121
1 2
L9
BK1608HS121
1 2
L10
BK1608HS121
1 2
N2
C295
22PF
C154 0.1UF
C153 0.1UF
C374
10UF/16V
C92
0.1UF
C89
0.01UF
C403
0.1UF
C103
0.1UF
C5
22PF
C23
22PF
C294
22PF
C308
1000PF
C306
1000PF
C305
220PF
C307
220PF
C24
22PF
C2
0.1UF
C317
10UF/16V
C318
10UF/16V
C10
0.1UF
C9
0.01UF
C11
0.01UF
C12
0.1UF
C22
22PF
R25
75
R207
2.2K
R26
75
R27
75
C1
0.1UF
C13
0.1UF
C14
1UF
C315
10UF/16V
R1
130 1%
R22 4.7K
R3 4.7K
R263
56
R68
150 1%
R72
150 1%
R4
33
R5
33
T132
T13
T118
T24
T125
T129
T5
T135
D3
BAV99
C
AC
A
R9
4.7K(R)
R11
4.7K(R)
R10 100
R8 100
T11
T140
C450
10UF/16V
C115
0.1UF
L27
BK1608HS121
1 2
D13
BAV99
C
AC
A
D5
BAV99
C
AC
A
D14
BAV99
C
AC
A
D4
BAV99
C
AC
A
D2
BAV99
C
AC
A
R258
56
R208
2.2K
D15
BAV99
C
AC
A
C425
10UF/16V
L26
BK1608HS121
1 2
N7
C128
0.1UF
N6
CN4
CRT CON
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
U6C
SIS650
C15
A12
B13
A13
F13
E13
D13
D12
B11
E12
A11
F12
E14
D14
F14
B12
C12
C13
C14
B15
A15
B14
A14
F10
E11
C11
F11
A10
D11
E10
Y3
W4
W6
V2
V1
W1
W2
V5
U4
U2
V6
U3
T4
R3
T5
T6
R2
R6
R1
R4
P4
N3
P5
P6
N1
N6
N2
N4
P1
P3
T3
T1
U6
U1
V3
VOSCI
ROUT
GOUT
BOUT
HSYNC
VSYNC
VGPIO0
VGPIO1
INT#A
CSYNC
RSYNC
LSYNC
VCOMP
VRSET
VVBWN
DACAVDD1
DACAVSS1
DACAVDD2
DACAVSS2
DCLKAVDD
DCLKAVSS
ECLKAVDD
ECLKAVSS
ENTEST
DLLEN#
TESTMODE0
TESTMODE1
TESTMODE2
TRAP1
TRAP0
PCIRST#
PWROK
AUXOK
Z4XAVDD
Z4XAVSS
Z1XAVDD
Z1XAVSS
VDDZCMP
ZCMP_N
ZCMP_P
VSSZCMP
ZVREF
ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15
ZSTB1
ZSTB#1
ZSTB0
ZSTB#0
ZUREQ
ZDREQ
ZCLK
T2
T92
650-3
VGA
HyperZip
DLLEN#
DRAM_SEL
TRAP0
TRAP1
SDR
LSYNC
CSYNC
RSYNC
1(DDR)
(30~50K Ohm) Default
DDR
0
1
0
embedded pull-low
0
0 yes
disable PLL
yes
1
NB debug mode
0
yes
0
normal
NOTE: This page is for universal PCB design( suitable for both 645 or 650)
NB Hardware Trap Table
enable panel link
enable VGA interface
enable PLL
TV selection, NTSC/PAL(0/1)
enable VB
NEAR SIS650
1 2
3
SOT-23
BAV99
AS SIS AP NOTE
A650-0-003
35.4mA
6.49mA
7.92mA
84.8mA
7.57mA
18.07mA
20MIL
10MIL
10MIL
10MIL
20MIL
20 mil
20 mil
20 mil
20 mil
20 mil
20 mil
20 mil
20 mil
Sheet 8 of 31
650-3
(HyperZip/VGA/
Misc)
3 of 4