Epson SED 1520 Series Technical Manual Download Page 23

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SED1520 Series

2–14

EPSON

Code

Command

RD WR

Display On/OFF

0/1

Display start line

Display start address (0 to 31)

Set page address

Page (0 to 3)

Set column

Column address (0 to 79)

(segment) address

Read status

Busy

ADC ON/OFF Reset

Write display data

Write data

Read display data

Read data

Select ADC

0/1

Statis drive

0/1

ON/OFF

Select duty

0/1

Read-Modify-Write

End

Reset

Function

Turns display on or off.

1: ON, 0: OFF

Specifies RAM line corresponding to top line

of display.

Sets display RAM page in page address

Sets display RAM column address in

column address register.

Reads the following status:

BUSY

1: Busy

0: Ready

ADC

1: CW output

0: CCW output

ON/OFF

1: Display off

0: Display on

RESET

1: Being reset

0: Normal

Writes data from data bus into display RAM.

Reads data from display RAM onto data

bus.

0: CW output, 1: CCW output

Selects static driving operation.

1: Static drive, 0: Normal driving

Selets LCD duty cycle

1: 1/32, 0: 1/16

Read-modify-write ON

Read-modify-write OFF

Software reset

COMMANDS

Summary

Summary of Contents for SED 1520 Series

Page 1: ...SED1520Series LCD driver with RAM Technical Manual ...

Page 2: ...l property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law o...

Page 3: ...CONTENTS Selection Guide 1 SED1510 Series 2 SED1520 Series 3 SED152A Series 4 SED1526 Series 5 SED1530 Series 6 SED1540 Series 7 SED1560 Series 8 SED1565 Series 9 SED1570 Series ...

Page 4: ...SED1500 Series Selection Guide ...

Page 5: ...A SED1522DAB SED1522FAA SED1522FAC SED1522TAA SED1540D0A SED1540D0B 3 5 11 1 3 1 4 73 3 4 SED1540F0A 18 internal 18 internal external 2 external 18 external 2 external 18 internal external 2 external 18 internal 4 external AI pad chip Au bump chip QFP12 48pin QFP6 60pin AI pad chip AI pad chip Au bump chip QFP5 100pin QFP15 100pin TCP AI pad chip Au bump chip QFP5 100pin QFP15 100pin TCP AI pad ch...

Page 6: ...2T0B 1 5bias SED1562TQA 8 bit parallel SED1565D0B or Serial SED1565D1B SED1565D2B 1 65 65 SED1565T0A 1 7 1 9 bias SED1565T0B SED1565T0C SED1566D0B SED1566D1B 1 49 49 132 65 SED1566D2B 1 8 5 5 4 5 16 0 1 6 1 8 bias 132 bits SED1566T0A SED1567D0B SED1567D1B 1 33 SED1567D2B 1 5 1 6 bias 33 SED1567T0B SED1567T0C SED1568D0B 1 55 1 6 1 8 bias 55 SED1569D0B 1 53 53 SED1569T 1 6 1 8 bias SED1570D0A 2 7 5 ...

Page 7: ...T0A 2 4 6 0 4 5 16 0 bits or Serial SED1532D0A SED1532DBA 1 64 1 65 SED1532D0B 100 33 SED1532DBA SED1532T0A SED1532TBA SED1535D0B 1 35 98 35 Part number Duty Display RAM bits Microprocessor interface Frequency KHz Package Application additional features LCD voltage range V Supply voltage range V Segment Common Built in power circuit for LCD voltage quadrupler SED153 0 Common Right side SED153 A Co...

Page 8: ...2 SED1520 Series ...

Page 9: ...rs 2 9 Column Address Counter 2 9 Page Register 2 9 Display Data RAM 2 9 Common Timing Generator Circuit 2 10 Display Data Latch Circuit 2 10 LCD Driver Circuit 2 10 Display Timing Generator 2 10 Oscillator Circuit SED1520 0A Only 2 11 Reset Circuit 2 11 COMMANDS 2 14 Summary 2 14 Command Description 2 15 SPECIFICATIONS 2 20 Absolute Maximum Ratings 2 20 Electrical Specifications 2 20 APPLICATION ...

Page 10: ...hich is able to drive one line of thirteen characters each Line up FEATURES Fast 8 bit MPU interface compatible with 80 and 68 family microcomputers Many command set Total 80 segment common drive sets Low power 30 µW at 2 kHz external clock Wide range of supply voltages VDD VSS 2 4 to 7 0 V VDD V5 3 5 to 13 0 V Low power CMOS Package code For example SED1520 SED1520T SED1520F PKG SED1520F A QFP5 1...

Page 11: ...coder Column address decoder Column address counter Column address register Status Command decoder Display timing generator circuit MPU interface I O buffer Display data RAM 2560 bit Low address register Bus holder CL FR D 0 D 7 E R W COM 0 to COM 15 V 1 V 2 V 3 V 4 V 5 SEG 0 to SEG 60 RD WR V DD V SS RES M S BLOCK DIAGRAM An example of SED1520 AA ...

Page 12: ...0 85 90 95 COM12 SEG0 COM13 SEG1 COM14 SEG2 COM15 SEG3 SEG60 SEG4 SEG59 SEG5 SEG58 SEG6 SEG57 SEG7 SEG56 SEG8 SEG55 SEG9 SEG54 SEG10 SEG53 SEG11 SEG52 SEG12 SEG51 SEG13 SEG50 SEG14 SEG49 SEG15 SEG48 SEG16 SEG47 SEG17 SEG46 SEG18 SEG21 D30 SEG22 D31 SEG23 D32 SEG24 D33 SEG25 D34 SEG26 D35 SEG27 D36 SEG28 D37 SEG29 VDD SEG30 RES SEG31 F R SEG32 V5 SEG33 V3 SEG34 V2 SEG35 M S SEG36 V4 SEG37 V1 SEG38 ...

Page 13: ... bump package Chip size 4 80 7 04 0 525 mm Bump pitch 199 µm Min Bump height 22 5 µm Typ Bump size 132 111 µm 20 µm for mushroom model 116 92 µm 4 µm for vertical model Note An example of SED1520DAA die numbers is given These numbers are the same as the bump package 100 95 90 85 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 D1520D AA X Y 4 80 mm 7 04 mm 0 0 ...

Page 14: ...G28 3098 159 45 SEG27 3297 159 46 SEG26 3497 159 47 SEG25 3696 159 48 SEG24 3896 159 49 SEG23 4095 159 50 SEG22 4295 159 51 SEG21 4641 482 52 SEG20 4641 681 53 SEG19 4641 881 54 SEG18 4641 1080 55 SEG17 4641 1280 56 SEG16 4641 1479 57 SEG15 4641 1679 58 SEG14 4641 1878 59 SEG13 4641 2078 60 SEG12 4641 2277 61 SEG11 4641 2477 62 SEG10 4641 2676 63 SEG9 4641 2876 64 SEG8 4641 3075 65 SEG7 4641 3275 ...

Page 15: ...nterface type to the 68 series or 80 series MPU is selected by the level input as follows High level 68 series MPU interface Low level 80 series MPU interface CS Input Active low Effective for an external clock operation model only An address bus signal is usually decoded by use of chip select signal and it is entered If the system has a built in oscillator this is used as an input pin to the osci...

Page 16: ...n of display RAM contents and RF signal 1 0 1 0 1 0 V V2 V5 V3 DD FR signal Data Output level COMn Output The output pin for LCD common low driving A single level of VDD V1 V4 and V5 is selected by the combination of common counter output and RF signal The slave LSI has the reverse common output scan sequence than the master LSI 1 0 1 0 1 0 V V1 V5 V4 DD FR signal Counter output Output level M S I...

Page 17: ...ansfer data between the system MPU and internal registers The combina tions used are given in the table blow In order to match the timing requirements of the MPU with those of the display data RAM and control registers all data is latched into and out of the driver This introduces a one cycle delay between a read request for data and the data arriving For example when the MPU executes a read cycle...

Page 18: ...the current line of data in display data RAM being transferred to the segment driver circuits Column Address Counter The column address counter is a 7 bit presettable counter that supplies the column address for MPU access to the display data RAM See Figure 2 The counter is incremented by one every time the driver receives a Read or Write Display Data command Addresses above 50H are invalid and th...

Page 19: ...Display Data Latch Circuit This latch stores one line of display data for use by the LCD driver interface circuitry The output of this latch is controlled by the Display ON OFF and Static Drive ON OFF commands LCD Driver Circuit The LCD driver circuitry generates the 80 4 level signals used to drive the LCD panel using output from the display data latch and the common timing generator circuitry Di...

Page 20: ...clock Reset Circuit Detects a rising or falling edge of an RES input and initializes the MPU during power on Initialization status 1 Display is off 2 Display start line register is set to line 1 3 Static drive is turned off 4 Column address counter is set to address 0 5 Page address register is set to page 3 6 1 32 duty SED1520 or 1 16 duty SED1522 is selected 7 Forward ADC is selected ADC command...

Page 21: ...05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F H Column address ADC D0 1 D0 0 SEG pin SEG 0 4F H 00 H 1 2 3 4 5 6 7 4E 4D 4C 4B 4A 49 48 01 02 03 04 05 06 07 77 78 79 02 01 00 4D 4E 4F D 0 D D D D D D D 1 2 3 4 5 6 7 DATA Page address D 1 D 2 0 0 0 1 1 0 1 1 Page 0 Page 1 Page 2 Page 3 Start line Example Response D 0 D D D D D D D 1 2 3 4 5 6 7 D 0 D D D D D D D 1...

Page 22: ...3 SEG4 0 1 2 3 15 0 0 0 1 2 3 1 1 2 2 3 3 31 15 31 FR COM0 COM1 COM2 SEG0 SEG1 COM0 SEG0 COM0 SEG1 V V V V1 V2 V3 V4 V5 V1 V2 V3 V4 V5 V5 V4 V3 V2 V1 V1 V2 V3 V4 V5 DD SS DD VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 VDD VDD V5 V4 V3 V2 V1 V1 V2 V3 V4 V5 VDD 1 5 bias 1 16 duty 1 6 bias 1 32 duty Figure 4 LCD drive waveforms example ...

Page 23: ...odify Write 0 1 0 1 1 1 0 0 0 0 0 End 0 1 0 1 1 1 0 1 1 1 0 Reset 0 1 0 1 1 1 0 0 0 1 0 Function Turns display on or off 1 ON 0 OFF Specifies RAM line corresponding to top line of display Sets display RAM page in page address register Sets display RAM column address in column address register Reads the following status BUSY 1 Busy 0 Ready ADC 1 CW output 0 CCW output ON OFF 1 Display off 0 Display...

Page 24: ...the specified display duty is displayed If the line address is changed dynamically by this command the vertical smooth scrolling and paging can be used This command loads the display start line register See Figure 2 Set Page Address This command specifies the page address that corresponds to the low address of the display data RAM when it is accessed by the MPU Any bit of the display data RAM can ...

Page 25: ... addresses are assigned to segment drivers ADC 1 Normal Column address n segment driver n ADC 0 Inverted Column address 79 u segment driver u The ON OFF bit indicates the current status of the display It is the inverse of the polarity of the display ON OFF command ON OFF 1 Display OFF ON OFF 0 Display ON The RESET bit indicates whether the driver is executing a hardware or software reset or if it ...

Page 26: ... a table of segments and column addresses for the two values of D Static Drive ON OFF Forces display on and all common outputs to be selected D 1 Static drive on D 0 Static drive off Select Duty This command sets the duty cycle of the LCD drive and is only valid for the SED1520F and SED1522F It is invalid for the SED1521F which performs passive operation The duty cycle of the SED1521F is determine...

Page 27: ...at a specific display area such as cursor blinking Any command other than Data Read or Write can be used in the Read Modify Write mode However the Column Address Set command cannot be used Set Page Address Set Column Address Read Modify Write Dummy Read Read Data Write Data Completed End No Yes End This command cancels read modify write mode and restores the contents of the column address register...

Page 28: ...DD level b The external oscillation clock input is inhibited and the OSC2 is set to the floating mode c The display and operation modes are kept The Power Save mode is released when the display is turned ON or when the static drive is turned OFF If the LCD drive voltage is supplied from an external resistance divider circuit the current passing through this resistor must be cut by the Power Save s...

Page 29: ...are should be taken to avoid thermally stressing the package during board assembly Electrical Specifications DC Characteristics Ta 20 to 75 deg C VDD 0 V unless stated otherwise Rating Parameter Symbol Condition Unit Applicable Pin Min Typ Max Operating Recommended 5 5 5 0 4 5 voltage 1 VSS V VSS See note 1 Allowable 7 0 2 4 Recommended 13 0 3 5 V5 V5 V Operating Allowable 13 0 See note 10 voltage...

Page 30: ...ns Rf 1 0 MΩ 2 15 18 21 VSS 5 0 V Oscillation frequency fOSC kHz See note 9 Rf 1 0 MΩ 2 11 16 21 VSS 3 0 V RES Reset time tR 1 0 µS See note 15 Notes 1 Operation over the specified voltage range is guaranteed except where the supply voltage changes suddenly during CPU access 2 A0 D0 to D7 E or RD R W or WR and CS 3 CL FR M S and RES 4 D0 to D7 5 FR 6 A0 E or RD R W or WR CS CL M S and RES 7 When D...

Page 31: ...Ta 25 C V 5V SS kHz fosc V 3V SS V 5V SS 200 100 0 0 5 1 0 1 5 2 0 2 5 SED1520 SED1522 Rf OSC1 OSC2 Hz Frame Rf M Ω M Ω Rf Same for 1 16 and 1 32 duties Figure 5 a Figure 5 b Relationship between external clocks fCL and frames SED1520FAA SED1522FAA 200 100 0 1 2 3 f CL kHz Hz Frame duty1 32 duty1 16 duty1 8 Figure 5 c 10 Operating voltage range of VSS and V5 systems 15 10 5 0 2 4 6 8 V V 5 VSS V O...

Page 32: ...0 to D7 RD access time tACC8 90 ns CL 100 pF Output disable time tCH8 10 60 ns Rise and fall time tr tf 15 ns VSS 2 7 to 4 5 V Ta 20 to 75 C Rating Parameter Symbol Condition Unit Signal Min Max Address hold time tAH8 20 ns A0 CS Address setup time tAW8 40 ns System cycle time tCYC8 2000 ns WR RD Control pulse width tCC 400 ns Data setup time tDS8 160 ns Data hold time tDH8 20 ns D0 to D7 RD acces...

Page 33: ...W E pulsewidth Write 80 ns Rise and fall time tr tf 15 ns VSS 2 7 to 4 5 V Ta 20 to 75 C Rating Parameter Symbol Condition Unit Signal Min Max System cycle time 1 tCYC6 2000 ns Address setup time tAW6 40 ns A0 CS R W Address hold time tAH6 20 ns Data setup time tDS6 160 ns Data hold time tDH6 20 ns D0 to D7 Output disable time tOH6 20 120 ns CL 100 pF Access time tACC6 180 ns Enable Read 200 ns tE...

Page 34: ... pulse width tWLCL 70 µs High level pulse width tWHCL 70 µs CL Rise time tr 60 300 ns Fall time tf 60 300 ns FR delay time tDFR 4 0 0 4 4 0 µs FR Note The listed input tDFR applies to the SED1520 and SED1521 and SED1522 in slave mode Output Ta 20 to 75 deg C VSS 5 0 V 10 unless stated otherwise Rating Parameter Symbol Condition Unit Signal Min Typ Max FR delay time tDFR CL 100 pF 0 2 0 4 µs FR VSS...

Page 35: ...SED1520 Series 2 26 EPSON APPLICATION NOTES MPU Interface Configuration 80 Family MPU RESET VDD VCC V5 VSS SED1520FAA GND MPU Decoder RES WR RD D0 to D7 CS A0 RES WR RD D0 to D7 A1 to A7 IOQR A0 ...

Page 36: ...21F0A See note 1 SED1522F0A To LCD SEG To LCD COM OSC1 OSC2 FR OSC1 OSC2 FR Master Slave SED1520F0A SED1520F0A M S To LCD COM VDD Rf VSS To LCD SEG M S To LCD SEG To LCD COM CL FR CL FR Master External clock Slave SED1520FAA SED1520FAA M S To LCD COM VDD VSS To LCD SEG M S To LCD SEG To LCD COM OSC1 OSC2 FR OSC1 OSC2 FR Master Slave SED1520F0A SED1521F0A M S VDD Rf 2 To LCD SEG ...

Page 37: ...1FAA Notes 1 The duty cycle of the slave must be the same as that for the master 2 If a system has two or more slave drivers a CMOS buffer will be required To LCD SEG To LCD COM CL FR CL FR External clock SED1520FAA SED1521FAA M S VDD To LCD SEG ...

Page 38: ...y 23 characters 2 lines LCD 16 141 1 16 1 61 62 141 SEG SEG SED1520F SED1521F COM 1 32 duty 33 characters 4 lines 1 16 1 61 62 141 142 202 17 32 COM SEG SEG SEG SED1520F SED1521F SED1520F COM LCD 32 202 The SED1521F can be omitted the 32 122 dot display mode is selected Note A combination of AB or AA type chip that uses internal clocks and 0B or 0A type chip that uses external clocks is NOT allowe...

Page 39: ...0 0 1 0 551 0 004 14 0 1 0 772 0 016 19 6 0 4 Index 1 008 0 016 25 6 0 4 0 787 0 004 20 0 1 0 059 0 012 1 5 0 3 0 006 0 002 0 15 0 05 0 106 0 004 2 7 0 1 1 0 12 75 50 76 25 51 26 100 Index 0 007 0 004 0 18 0 1 0 020 0 004 0 5 0 1 0 005 0 002 0 127 0 05 0 055 0 004 1 4 0 1 0 630 0 016 16 0 0 4 0 551 0 004 14 0 0 1 0 020 0 004 0 5 0 2 0 039 1 0 0 630 0 016 16 0 0 4 0 551 0 004 14 0 0 1 ...

Page 40: ...pecifications Base U rexS 75µm Copper foil Electrolytic copper foil 35µm Sn plating Product pitch 81P 28 5mm Solder resist positional tolerance 0 3 Output terminal pattern shape Mold marking area Mold marking area Punching hole for good product ...

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