3 FUNCTION OPTION GENERATOR FOG6008
16
EPSON
S5U1C60N08D MANUAL
(DEVELOPMENT SOFTWARE TOOL FOR S1C60N08)
14 SOUT specification
*** OPTION NO.14 ***
--- SOUT SPECIFICATION ---
SOUT SPECIFICATION
1. COMPLEMENTARY
2. P-CH OPEN DRAIN
PLEASE SELECT NO.(1) ? 1
SOUT SPECIFICATION 1. COMPLEMENTARY SELECTED
Select the output specification for the SOUT
terminal.
Either complementary output or Pch open drain
output may be selected.
Select complementary output if the SOUT terminal
will not be used.
15 SCLK specification
*** OPTION NO.15 ***
--- SCLK SPECIFICATION ---
SCLK PULL DOWN RESISTOR
1. WITH RESISTOR
2. GATE DIRECT
PLEASE SELECT NO.(1) ? 1
OUTPUT SPECIFICATION
1. COMPLEMENTARY
2. P-CH OPEN DRAIN
PLEASE SELECT NO.(1) ? 1
LOGIC
1. POSITIVE
2. NEGATIVE
PLEASE SELECT NO.(1) ? 1
SCLK PULL DOWN RESISTOR 1. WITH RESISTOR SELECTED
OUTPUT SPECIFICATION 1. COMPLEMENTARY SELECTED
LOGIC 1. POSITIVE SELECTED
16 SIO data permutation
*** OPTION NO.16 ***
--- SIO DATA PERMUTATION ---
SIO DATA PERMUTATION
1. MSB FIRST
2. LSB FIRST
PLEASE SELECT NO.(1) ? 1
SIO DATA PERMUTATION 1. MSB FIRST SELECTED
Select the pull down resistor, output specification
and logic for the SCLK terminal (input/output
terminal of the SIO synchronous clock).
Pull down resistor is only available when the clock
mode is set at external clock mode.
Select with pull down resistor, complementary
output, and positive logic it the SCLK terminal will
not be used.
The SCLK timing chart is shown in Figure 3.3.8.
Select whether the SIO input/output (SIN or
SOUT) data bit permutation will be MSB first or
LSB first.
Select one suitable for your programming needs.
Input/output data permutation is shown in Figure
3.3.9.
Fig. 3.3.8 SCLK timing chart
Negative
Positive
SIN
SIN
Address [2F1H]
Address [2F0H]
Address [2F1H]
Address [2F0H]
Output
latch
SOUT
SOUT
SD3 SD2 SD1 SD0
SD4 SD5 SD6 SD7
SD7 SD6 SD5 SD4
SD0 SD1 SD2 SD3
Output
latch
(In case of LSB first)
(In case of MSB first)
Fig. 3.3.9 Input/output data permutation
17 Event counter noise rejector
*** OPTION NO.17 ***
--- EVENT COUNTER NOISE REJECTOR ---
EVENT COUNTER NOISE REJECTOR
1. 2048 OR 2400 HZ
2. 256 OR 300 HZ
PLEASE SELECT NO.(1) ? 1
EVENT COUNTER NOISE REJECTOR 1. 2048 OR 2400 HZ SELECTED
The system is equipment with built-in noise
rejector to prevent operational errors by the event
counter caused by noise and chattering in the K02
and K03 terminals.
Either 2,048 (or 2,400) Hz or 256 (or 300) Hz may
be selected as the sampling frequency.
Select one suitable for the input signal.
Summary of Contents for S5U1C60N08D
Page 4: ......
