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Epson S1D13505, Technical Manual

The Epson S1D13505 Technical Manual provides comprehensive instructions and detailed information on operating and troubleshooting the Epson S1D13505 product. Available for free download on our website, this manual equips users with a valuable resource to enhance their experience and maximize the potential of their Epson S1D13505.

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Page 106

Epson Research and Development

Vancouver Design Center

S1D13505

Hardware Functional Specification

X23A-A-001-14

Issue Date: 01/02/02

8.2.4   Display Configuration Registers

bit 7

SwivelView Enable 
When this bit = 1, all CPU accesses to the display buffer are translated to provide clockwise 90° 
hardware rotation of the display image. Refer to “Section 13 SwivelView” for application and limi-
tations.

bits 6-5

Simultaneous Display Option Select Bits [1:0]
These bits are used to select one of four different simultaneous display mode options: Normal, Line 
Doubling, Interlace, or Even Scan Only. The purpose of these modes is to manipulate the vertical 
resolution of the image so that it fits on both the CRT, typically 640x480, and LCD. The following 
table describes the four modes using a 640x480 CRT as an example:

Note

1.  Dual Panel Considerations: When configured for a dual LCD panel and using 

Simultaneous Display, the Half Frame Buffer Disable, REG[1Bh] bit 0, must be set to 1. 
This results in a lower contrast on the LCD panel, which may require adjustment.

2. The Line doubling option is not supported with dual panel.

Display Mode Register 

REG[0Dh]

RW

SwivelView 
Enable

Simultaneous
Display 
Option Select 
Bit 1

Simultaneous
Display 
Option Select 
Bit 0

Bit-per-pixel 
Select Bit 2

Bit-per-pixel 
Select Bit 1

Bit-per-pixel 
Select Bit 0

CRT Enable

LCD Enable

Table 8-6: Simultaneous Display Option Selection

Simultaneous 

Display Option 

Select Bits [1:0]

Simultaneous 

Display Mode

Mode Description

00

Normal

The image is not manipulated. This mode is used when the CRT and LCD have the same 
resolution, e.g. 480 lines. 

It is necessary to suit the vertical retrace period to the CRT. This results in a lower LCD 
duty cycle 

(

1/525 compared to the usual 1/481). This reduced duty cycle may result in 

lower contrast on the LCD.

01

Line Doubling

Each line is replicated on the CRT. This mode is used to display a 240-line image on a 
240-line LCD and stretch it to a 480-line image on the CRT. The CRT has a heightened 
aspect ratio. 

It is necessary to suit the vertical retrace period to the CRT. This results in a lower LCD 
duty cycle 

(

2/525 compared to the usual 1/241). This reduced duty cycle is not extreme 

and the contrast of the LCD image should not be greatly reduced.

10

Interlace

The odd and even fields of a 480-line image are interlaced on the LCD. This mode is used 
to display a 480-line image on the CRT and squash it onto a 240-line LCD. The full image 
is viewed on the LCD but the interlacing may create flicker. The LCD has a shortened 
aspect ratio.

It is necessary to suit the vertical retrace period to the CRT. This results in a lower LCD 
duty cycle (2/525 compared to the usual 1/241). This reduced duty cycle is not extreme 
and the contrast of the LCD image should not be greatly reduced.

11

Even Scan Only

Only the even field of a 480-line image is displayed on the LCD. This is an alternate 
method to display a 480-line image on the CRT and squash it onto a 240-line LCD. Only 
the even scans are viewed on the LCD. The LCD has a shortened aspect ratio.

It is necessary to suit the vertical retrace period to the CRT. This results in a lower LCD 
duty cycle 

(

2/525 compared to the usual 1/241). This reduced duty cycle is not extreme 

and the contrast of the LCD image should not be greatly reduced.

Summary of Contents for S1D13505

Page 1: ...ent but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson ...

Page 2: ...Page 2 Epson Research and Development Vancouver Design Center S1D13505 TECHNICAL MANUAL X23A Q 001 12 Issue Date 01 04 18 THIS PAGE LEFT BLANK ...

Page 3: ...To obtain these programs contact Application Engineering Support Application Engineering Support Engineering and Sales Support is provided by Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http www epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4...

Page 4: ...Page 4 Epson Research and Development Vancouver Design Center S1D13505 TECHNICAL MANUAL X23A Q 001 12 Issue Date 01 04 18 THIS PAGE LEFT BLANK ...

Page 5: ...fer Display Support 4 8 bit monochrome passive LCD interface 4 8 16 bit color passive LCD interface Single panel single drive displays Dual panel dual drive displays Direct support for 9 12 bit TFT D TFD 18 bit TFT D TFD is supported up to 64K color depth 16 bit data Embedded RAMDAC with direct analog CRT drive Simultaneous display of CRT and passive or TFT D TFD panels Maximum resolution of 800x6...

Page 6: ... laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft Windows and the Windows Embedded Partner Logo are registered trademarks of Mi crosoft Corporation All other trademarks are the property of their respective owners Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http www epson co j...

Page 7: ...ocument but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Ep...

Page 8: ...Page 2 Epson Research and Development Vancouver Design Center S1D13505 Hardware Functional Specification X23A A 001 14 Issue Date 01 02 02 THIS PAGE LEFT BLANK ...

Page 9: ...4 Internal Description 20 4 1 Block Diagram Showing Datapaths 20 4 2 Block Descriptions 20 4 2 1 Register 20 4 2 2 Host Interface 20 4 2 3 CPU R W 20 4 2 4 Memory Controller 21 4 2 5 Display FIFO 21 4 2 6 Cursor FIFO 21 4 2 7 Look Up Tables 21 4 2 8 CRTC 21 4 2 9 LCD Interface 21 4 2 10 DAC 21 4 2 11 Power Save 21 4 2 12 Clocks 21 5 Pins 22 5 1 Pinout Diagram 22 5 2 Pin Description 23 5 2 1 Host I...

Page 10: ... DRAM Read Write Read Write Timing 69 7 3 5 FPM DRAM CAS Before RAS Refresh Timing 72 7 3 6 FPM DRAM Self Refresh Timing 73 7 4 Power Sequencing 74 7 4 1 LCD Power Sequencing 74 7 4 2 Power Save Status 75 7 5 Display Interface 76 7 5 1 4 Bit Single Monochrome Passive LCD Panel Timing 76 7 5 2 8 Bit Single Monochrome Passive LCD Panel Timing 78 7 5 3 4 Bit Single Color Passive LCD Panel Timing 80 7...

Page 11: ...Configuration 124 10 1 Display Mode Data Format 124 10 2 Image Manipulation 126 11 Look Up Table Architecture 127 11 1 Monochrome Modes 127 11 2 Color Modes 129 12 Ink Cursor Architecture 133 12 1 Ink Cursor Buffers 133 12 2 Ink Cursor Data Format 133 12 3 Ink Cursor Image Manipulation 134 12 3 1 Ink Image 134 12 3 2 Cursor Image 134 13 SwivelView 135 13 1 Concept 135 13 2 Image Manipulation in Sw...

Page 12: ...Page 6 Epson Research and Development Vancouver Design Center S1D13505 Hardware Functional Specification X23A A 001 14 Issue Date 01 02 02 THIS PAGE LEFT BLANK ...

Page 13: ... PC Card Timing 51 Table 7 6 Generic Timing 53 Table 7 7 MIPS ISA Timing 55 Table 7 8 Philips Timing 57 Table 7 9 Clock Input Requirements for BUSCLK using Philips local bus 57 Table 7 10 Toshiba Timing 59 Table 7 11 Clock Input Requirements for BUSCLK using Toshiba local bus 59 Table 7 12 Power PC Timing 61 Table 7 13 Clock Input Requirements for CLKI divided down internally MCLK CLKI 2 62 Table ...

Page 14: ...Refresh Selection 111 Table 8 11 MA GPIO Pin Functionality 112 Table 8 12 Minimum Memory Timing Selection 114 Table 8 13 RAS to CAS Delay Timing Select 115 Table 8 14 RAS Precharge Timing Select 116 Table 8 15 Optimal NRC NRP and NRCD values at maximum MCLK frequency 116 Table 8 16 Minimum Memory Timing Selection 117 Table 8 17 Ink Cursor Selection 118 Table 8 18 Ink Cursor Start Address Encoding ...

Page 15: ... 7 MIPS ISA Timing 54 Figure 7 8 Philips Timing 56 Figure 7 9 Clock Input Requirement 57 Figure 7 10 Toshiba Timing 58 Figure 7 11 Clock Input Requirement 59 Figure 7 12 Power PC Timing 60 Figure 7 13 Clock Input Requirement 62 Figure 7 14 EDO DRAM Read Write Timing 63 Figure 7 15 EDO DRAM Read Write Timing 64 Figure 7 16 EDO DRAM CAS Before RAS Refresh Timing 66 Figure 7 17 EDO DRAM Self Refresh ...

Page 16: ...igure 7 41 16 Bit Dual Color Passive LCD Panel A C Timing 93 Figure 7 42 16 Bit TFT D TFD Panel Timing 94 Figure 7 43 TFT D TFD A C Timing 95 Figure 7 44 CRT Timing 97 Figure 7 45 CRT A C Timing 98 Figure 9 1 Display Buffer Addressing 122 Figure 10 1 1 2 4 8 Bit per pixel Format Memory Organization 124 Figure 10 2 15 16 Bit per pixel Format Memory Organization 125 Figure 10 3 Image Manipulation 12...

Page 17: ...ate your comments on our documentation Please contact us via email at documentation erd epson com 1 2 Overview Description The S1D13505 is a color monochrome LCD CRT graphics controller interfacing to a wide range of CPUs and display devices The S1D13505 architecture is designed to meet the low cost low power requirements of the embedded markets such as Mobile Communications Hand Held PCs and Offi...

Page 18: ...4 bus interface 8 16 bit SH 3 bus interface 8 16 bit interface to 8 16 32 bit MC68000 microprocessors microcontrollers 8 16 bit interface to 8 16 32 bit MC68030 microprocessors microcontrollers Philips PR31500 PR31700 MIPS Toshiba TX3912 MIPS 16 bit Power PC MPC821 microprocessor 16 bit Epson E0C33 microprocessor PC Card PCMCIA StrongARM PC Card NEC VR41xx MIPS ISA bus Supports the following inter...

Page 19: ...s into 4096 colors 15 16 bpp modes are mapped directly 2 5 Display Features SwivelView direct hardware 90 rotation of display image for portrait mode display Split Screen Display allows two different images to be simultaneously viewed on the same display Virtual Display Support displays images larger than the display size through the use of panning Double Buffering multi pages provides smooth anim...

Page 20: ...PIO 3 1 are available if the upper Memory Address pins are not required for asymmetric DRAM support Suspend power save mode can be initiated by either hardware or software The SUSPEND pin is used either as an input to initiate Suspend mode or as a General Purpose Output that can be used to control the LCD backlight Power on polarity is selected by an MD configuration pin Operating voltages from 2 ...

Page 21: ...0 RD WR AB 20 0 DB 15 0 WE1 BS RD M R CS BUSCLK WAIT RESET A 21 CSn WE1 LCDPWR LCAS UCAS MA 8 0 MD 15 0 WE RAS Power Management SUSPEND RED GREEN BLUE HRTC VRTC CRT Display IREF IREF WE A 8 0 D 15 0 RAS 256Kx16 LCAS UCAS FPM EDO DRAM S1D13505F00A FPFRAME FPSHIFT FPLINE DRDY FPDAT 15 8 FPDAT 7 0 CLKI Oscillator FPFRAME FPSHIFT FPLINE MOD UD 7 0 LD 7 0 4 8 16 bit LCD Display SH 3 BUS RESET WE0 D 15 ...

Page 22: ...S M R CS BUSCLK WAIT RESET A 23 21 FC0 FC1 Decoder Decoder UDS LCDPWR LCAS UCAS MA 8 0 MD 15 0 WE RAS Power Management SUSPEND RED GREEN BLUE HRTC VRTC CRT Display IREF IREF WE A 8 0 D 15 0 RAS 256Kx16 LCAS UCAS FPM EDO DRAM S1D13505F00A FPFRAME FPSHIFT FPLINE DRDY FPDAT 15 8 FPDAT 7 0 CLKI Oscillator FPFRAME FPSHIFT FPLINE MOD UD 7 0 LD 7 0 4 8 16 bit LCD Display MC68030 BUS RESET SIZ0 D 31 16 AS...

Page 23: ...M R CS BUSCLK WAIT RESET A 27 21 CSn WE1 LCDPWR WE A 11 0 D 15 0 RAS 1Mx16 LCAS UCAS MA 11 0 MD 15 0 WE RAS LCAS UCAS FPM EDO DRAM Decoder WE0 WE0 Power Management SUSPEND RED GREEN BLUE HRTC VRTC CRT Display IREF IREF S1D13505F00A FPFRAME FPSHIFT FPLINE DRDY FPDAT 15 8 FPDAT 7 0 CLKI Oscillator FPFRAME FPSHIFT FPLINE MOD UD 7 0 LD 7 0 4 8 16 bit LCD Display MIPS BUS RESET D 15 0 MEMR RDY A 20 0 B...

Page 24: ...play IREF IREF PR31500 BUS RESET WE D 31 16 CARDxCSL RD CARDxWAIT A 12 0 DCLKOUT WE0 RD WR AB 12 0 DB 15 0 WE1 BS RD M R CS BUSCLK WAIT RESET CARDxCSH AB 16 13 ALE CARDREG CARDIORD AB20 AB19 AB18 AB17 CARDIOWR PR31700 Philips S1D13505F00A FPFRAME FPSHIFT FPLINE DRDY FPDAT 15 8 FPDAT 7 0 CLKI Oscillator FPFRAME FPSHIFT FPLINE MOD UD 7 0 LD 7 0 4 8 16 bit LCD Display LCDPWR WE A 11 0 D 15 0 RAS 1Mx1...

Page 25: ...15 0 WE1 BS RD M R CS BUSCLK WAIT RESET A 0 10 Decoder Decoder BI LCDPWR WE A 8 0 D 15 0 RAS 256Kx16 LCAS UCAS MA 8 0 MD 15 0 WE RAS LCAS UCAS FPM EDO DRAM Power Management SUSPEND RED GREEN BLUE HRTC VRTC CRT Display IREF IREF S1D13505F00A FPFRAME FPSHIFT FPLINE DRDY FPDAT 15 8 FPDAT 7 0 CLKI Oscillator FPFRAME FPSHIFT FPLINE MOD UD 7 0 LD 7 0 4 8 16 bit LCD Display PC Card BUS RESET D 15 0 OE WA...

Page 26: ...s 4 2 2 Host Interface The Host Interface I F block provides the means for the CPU MPU to communicate with the display buffer and internal registers via one of the supported bus interfaces 4 2 3 CPU R W The CPU R W block synchronizes the CPU requests for display buffer access If SwivelView is enabled the data is rotated in this block Clocks LCD Memory Controller 16 bit FPM EDO DRAM LCD Power Save ...

Page 27: ...Up Tables The Look Up Tables block contains three 256x4 Look Up Tables LUT one for each primary color In monochrome mode only the green LUT is selected and used This block contains anti sparkle circuitry The cursor ink and display data are merged in this block 4 2 8 CRTC The CRTC generates the sync timing for the LCD and CRT defining the vertical and horizontal display periods 4 2 9 LCD Interface ...

Page 28: ...4 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 58 59 60 61 62 63 51 52 53 54 55 56 57 64 S1D13505 RD WR WAIT VDD VSS DB15 DB14 DB12 DB8 DB5 DB3 DB2 DB1 DB0 DB13 DB4 AB2 RESET VDD MA6 MA8 DB7 FPDAT3 MA3 MA4 MA2 MA5 MD6 MA11 MA0 MA7 MA10 MA9 VDD BLUE VSS DACVDD GREEN FPDAT13 FPDAT10 RAS WE UCAS VSS MD7 MD8 MD5 MD10 MD4 MD11 MD3 MD12 MD2 MD13 MD1 AB3 BS WE1 WE0 RD M R CS AB0 AB1 AB11 AB12 AB15 AB1...

Page 29: ...t Interface Pin Descriptions Pin Name Type Pin Cell RESET State Description AB0 I 3 CS Hi Z For SH 3 SH 4 Bus this pin inputs system address bit 0 A0 For MC68K Bus 1 this pin inputs the lower data strobe LDS For MC68K Bus 2 this pin inputs system address bit 0 A0 For Generic Bus this pin inputs system address bit 0 A0 For MIPS ISA Bus this pin inputs system address bit 0 SA0 For Philips PR31500 31...

Page 30: ...CARDIORD For PowerPC Bus this pin inputs the system address bit 13 A13 For all other busses this pin inputs the system address bit 18 A18 See Host Bus Interface Pin Mapping for summary See the respective AC Timing diagram for detailed functionality AB19 I 112 C Hi Z For Philips PR31500 31700 Bus this pin inputs the card control register access CARDREG For Toshiba TX3912 Bus this pin inputs the car...

Page 31: ...is pin inputs the data strobe DS For Generic Bus this pin inputs the write enable signal for the upper data byte WE1 For MIPS ISA Bus this pin inputs the system byte high enable signal SBHE For Philips PR31500 31700 Bus this pin inputs the odd byte access enable signal CARDxCSH For Toshiba TX3912 Bus this pin inputs the odd byte access enable signal CARDxCSH For PowerPC Bus this pin outputs the bu...

Page 32: ...d to VDD For MIPS ISA Bus this pin is connected to VDD For Philips PR31500 31700 Bus this pin is connected to VDD For Toshiba TX3912 Bus this pin is connected to VDD For PowerPC Bus this pin inputs the Transfer Start signal TS For PC Card PCMCIA Bus this pin is connected to VDD See Host Bus Interface Pin Mapping for summary See the respective AC Timing diagram for detailed functionality RD WR I 10...

Page 33: ...Interface Pin Mapping for summary See the respective AC Timing diagram for detailed functionality WE0 I 8 CS Hi Z This is a multi purpose pin For SH 3 SH 4 Bus this pin inputs the write enable signal for the lower data byte WE0 For MC68K Bus 1 this pin must be connected to VDD For MC68K Bus 2 this pin inputs the bus size bit 0 SIZ0 For Generic Bus this pin inputs the write enable signal for the lo...

Page 34: ...ow during reset by the internal pull down resistor For MIPS ISA Bus this pin outputs the IO channel ready signal IOCHRDY MD5 must be pulled low during reset by the internal pull down resistor For Philips PR31500 31700 Bus this pin outputs the wait state signal CARDxWAIT MD5 must be pulled low during reset by the internal pull down resistor For Toshiba TX3912 Bus this pin outputs the wait state sig...

Page 35: ...ory Interface Pin Mapping for summary See Memory Interface Timing for detailed functionality WE O 53 CO1 1 For dual CAS DRAM this is the write enable signal WE For single CAS DRAM this is the write enable signal for the lower byte LWE See Memory Interface Pin Mapping for summary See Memory Interface Timing for detailed functionality RAS O 54 CO1 1 Row address strobe see Memory Interface Timing for...

Page 36: ...t This is a multi purpose pin For asymmetrical 2M byte DRAM this is memory address bit 10 MA10 For symmetrical 2M byte DRAM and all 512K byte DRAM this pin can be used as general purpose IO pin 1 GPIO1 Note that unless configured otherwise this pin defaults to an input and must be driven to a valid logic level See Memory Interface Pin Mapping for summary See Memory Interface Timing for detailed fu...

Page 37: ... RESET see Summary of Configuration Options This output is controlled by the power save mode circuitry see Power Save Modes for details DRDY O 76 CN3 0utput This is a multi purpose pin For TFT D TFD panels this is the display enable output DRDY For passive LCD with Format 1 interface this is the 2nd Shift Clock FPSHIFT2 For all other LCD panels this is the LCD backplane bias signal MOD See LCD Int...

Page 38: ...t used to put the S1D13505 into Hardware Suspend mode see Section 15 Power Save Modes for details When MD 10 9 01 at rising edge of RESET this pin is an output GPO with a reset state of 1 The state of GPO is controlled by REG 21h bit 7 When MD 10 9 11 at rising edge of RESET this pin is an output GPO with a reset state of 0 The state of GPO is controlled by REG 21h bit 7 CLKI I 69 C Input clock fo...

Page 39: ...us MD4 Little Endian Big Endian MD5 WAIT is active high 1 insert wait state WAIT is active low 0 insert wait state MD 7 6 Memory Address GPIO configuration 00 symmetrical 256K 16 DRAM MA 8 0 DRAM address MA 11 9 GPIO2 1 3 pins 01 symmetrical 1M 16 DRAM MA 9 0 DRAM address MA 10 11 GPIO2 1 pins 10 asymmetrical 256K 16 DRAM MA 9 0 DRAM address MA 10 11 GPIO2 1 pins 11 asymmetrical 1M 16 DRAM MA 11 0...

Page 40: ...A 16 13 A 16 13 SA 16 13 VDD VDD A 15 18 A 16 13 AB 12 1 A 12 1 A 12 1 A 12 1 A 12 1 A 12 1 SA 12 1 A 12 1 A 12 1 A 19 30 A 12 1 AB0 A01 A0 LDS A0 A01 SA0 A01 A01 A31 A01 DB 15 8 D 15 8 D 15 8 D 15 8 D 31 24 D 15 8 SD 15 8 D 31 24 D 31 24 D 0 7 D 15 8 DB 7 0 D 7 0 D 7 0 D 7 0 D 23 16 D 7 0 SD 7 0 D 23 16 D 23 16 D 8 15 D 7 0 WE1 WE1 WE1 UDS DS WE1 SBHE CARDxCSH CARDxCSH BI CE2 M R External Decode ...

Page 41: ...ise should be connected to either VSS or IO VDD if not used Table 5 7 Memory Interface Pin Mapping S1D13505 Pin Names FPM EDO DRAM Sym 256Kx16 Asym 256Kx16 Sym 1Mx16 Asym 1Mx16 2 CAS 2 WE 2 CAS 2 WE 2 CAS 2 WE 2 CAS 2 WE MD 15 0 D 15 0 MA 8 0 A 8 0 MA9 GPIO3 A9 A9 MA10 GPIO1 A10 MA11 GPIO2 A11 UCAS UCAS UWE UCAS UWE UCAS UWE UCAS UWE LCAS LCAS CAS LCAS CAS LCAS CAS LCAS CAS WE WE LWE WE LWE WE LWE...

Page 42: ...D4 D4 D4 UD0 UD0 G1 G2 G4 FPDAT5 D1 D5 UD1 D1 D5 D5 D5 UD1 UD1 G0 G1 G3 FPDAT6 D2 D6 UD2 D2 D6 D6 D6 UD2 UD2 B2 B3 B5 FPDAT7 D3 D7 UD3 D3 D7 D7 D7 UD3 UD3 B1 B2 B4 FPDAT8 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 D8 driven 0 LD4 B0 B1 B3 FPDAT9 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 D9 driven 0 LD5 driven 0 R0 R2 FPDAT10 driven 0 driven 0 driven 0 driven 0 driven 0 drive...

Page 43: ...T Interface The following figure shows the external circuitry for the CRT interface Figure 5 3 External Circuitry for CRT Interface 2N2222 4 6 mA 4 6 mA 140Ω 1 1kΩ 1 1 5kΩ 1 DAC VSS DAC VSS V R V DAC VSS DAC VSS DAC VDD 2 7V to 5 5V DAC VDD 3 3V LM334 290Ω 1 29Ω 1 1N457 1µF 150Ω 1 150Ω 1 150Ω 1 DAC VSS DAC VSS DAC VSS 4 6 mA OR IREF R G B To CRT ...

Page 44: ...oltage VSS 0 3 to 6 0 V DAC VDD Supply Voltage VSS 0 3 to 6 0 V VIN Input Voltage VSS 0 3 to VDD 0 5 V VOUT Output Voltage VSS 0 3 to VDD 0 5 V TSTG Storage Temperature 65 to 150 C TSOL Solder Temperature Time 260 for 10 sec max at lead C Table 6 2 Recommended Operating Conditions Symbol Parameter Condition Min Typ Max Units VDD Supply Voltage VSS 0 V 2 7 3 0 3 3 5 0 5 5 V VIN Input Voltage VSS VD...

Page 45: ... Level Output Voltage VDD min IOL 4mA Type1 8mA Type2 12mA Type3 VDD 0 4 V VOL Low Level Output Voltage VDD min IOL 4mA Type1 8mA Type2 12mA Type3 0 4 V VIH High Level Input Voltage CMOS level VDD max 3 5 V VIL Low Level Input Voltage CMOS level VDD min 1 0 V VT High Level Input Voltage CMOS Schmitt VDD 5 0V 4 0 V VT Low Level Input Voltage CMOS Schmitt VDD 5 0V 0 8 V VH1 Hysteresis Voltage CMOS S...

Page 46: ...h Level Output Voltage VDD min IOL 2mA Type1 4mA Type2 6mA Type3 VDD 0 3 V VOL Low Level Output Voltage VDD min IOL 2mA Type1 4mA Type2 6mA Type3 0 3 V VIH High Level Input Voltage CMOS level VDD max 2 2 V VIL Low Level Input Voltage CMOS level VDD min 0 8 V VT High Level Input Voltage CMOS Schmitt VDD 3 3V 2 4 V VT Low Level Input Voltage CMOS Schmitt VDD 3 3V 0 6 V VH1 Hysteresis Voltage CMOS Sc...

Page 47: ...el Output Voltage VDD min IOL 1 8mA Type1 3 5mA Type2 5mA Type3 VDD 0 3 V VOL Low Level Output Voltage VDD min IOL 1 8mA Type1 3 5mA Type2 5mA Type3 0 3 V VIH High Level Input Voltage CMOS level VDD max 2 0 V VIL Low Level Input Voltage CMOS level VDD min 0 8 V VT High Level Input Voltage CMOS Schmitt VDD 3 0V 2 3 V VT Low Level Input Voltage CMOS Schmitt VDD 3 0V 0 5 V VH1 Hysteresis Voltage CMOS...

Page 48: ... must be 5 nsec 10 90 CL 50pF CPU Interface unless noted CL 100pF LCD Panel Interface CL 10pF Display Buffer Interface CL 10pF CRT Interface 7 1 CPU Interface Timing 7 1 1 SH 4 Interface Timing Figure 7 1 SH 4 Timing Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected t1 t2 t3 t4 t10 t11 t15 t5 t6 t7 t8 t9 t12 t16 t13 t14 CKIO A 20 0 M R CSn ...

Page 49: ...f RD or the first positive edge of CKIO after A 20 0 M R becomes valid whichever one is later Table 7 1 SH 4 Timing 3 0Va a Two Software WAIT States Required 5 0Vb b One Software WAIT State Required Symbol Parameter Min Max Min Max Units t1 Clock period 15 15 ns t2 Clock pulse width high 6 6 ns t3 Clock pulse width low 6 6 ns t4 A 20 0 M R RD WR setup to CKIO 3 3 ns t5 A 20 0 M R RD WR hold from C...

Page 50: ...igure 7 2 SH 3 Timing Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected Note The SH 3 Wait State Control Register for the area in which the S1D13505 resides must be set to a non zero value t1 t2 t3 t4 t10 t11 t15 t5 t6 t7 t8 t9 t12 t16 t13 t14 CKIO A 20 0 M R CSn RD WR RD D 15 0 read BS WAIT WEn D 15 0 write t12 ...

Page 51: ...Timing 3 0Va a Two Software WAIT States Required 5 0Vb b One Software WAIT State Required Symbol Parameter Min Max Min Max Units t1 Clock period 15 1 15 1 ns t2 Clock pulse width high 6 6 ns t3 Clock pulse width low 6 6 ns t4 A 20 0 M R RD WR setup to CKIO 3 3 ns t5 A 20 0 M R RD WR hold from CS 0 0 ns t6 BS setup 4 4 ns t7 BS hold 1 1 ns t8 CSn setup 4 4 ns t92 Falling edge RD to D 15 0 driven 0 ...

Page 52: ...ssue Date 01 02 02 7 1 3 MC68K Bus 1 Interface Timing e g MC68000 Figure 7 3 MC68000 Timing Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected A 20 1 AS UDS D 15 0 write M R R W DTACK CLK t1 t2 t3 t4 t10 t7 CS t6 t9 t5 t11 LDS t12 t13 D 15 0 read t14 t15 t16 t8 t17 ...

Page 53: ...d 20 20 ns t2 Clock pulse width high 6 6 ns t3 Clock pulse width low 6 6 ns t4 A 20 1 M R setup to first CLK where CS 0 AS 0 and either UDS 0 or LDS 0 10 10 ns t5 A 20 1 M R hold from AS 0 0 ns t6 CS hold from AS 0 0 ns t7 R W setup to before to either UDS 0 or LDS 0 10 10 ns t8 R W hold from AS 0 0 ns t91 AS 0 and CS 0 to DTACK driven high 0 0 ns t10 AS high to DTACK high 3 18 3 12 ns t11 First B...

Page 54: ...e Date 01 02 02 7 1 4 MC68K Bus 2 Interface Timing e g MC68030 Figure 7 4 MC68030 Timing Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected A 20 0 AS DS D 31 16 write SIZ 1 0 M R R W DSACK1 CLK t1 t2 t3 t4 t10 t7 CS t6 t8 t5 D 31 16 read t11 t12 t13 t9 t14 t15 t16 t17 ...

Page 55: ... 20 20 ns t2 Clock pulse width high 6 6 ns t3 Clock pulse width low 6 6 ns t4 A 20 0 SIZ 1 0 M R setup to first CLK where CS 0 AS 0 and either UDS 0 or LDS 0 10 10 ns t5 A 20 0 SIZ 1 0 M R hold from AS 0 0 ns t6 CS hold from AS 0 0 ns t7 R W setup to DS 10 10 ns t8 R W hold from AS 0 0 ns t91 AS 0 and CS 0 to DSACK1 driven high 0 0 ns t10 AS high to DSACK1 high 3 18 3 12 ns t11 First BCLK where AS...

Page 56: ...on X23A A 001 14 Issue Date 01 02 02 7 1 5 PC Card Interface Timing Figure 7 5 PC Card Timing Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected A 20 0 OE D 15 0 write M R WAIT CLK t1 t2 t3 t4 t9 CE 1 0 t7 t8 WE t11 D 15 0 read t5 t6 t10 t12 t13 CS ...

Page 57: ... Card Timing 3 0V 5 0V Symbol Parameter Min Max Min Max Units t1 Clock period 20 20 ns t2 Clock pulse width high 6 6 ns t3 Clock pulse width low 6 6 ns t4 A 20 0 M R setup to first CLK where CS 0 and either OE 0 or WE 0 10 10 ns t5 A 20 0 M R hold from rising edge of either OE or WE 0 0 ns t6 CS hold from rising edge of either OE or WE 0 0 ns t71 Falling edge of either OE or WE to WAIT driven low ...

Page 58: ... X23A A 001 14 Issue Date 01 02 02 7 1 6 Generic Interface Timing Figure 7 6 Generic Timing Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected A 20 0 RD0 RD1 D 15 0 write M R WAIT CLK t1 t2 t3 t4 t9 t7 t8 WE0 WE1 t11 D 15 0 read t5 t6 t10 t12 t13 CS ...

Page 59: ...ol Parameter Min Max Min Max Units t1 Clock period 20 20 ns t2 Clock pulse width high 6 6 ns t3 Clock pulse width low 6 6 ns t4 A 20 0 M R setup to first CLK where CS 0 and either RD0 RD1 WE0 or WE1 0 10 10 ns t5 A 20 0 M R hold from rising edge of either RD0 RD1 WE0 or WE1 0 0 0 ns t6 CS hold from rising edge of either RD0 RD1 WE0 or WE1 0 0 0 ns t71 Falling edge of either RD0 RD1 WE0 or WE1 to W...

Page 60: ...01 14 Issue Date 01 02 02 7 1 7 MIPS ISA Interface Timing Figure 7 7 MIPS ISA Timing Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected LatchA20 MEMR SD 15 0 write M R SBHE IOCHRDY BUSCLK t1 t2 t3 t4 t9 CS t7 t8 MEMW t11 SD 15 0 read t5 t6 t10 t12 t13 SA 19 0 ...

Page 61: ...0V 5 0V Symbol Parameter Min Max Min Max Units t1 Clock period 20 20 ns t2 Clock pulse width high 6 6 ns t3 Clock pulse width low 6 6 ns t4 LatchA20 SA 19 0 M R SBHE setup to first BUSCLK where CS 0 and either MEMR 0 or MEMW 0 10 10 ns t5 LatchA20 SA 19 0 M R SBHE hold from rising edge of either MEMR or MEMW 0 0 ns t6 CS hold from rising edge of either MEMR or MEMW 0 0 ns t71 Falling edge of eithe...

Page 62: ...onal Specification X23A A 001 14 Issue Date 01 02 02 7 1 8 Philips Interface Timing e g PR31500 PR31700 Figure 7 8 Philips Timing ADDR 12 0 WE RD D 31 16 write CARDREG CARDxWAIT DCLKOUT t1 t2 t3 t4 t7 CARDxCSH t6 t8 ALE CARDxCSL CARDIORD CARDIOWR t5 t9 t10 t11 t12 D 31 16 read t13 t14 t15 ...

Page 63: ... 6 6 ns t3 Clock pulse width high 6 6 ns t4 ADDR 12 0 setup to first CLK of cycle 10 10 ns t5 ADDR 12 0 hold from command invalid 0 0 ns t6 ADDR 12 0 setup to falling edge ALE 10 10 ns t7 ADDR 12 0 hold from falling edge ALE 5 5 ns t8 CARDREG hold from command invalid 0 0 ns t91 Falling edge of chip select to CARDxWAIT driven 0 15 0 9 ns t10 Command invalid to CARDxWAIT tri state 5 25 2 5 10 ns t1...

Page 64: ...nctional Specification X23A A 001 14 Issue Date 01 02 02 7 1 9 Toshiba Interface Timing e g TX3912 Figure 7 10 Toshiba Timing ADDR 12 0 WE RD D 31 16 write CARDREG CARDxWAIT DCLKOUT t1 t2 t3 t4 t7 CARDxCSH t6 t8 ALE CARDxCSL CARDIORD CARDIOWR t5 t9 t10 t11 t12 D 31 16 read t13 t14 t15 ...

Page 65: ... 4 ns t3 Clock pulse width high 5 4 5 4 ns t4 ADDR 12 0 setup to first CLK of cycle 10 10 ns t5 ADDR 12 0 hold from command invalid 0 0 ns t6 ADDR 12 0 setup to falling edge ALE 10 10 ns t7 ADDR 12 0 hold from falling edge ALE 5 5 ns t8 CARDREG hold from command invalid 0 0 ns t91 Falling edge of chip select to CARDxWAIT driven 0 15 0 9 ns t10 Command invalid to CARDxWAIT tri state 5 25 2 5 10 ns ...

Page 66: ...7 1 10 Power PC Interface Timing e g MPC8xx MC68040 Coldfire Figure 7 12 Power PC Timing Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected A 11 31 RD WR TS D 0 15 write TSIZ 0 1 M R TA CLKOUT t1 t2 t3 t4 t10 D 0 15 read t11 t20 CS t5 t6 t7 t8 t9 t12 t21 t17 t18 BI t13 t14 t15 t16 t19 ...

Page 67: ...p 10 10 ns t7 CS hold 0 0 ns t8 TS setup 7 10 ns t9 TS hold 5 0 ns t10 CLKOUT to TA driven 0 0 ns t11 CLKOUT to TA low 3 19 3 12 ns t12 CLKOUT to TA high 3 19 7 3 13 ns t13 negative edge CLKOUT to TA tri state 5 25 2 5 10 ns t14 CLKOUT to BI driven 0 18 0 11 ns t15 CLKOUT to BI high 3 16 3 10 ns t16 negative edge CLKOUT to BI tri state 5 25 2 5 10 ns t17 D 0 15 setup to 2nd CLKOUT after TS 0 write...

Page 68: ... internally MCLK CLKI 2 Symbol Parameter Min Max Units TOSC Input Clock Period 12 5 ns tPWH Input Clock Pulse Width High 5 6 ns tPWL Input Clock Pulse Width Low 5 6 ns tf Input Clock Fall Time 10 90 5 ns tr Input Clock Rise Time 10 90 5 ns Table 7 14 Clock Input Requirements for CLKI Symbol Parameter Min Max Units TOSC Input Clock Period 25 ns tPWH Input Clock Pulse Width High 11 3 ns tPWL Input C...

Page 69: ...ate 01 02 02 X23A A 001 14 7 3 Memory Interface Timing 7 3 1 EDO DRAM Read Write Read Write Timing Figure 7 14 EDO DRAM Read Write Timing RAS CAS MA MD read R C1 t2 Memory Clock d1 C2 C3 d2 d3 t3 t4 t5 t6 t1 t7 t8 t9 t10 t11 t10 t11 t14 t15 t16 t17 WE read t12 t13 t1 WE write t18 t19 MD write t20 t21 d1 d2 d3 t22 ...

Page 70: ...delay time REG 22h bit 4 0 and bits 3 2 00 or 10 2t1 3 ns RAS to CAS delay time REG 22h bit 4 1 and bits 3 2 00 or 10 1t1 3 ns RAS to CAS delay time REG 22h bits 3 2 01 1 45 t1 3 ns t5 CAS precharge time 0 45 t1 3 ns t6 CAS pulse width 0 45 t1 3 ns t7 RAS hold time 1 t1 3 ns t8 Row address setup time REG 22h bits 3 2 00 2 45 t1 ns Row address setup time REG 22h bits 3 2 01 2 t1 ns Row address setu...

Page 71: ...bits 3 2 00 2 45 t1 3 ns Read Command Hold REG 22h bit 4 1 and bits 3 2 10 1 45 t1 3 ns Read Command Hold REG 22h bits 3 2 01 2 45 t1 3 ns t14 Read Data Setup referenced from CAS 5 ns t15 Read Data Hold referenced from CAS 3 ns t16 Last Read Data Setup referenced from RAS 5 ns t17 Bus Turn Off from RAS 3 t1 5 ns t18 Write Command Setup 0 45 t1 3 ns t19 Write Command Hold 0 45 t1 3 ns t20 Write Dat...

Page 72: ...se width REG 22h bit 6 5 00 and bits 3 2 00 3 t1 3 ns RAS pulse width REG 22h bit 6 5 00 and bits 3 2 01 3 45 t1 3 ns RAS pulse width REG 22h bit 6 5 00 and bits 3 2 10 4 t1 3 ns RAS pulse width REG 22h bit 6 5 01 and bits 3 2 00 2 t1 3 ns RAS pulse width REG 22h bit 6 5 01 and bits 3 2 01 2 45 t1 3 ns RAS pulse width REG 22h bit 6 5 01 and bits 3 2 10 3 t1 3 ns RAS pulse width REG 22h bit 6 5 10 ...

Page 73: ...t 6 5 00 and bits 3 2 10 3 45 t1 3 ns CAS Hold to RAS REG 22h bit 6 5 01 and bits 3 2 00 1 45 t1 3 ns CAS Hold to RAS REG 22h bit 6 5 01 and bits 3 2 01 2 t1 3 ns CAS Hold to RAS REG 22h bit 6 5 01 and bits 3 2 10 2 45 t1 3 ns CAS Hold to RAS REG 22h bit 6 5 10 and bits 3 2 00 0 45 t1 3 ns CAS Hold to RAS REG 22h bit 6 5 10 and bits 3 2 01 1 t1 3 ns CAS Hold to RAS REG 22h bit 6 5 10 and bits 3 2 ...

Page 74: ...REG 22h bits 3 2 00 2 t1 3 ns RAS precharge time REG 22h bits 3 2 01 1 45t1 3 ns RAS precharge time REG 22h bits 3 2 10 1 t1 3 ns t3 RAS to CAS precharge time REG 22h bits 3 2 00 1 45t1 3 ns RAS to CAS precharge time REG 22h bits 3 2 01 or 10 0 45t1 3 ns t4 CAS setup time REG 22h bits 3 2 00 or 10 0 45t1 3 ns CAS setup time REG 22h bits 3 2 01 1 t1 3 ns t5 CAS precharge time REG 22h bits 3 2 00 2 ...

Page 75: ...n S1D13505 Issue Date 01 02 02 X23A A 001 14 7 3 4 FPM DRAM Read Write Read Write Timing Figure 7 18 FPM DRAM Read Write Timing RAS CAS MA MD read R C1 t2 Memory Clock d1 C2 C3 d2 d3 t3 t4 t5 t6 t1 t7 t8 t9 t10 t11 t10 t11 t14 t15 WE read t12 t13 t1 WE write t16 t17 MD write t18 t19 d1 d2 d3 t20 ...

Page 76: ...RAS precharge time REG 22h bits 3 2 10 1 t1 3 ns t4 RAS to CAS delay time REG 22h bit 4 1 and bits 3 2 00 or 10 1 45 t1 3 ns RAS to CAS delay time REG 22h bit 4 0 and bits 3 2 00 or 10 2 45 t1 3 ns RAS to CAS delay time REG 22h bit 4 1 and bits 3 2 01 1t1 3 ns RAS to CAS delay time REG 22h bit 4 0 and bits 3 2 01 2t1 3 ns t5 CAS precharge time 0 45 t1 3 ns t6 CAS pulse width 0 45 t1 3 ns t7 RAS ho...

Page 77: ...0 3 45 t1 3 ns Read Command Setup REG 22h bit 4 1 and bits 3 2 01 or 10 2 45 t1 3 ns t13 Read Command Hold REG 22h bit 4 0 and bits 3 2 00 4 t1 3 ns Read Command Hold REG 22h bit 4 0 and bits 3 2 01 or 10 3 t1 3 ns Read Command Hold REG 22h bit 4 1 and bits 3 2 00 3 t1 3 ns Read Command Hold REG 22h bit 4 1 and bits 3 2 01 or 10 2 t1 3 ns t14 Read Data Setup referenced from CAS 5 ns t15 Bus Tri St...

Page 78: ...h bits 6 5 01 and bits 3 2 00 1 45 t1 3 ns RAS pulse width REG 22h bits 6 5 01 and bits 3 2 01 or 10 2 45 t1 3 ns RAS pulse width REG 22h bits 6 5 10 and bits 3 2 00 0 45 t1 3 ns RAS pulse width REG 22h bits 6 5 10 and bits 3 2 01 or 10 1 45 t1 3 ns t4 CAS pulse width REG 22h bits 3 2 00 2 t1 3 ns CAS pulse width REG 22h bits 3 2 01 or 10 1 t1 3 t5 CAS Setup to RAS 0 45 t1 3 ns t6 CAS Hold to RAS ...

Page 79: ... Refresh Timing Symbol Parameter Min Max Units t1 Internal memory clock 40 ns t2 RAS precharge time REG 22h bits 3 2 00 2 45 t1 1 ns RAS precharge time REG 22h bits 3 2 01 or 10 1 45 t1 1 ns t3 RAS to CAS precharge time REG 22h bits 3 2 00 2 t1 ns RAS to CAS precharge time REG 22h bits 3 2 01 or 10 1 t1 ns t4 CAS setup time CAS before RAS refresh 0 45 t1 2 ns RAS CAS t3 t4 t2 Memory Clock Stopped ...

Page 80: ... of the pixel clock Symbol Parameter Min Max Units t1 SUSPEND or LCD ENABLE BIT low to LCDPWR off 2TFPFRAME 8TPCLK ns t2 SUSPEND or LCD ENABLE BIT low to FPFRAME inactive 1 Frames t3 FPFRAME inactive to FPLINE FPSHIFT FPDATA DRDY inactive 128 Frames t4 SUSPEND to CLKI inactive 130 Frames t5 SUSPEND or LCD ENABLE BIT high to FPLINE FPSHIFT FPDATA DRDY active TFPFRAME 8TPCLK ns t6 FPLINE FPSHIFT FPD...

Page 81: ...cess not be performed after a Power Save Mode has been initiated Table 7 22 Power Save Status and Local Bus Memory Access Relative to Power Save Mode Symbol Parameter Min Max Units t1 Power Save initiated to rising edge of Power Save Status and the last time memory access by the local bus may be performed 129 130 Frames t2 Power Save deactivated to falling edge of Power Save Status 12 MCLK t3 Fall...

Page 82: ...cal Display Period REG 09h bits 1 0 REG 08h bits 7 0 1 VNDP Vertical Non Display Period REG 0Ah bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period REG 05h bits 4 0 1 8Ts FPLINE FPSHIFT FPFRAME FPLINE MOD MOD Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel UD 3 0 UD2 UD1 UD0 UD3 VDP LINE1 LINE2 LINE3 LINE4 LINE239 ...

Page 83: ...r Min Typ Max Units t1 FPFRAME setup to FPLINE pulse trailing edge note 2 t2 FPFRAME hold from FPLINE pulse trailing edge 14 Ts note 1 t3 FPLINE pulse width 9 Ts t4 FPLINE period note 3 t5 MOD transition to FPLINE pulse trailing edge 1 note 4 Ts t6 FPSHIFT falling edge to FPLINE pulse leading edge note 5 t7 FPLINE pulse trailing edge to FPSHIFT falling edge t10 t11 Ts t8 FPSHIFT period 4 Ts t9 FPS...

Page 84: ... VNDP Vertical Non Display Period REG 0Ah bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period REG 05h bits 4 0 1 8Ts FPLINE FPSHIFT FPFRAME FPLINE MOD MOD Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel UD 3 0 LD 3 0 UD2 UD1 UD0 UD3 LD2 LD1 LD0 LD3 HNDP VDP LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 1 2 1 ...

Page 85: ...Max Units t1 FPFRAME setup to FPLINE pulse trailing edge note 2 t2 FPFRAME hold from FPLINE pulse trailing edge 14 Ts note 1 t3 FPLINE pulse width 9 Ts t4 FPLINE period note 3 t5 MOD transition to FPLINE pulse trailing edge 1 note 4 Ts t6 FPSHIFT falling edge to FPLINE pulse leading edge note 5 t7 FPLINE pulse trailing edge to FPSHIFT falling edge t10 t11 Ts t8 FPSHIFT period 8 Ts t9 FPSHIFT falli...

Page 86: ...1 0 REG 08h bits 7 0 1 VNDP Vertical Non Display Period REG 0Ah bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period REG 05h bits 4 0 1 8Ts FPLINE UD 3 0 FPFRAME FPLINE MOD UD2 UD1 UD0 UD3 MOD Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel FPSHIFT VDP LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 VNDP 1 R1 1 ...

Page 87: ...x Units t1 FPFRAME setup to FPLINE pulse trailing edge note 2 t2 FPFRAME hold from FPLINE pulse trailing edge 14 Ts note 1 t3 FPLINE pulse width 9 Ts t4 FPLINE period note 3 t5 MOD transition to FPLINE pulse trailing edge 1 note 4 Ts t6 FPSHIFT falling edge to FPLINE pulse leading edge note 5 t7 FPLINE pulse trailing edge to FPSHIFT falling edge t10 t11 Ts t8 FPSHIFT period 1 Ts t9 FPSHIFT falling...

Page 88: ...6 0 1 8Ts HNDP Horizontal Non Display Period REG 05h bits 4 0 1 8Ts FPLINE FPSHIFT2 FPFRAME FPLINE UD2 UD1 UD0 LD3 LD2 LD1 LD0 UD3 FPSHIFT Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel UD 3 0 LD 3 0 VDP LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 HDP VNDP 1 R1 1 B1 1 G2 1 R3 1 B3 1 G4 1 R5 1 B5 1 G1 1 R2 1 B2 1 G3 1 R4 1 B4 1 G5 1 R6 1 G6 1 R7 1 B7 1 ...

Page 89: ...FPFRAME hold from FPLINE pulse trailing edge 14 Ts note 1 t3 FPLINE pulse width 9 Ts t4 FPLINE period note 3 t5a FPSHIFT2 falling edge to FPLINE pulse leading edge note 4 t5b FPSHIFT falling edge to FPLINE pulse leading edge note 5 t6 FPLINE pulse trailing edge to FPSHIFT2 rising FPSHIFT falling edge t9 t10 Ts t7 FPSHIFT2 FPSHIFT period 4 Ts t8a FPSHIFT falling edge to FPLINE pulse trailing edge n...

Page 90: ...y Period REG 0Ah bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period REG 05h bits 4 0 1 8Ts FPLINE UD 3 0 LD 3 0 FPFRAME FPLINE MOD UD2 UD1 UD0 LD3 LD2 LD1 LD0 UD3 MOD Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel FPSHIFT VDP LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 VNDP 1 R1 1 G1 1 B1 1 R2 1 G2 1 B2 1...

Page 91: ...n Typ Max Units t1 FPFRAME setup to FPLINE pulse trailing edge note 2 t2 FPFRAME hold from FPLINE pulse trailing edge 14 Ts note 1 t3 FPLINE period note 3 t4 FPLINE pulse width 9 Ts t5 MOD transition to FPLINE pulse trailing edge 1 note 4 Ts t6 FPSHIFT falling edge to FPLINE pulse leading edge note 5 t7 FPSHIFT falling edge to FPLINE pulse trailing edge note 6 t8 FPLINE pulse trailing edge to FPSH...

Page 92: ...h bits 4 0 1 8Ts VDP FPLINE FPSHIFT UD 7 0 LD 7 0 LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 FPFRAME LINE1 LINE2 FPLINE MOD UD6 UD5 UD4 UD3 UD2 UD1 UD0 UD7 MOD VNDP HDP 1 R1 1 G6 1 G635 1 B1 1 R7 1 G636 1 G2 1 B7 1 R637 1 R3 1 G8 1 B637 1 B3 1 R9 1 G638 1 G4 1 B9 1 R639 1 R5 1 G10 1 B639 1 G1 1 B6 1 R636 1 R2 1 G7 1 B636 1 B2 1 R8 1 G637 1 G3 1 B8 1 R638 1 R4 1 G9 1 B638 1 B4 1 R10 1 G639 1 G5 1 B10 ...

Page 93: ... Units t1 FPFRAME setup to FPLINE pulse trailing edge note 2 t2 FPFRAME hold from FPLINE pulse trailing edge 14 Ts note 1 t3 FPLINE period note 3 t4 FPLINE pulse width 9 Ts t5 MOD transition to FPLINE pulse trailing edge 1 note 4 Ts t6 FPSHIFT falling edge to FPLINE pulse leading edge note 5 t7 FPSHIFT falling edge to FPLINE pulse trailing edge note 6 t8 FPLINE pulse trailing edge to FPSHIFT falli...

Page 94: ...od REG 0Ah bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period REG 05h bits 4 0 1 8Ts FPLINE FPSHIFT UD 3 0 LD 3 0 FPFRAME FPLINE MOD UD2 UD1 UD0 LD3 LD2 LD1 LD0 UD3 MOD Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel VDP 1 2 1 6 1 638 1 3 1 7 1 639 1 4 1 8 1 640 241 1 241 5 241 637 241 638 241 639 241 640 1 1 1 5 ...

Page 95: ...ax Units t1 FPFRAME setup to FPLINE pulse trailing edge note 2 t2 FPFRAME hold from FPLINE pulse trailing edge 14 Ts note 1 t3 FPLINE period note 3 t4 FPLINE pulse width 9 Ts t5 MOD transition to FPLINE pulse trailing edge 1 note 4 Ts t6 FPSHIFT falling edge to FPLINE pulse leading edge note 5 t7 FPSHIFT falling edge to FPLINE pulse trailing edge note 6 t8 FPLINE pulse trailing edge to FPSHIFT fal...

Page 96: ...PSHIFT UD 3 0 LD 3 0 FPFRAME FPLINE MOD MOD Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel VDP HDP VNDP HNDP LINE 1 241 LINE 2 242 LINE 3 243 LINE 4 244 LINE 239 479 LINE 240 480 LINE 1 241 LINE 2 242 1 R1 1 G1 1 B1 1 R2 1 G2 1 B2 1 R3 1 G3 1 B3 1 R4 1 G4 1 B4 1 R5 1 G5 1 B5 1 R6 1 G6 1 B6 1 R7 1 G7 1 R8 1 G8 1 B8 1 B639 1 R640 1 G640 1 B640 241 B639 241 R640 ...

Page 97: ...FPFRAME setup to FPLINE pulse trailing edge note 2 t2 FPFRAME hold from FPLINE pulse trailing edge 14 Ts note 1 t3 FPLINE period note 3 t4 FPLINE pulse width 9 Ts t5 MOD transition to FPLINE pulse trailing edge 1 note 4 Ts t6 FPSHIFT falling edge to FPLINE pulse leading edge note 5 t7 FPSHIFT falling edge to FPLINE pulse trailing edge note 6 t8 FPLINE pulse trailing edge to FPSHIFT falling edge t1...

Page 98: ...G 05h bits 4 0 1 8Ts 9 VDP FPLINE FPSHIFT UD 7 0 LD 7 0 FPFRAME FPLINE MOD UD6 LD6 UD5 LD5 UD4 LD4 UD3 LD3 UD2 LD2 UD1 LD1 UD0 LD0 UD7 LD7 MOD VNDP Diagram drawn with 2 FPLINE vertical blank period 1 R1 241 R1 1 B3 241 B3 1 G638 241 G638 1 B1 241 B1 1 G4 241 G4 1 R639 241 R639 1 R2 241 R2 1 B4 241 B4 1 G639 241 G63 1 G2 241 G2 1 R5 241 R5 1 B639 241 B639 1 B2 241 B2 1 G5 241 G5 1 R640 241 R640 1 R...

Page 99: ...Units t1 FPFRAME setup to FPLINE pulse trailing edge note 2 t2 FPFRAME hold from FPLINE pulse trailing edge 14 Ts note 1 t3 FPLINE period note 3 t4 FPLINE pulse width 9 Ts t5 MOD transition to FPLINE pulse trailing edge 1 note 4 Ts t6 FPSHIFT falling edge to FPLINE pulse leading edge note 5 t7 FPSHIFT falling edge to FPLINE pulse trailing edge note 6 t8 FPLINE pulse trailing edge to FPSHIFT fallin...

Page 100: ... 09h bits 1 0 REG 08h bits 7 0 1 VNDP Vertical Non Display Period REG 0Ah bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period HNDP1 HNDP2 REG 05h bits 4 0 1 8Ts FPFRAME FPLINE LINE1 LINE480 1 1 1 1 1 1 1 2 1 2 1 2 1 640 1 640 1 640 FPLINE FPSHIFT DRDY R 5 1 G 5 0 B 5 1 R 5 1 G 5 0 B 5 1 VDP DRDY Note DRDY is used to indicate the first pixel Example Ti...

Page 101: ...e Functional Specification S1D13505 Issue Date 01 02 02 X23A A 001 14 Figure 7 43 TFT D TFD A C Timing t12 t7 FPLINE t8 t6 FPFRAME DRDY FPSHIFT 640 t9 FPLINE 2 1 639 R 5 1 t13 t2 t3 t16 t4 t5 t14 t15 t1 t11 t10 G 5 0 B 5 1 Note DRDY is used to indicate the first pixel t17 ...

Page 102: ...4 0 1 8 2 Table 7 32 TFT D TFD A C Timing Symbol Parameter Min Typ Max Units t1 FPSHIFT period 1 Ts note 1 t2 FPSHIFT pulse width high 0 45 Ts t3 FPSHIFT pulse width low 0 45 Ts t4 data setup to FPSHIFT falling edge 0 45 Ts t5 data hold from FPSHIFT falling edge 0 45 Ts t6 FPLINE cycle time note 2 t7 FPLINE pulse width low note 3 t8 FPFRAME cycle time note 4 t9 FPFRAME pulse width low note 5 t10 h...

Page 103: ...NDP Vertical Non Display Period REG 0Ah bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period HNDP1 HNDP2 REG 05h bits 4 0 1 8Ts Note The signals RED GREEN and BLUE are analog signals from the embedded DAC and represent the color components which make up each pixel VRTC HRTC LINE1 LINE480 1 1 1 2 1 640 HRTC RED GREEN BLUE RED GREEN BLUE VDP HDP VNDP HND...

Page 104: ...Figure 7 45 CRT A C Timing 1 t8 min REG 09h bits 1 0 REG 08h bits 7 0 1 REG 0Ah bits 6 0 1 lines 2 t9min REG 0Ch bits 2 0 1 lines 3 t12min REG 06h bits 4 0 1 8 Ts Symbol Parameter Min Typ Max Units t1 VRTC cycle time note 1 t2 VRTC pulse width low note 2 t3 VRTC falling edge to FPLINE falling edge phase difference note 3 t3 HRTC t1 VRTC t2 ...

Page 105: ...ng unless otherwise noted 8 2 1 Revision Code Register bits 7 2 Product Code Bits 5 0 This is a read only register that indicates the product code of the chip The product code for the S1D13505 is 000011 bits 1 0 Revision Code Bits 1 0 This is a read only register that indicates the revision code of the chip The revision code for the S1D13505F00A is 00 Table 8 1 S1D13505 Addressing CS M R Access 0 ...

Page 106: ...y FIFO is disabled REG 23h bit 7 1 and the Half Frame Buffer is disabled REG 1Bh bit 0 1 and the Ink Cursor is inactive Reg 27h bits 7 6 00 This condition also occurs when the CRT and LCD enable bits Reg 0Dh bits 1 0 have remained 0 since chip reset For further programming information see S1D13505 Programming Notes and Examples document number X23A G 003 xx Memory Configuration Register REG 01h RW...

Page 107: ...l Select When this bit 1 dual passive LCD panel is selected When this bit 0 single passive LCD panel is selected bit 0 TFT Passive LCD Panel Select When this bit 1 TFT D TFD panel is selected When this bit 0 passive LCD panel is selected bits 5 0 MOD Rate Bits 5 0 When the DRDY pin is configured as MOD this register controls the toggle rate of the MOD out put When this register is zero the MOD out...

Page 108: ...its 4 0 Horizontal Non Display Period Bits 4 0 These bits specify the horizontal non display period Horizontal non display period pixels Horizontal Non Display Period Bits 4 0 1 8 The recommended minimum value which should be programmed into this register is 3 32 pixels The maximum value which can be programmed into this register is 1Fh which gives a horizontal non display period of 256 pixels Not...

Page 109: ...en this bit 0 the FPLINE pulse is active low for TFT D TFD and active high for passive LCD bits 3 0 HRTC FPLINE Pulse Width Bits 3 0 For CRT and TFT D TFD these bits specify the pulse width of HRTC and FPLINE respectively For passive LCD FPLINE is automatically created and these bits have no effect HRTC FPLINE pulse width pixels HRTC FPLINE Pulse Width Bits 3 0 1 8 The maximum HRTC pulse width is ...

Page 110: ... period is indicated When this bit 0 a vertical display period is indicated bits 5 0 Vertical Non Display Period Bits 5 0 These bits specify the vertical non display period Vertical non display period lines Vertical Non Display Period Bits 5 0 1 Note This register must be programmed such that REG 0Ah 1 and REG 0Ah bits 5 0 1 REG 0Bh 1 REG 0Ch bits 2 0 1 Vertical Display Height Register 0 REG 08h R...

Page 111: ...or passive LCD When this bit 1 the FPFRAME pulse is active high for TFT D TFD and active low for passive When this bit 0 the FPFRAME pulse is active low for TFT D TFD and active high for passive bits 2 0 VRTC FPFRAME Pulse Width Bits 2 0 For CRT and TFT D TFD these bits specify the pulse width of VRTC and FPFRAME respectively For passive LCD FPFRAME is automatically created and these bits have no ...

Page 112: ... used when the CRT and LCD have the same resolution e g 480 lines It is necessary to suit the vertical retrace period to the CRT This results in a lower LCD duty cycle 1 525 compared to the usual 1 481 This reduced duty cycle may result in lower contrast on the LCD 01 Line Doubling Each line is replicated on the CRT This mode is used to display a 240 line image on a 240 line LCD and stretch it to ...

Page 113: ... 1 and Screen 2 with Screen 1 above Screen 2 This 10 bit value specifies the height of Screen 1 Height of Screen 1 lines Screen 1 Line Compare Bits 9 0 1 If the height of Screen 1 is less than the display height then the remainder of the display is taken up by Screen 2 For normal operation no split screen this register must be set greater than the Vertical Display Height register e g set to the re...

Page 114: ...play Configuration for details Screen 1 Display Start Address Register 0 REG 10h RW Start Address Bit 7 Start Address Bit 6 Start Address Bit 5 Start Address Bit 4 Start Address Bit 3 Start Address Bit 2 Start Address Bit 1 Start Address Bit 0 Screen 1 Display Start Address Register 1 REG 11h RW Start Address Bit 15 Start Address Bit 14 Start Address Bit 13 Start Address Bit 12 Start Address Bit 1...

Page 115: ...anning can be achieved by a combination of this register and the Display Start Address registers See Section 10 Display Configuration for details bits 7 4 Screen 2 Pixel Panning Bits 3 0 Pixel panning bits for screen 2 bits 3 0 Screen 1 Pixel Panning Bits 3 0 Pixel panning bits for screen 1 Memory Address Offset Register 0 REG 16h RW Memory Address Offset Bit 7 Memory Address Offset Bit 6 Memory A...

Page 116: ...ios for selection of clock ratios 8 2 6 Power Save Configuration Registers bit 7 Power Save Status This is a read only status bit This bit indicates the power save state of the chip When this bit 1 the panel has been powered down and the memory controller is either in self refresh mode or is performing only CAS before RAS refresh cycles When this bit 0 the chip is either powered up in transition o...

Page 117: ...ble the Host Interface When this bit is high all memory and all registers except REG 1Ah read only and REG 1Bh are inaccessible bit 0 Half Frame Buffer Disable This bit is used to disable the Half Frame Buffer When this bit 1 the Half Frame Buffer is disabled When this bit 0 the Half Frame Buffer is enabled When a single panel is selected the Half Frame Buffer is automatically disabled and this bi...

Page 118: ... When this bit 1 the GPIO3 pin is configured as an output pin When this bit 0 default the GPIO3 pin is configured as an input pin bit 2 GPIO2 Pin IO Configuration When this bit 1 the GPIO2 pin is configured as an output pin When this bit 0 default the GPIO2 pin is configured as an input pin bit 1 GPIO1 Pin IO Configuration When this bit 1 the GPIO1 pin is configured as an output pin When this bit ...

Page 119: ... configured as an output see REG 1Eh a 1 in this bit drives GPIO1 high and a 0 in this bit drives GPIO1 low When GPIO1 is configured as an input a read from this bit returns the status of GPIO1 bit 7 GPO Control This bit is used to control the state of the SUSPEND pin when it is configured as General Purpose Output GPO When this bit 0 the GPO output is set to the reset state When this bit 1 the GP...

Page 120: ...r X23A G 003 xx bit 7 Reserved bits 6 5 RC Timing Value NRC Bits 1 0 These bits select the DRAM random cycle timing parameter tRC These bits specify the number NRC of MCLK periods TM used to create tRC NRC should be chosen to meet tRC as well as tRAS the RAS pulse width Use the following two formulae to calculate NRC then choose the larger value Note these formulae assume an MCLK duty cycle of 50 ...

Page 121: ...o select 2 MCLK for NRCD This is done to satisfy the CAS address setup time tASC The resulting tRC is related to NRCD as follows tRCD NRCD TM if EDO and NRP 1 or 2 tRCD 1 5 TM if EDO and NRP 1 5 tRCD NRCD 0 5 TM if FPM and NRP 1 or 2 tRCD NRCD TM if FPM and NRP 1 5 bits 3 2 RAS Precharge Timing Value NRP Bits 1 0 Minimum Memory Timing for RAS precharge These bits select the DRAM RAS Precharge timi...

Page 122: ...accesses When this bit 0 the display FIFO is enabled Note For further performance increase in dual panel mode disable the half frame buffer see section 8 2 7 and disable the cursor see section 8 2 9 Table 8 14 RAS Precharge Timing Select REG 22h bits 3 2 NRP RAS Precharge Width tRP 00 2 2 01 1 5 1 5 10 1 1 11 Reserved Reserved Table 8 15 Optimal NRC NRP and NRCD values at maximum MCLK frequency DR...

Page 123: ...Look Up Table Registers bits 7 0 LUT Address Bits 7 0 These 8 bits control a pointer into the Look Up Tables LUT The S1D13505 has three 256 posi tion 4 bit wide LUTs one for each of red green and blue refer to Look Up Table Architecture for details This register selects which LUT entry is read write accessible through the LUT Data Register REG 26h Writing the LUT Address Register automatically set...

Page 124: ...rsor FIFO depth required to sustain uninterrupted display fetches When these bits are all 0 the Ink Cursor FIFO depth is calculated automatically REG 29 bit 7 Reserved This bit must be set to 0 Look Up Table Data Register REG 26h RW LUT Data Bit 3 LUT Data Bit 2 LUT Data Bit 1 LUT Data Bit 0 n a n a n a n a Ink Cursor Control Register REG 27h RW Ink Cursor Mode Bit 1 Ink Cursor Mode Bit 0 n a n a ...

Page 125: ...egister must be set during VNDP vertical non display period Check the VNDP status bit REG 0Ah bit 7 to determine if you are in VNDP then update the register REG 2C bits 7 0 Ink Cursor Color 0 Bits 15 0 REG 2D bits 7 0 These bits define the 5 6 5 RGB Ink Cursor color 0 Cursor Y Position Register 0 REG 2Ah RW Cursor Y Position Bit 7 Cursor Y Position Bit 6 Cursor Y Position Bit 5 Cursor Y Position B...

Page 126: ...rd of line n 1 is calculated as follows Ink Address Offset words REG 04h 1 Cursor Address Offset words 8 Ink Cursor Color 1 Register 0 REG 2Eh RW Cursor Color 1 Bit 7 Cursor Color 1 Bit 6 Cursor Color 1 Bit 5 Cursor Color 1 Bit 4 Cursor Color 1 Bit 3 Cursor Color 1 Bit 2 Cursor Color 1 Bit 1 Cursor Color 1 Bit 0 Ink Cursor Color 1 Register 1 REG 2Fh RW Cursor Color 1 Bit 15 Cursor Color 1 Bit 14 C...

Page 127: ...he alternate FRM scheme may be used The alternate FRM scheme may produce more visually appealing output The following table shows the recommended alternate FRM scheme values Alternate FRM Register REG 31h RW Alternate FRM Bit 7 Alternate FRM Bit 6 Alternate FRM Bit 5 Alternate FRM Bit 4 Alternate FRM Bit 3 Alternate FRM Bit 2 Alternate FRM Bit 1 Alternate FRM Bit 0 Table 8 19 Recommended Alternate...

Page 128: ...ers and a half frame buffer A 512K byte display buffer is replicated in the 2M byte address space see the figure below Figure 9 1 Display Buffer Addressing Table 9 1 S1D13505 Addressing CS M R Access 0 0 Register access REG 00h is addressed when AB 5 0 0 REG 01h is addressed when AB 5 0 1 REG n is addressed when AB 5 0 n 0 1 Memory access the 2M byte display buffer is addressed by AB 20 0 1 X S1D1...

Page 129: ... There may be several Ink Cursor images stored in the display buffer but only one may be active at any given time See Ink Cursor Architecture on page 133 for details 9 3 Half Frame Buffer In dual panel mode with the half frame buffer enabled the top of the display buffer is allocated to the half frame buffer The size of the half frame buffer is a function of the panel resolution and whether the pa...

Page 130: ...ory Panel Display P0P1P2 P3P4P5P6 P7 2 bpp A0 B0 A1 B1 A2 B2 A3 B3 Host Address Display Memory A4 B4 A5 B5 A6 B6 A7 B7 bit 7 bit 0 bit 7 bit 0 4 bpp A0 B0 C0 D0 A1 B1 C1 D1 Host Address Display Memory A2 B2 C2 D2 A3 B3 C3 D3 bit 7 bit 0 A4 B4 C4 D4 A5 B5 C5 D5 Host Address Display Memory bit 7 bit 0 8 bpp A0 B0 C0 D0 E0 F0 G0 H0 A1 B1 C1 D1 E1 F1 G1 H1 A2 B2 C2 D2 E2 F2 G2 H2 Byte 0 Byte 0 Byte 1 ...

Page 131: ... Address Display Memory bit 7 bit 0 Panel Display P0P1P2 P3P4P5P6 P7 R0 3 R0 2 R0 1 R0 0 G0 4 G0 3 G0 2 G0 1 G0 0 B0 4 B0 3 B0 2 B0 1 B0 0 G1 2 G1 1 G1 0 B1 4 B1 3 B1 2 B1 1 B1 0 16 bpp R0 4 Host Address Display Memory bit 7 bit 0 R0 3 R0 2 R0 1 R0 0 G0 5 G0 4 G0 3 G0 2 G0 1 G0 0 B0 4 B0 3 B0 2 B0 1 B0 0 R1 4 R1 3 R1 2 R1 1 R1 0 G1 5 G1 4 G1 3 G1 2 G1 1 G1 0 B1 4 B1 3 B1 2 B1 1 B1 0 5 6 5 RGB 5 5 ...

Page 132: ...ines the starting word of the Screen 1 REG 15h REG 14h REG 13 defines the starting word of the Screen 2 REG 18h bits 3 0 define the starting pixel within the starting word for Screen 1 REG 18h bits 7 4 define the starting pixel within the starting word for Screen 2 REG 0Fh REG 0Eh define the last line of Screen 1 the remainder of the display is taken up by Screen 2 Figure 10 3 Image Manipulation R...

Page 133: ...es The green Look Up Table LUT is used for all monochrome modes 1 Bit per pixel Monochrome mode Figure 11 1 1 Bit per pixel Monochrome Mode Data Output Path 2 Bit per pixel Monochrome Mode Figure 11 2 2 Bit per pixel Monochrome Mode Data Output Path Green Look Up Table 256x4 00 01 FC FD FE FF 1 bit per pixel data 4 bit Grey Data from Image Buffer 0 1 Green Look Up Table 256x4 00 01 02 03 FC FD FE ...

Page 134: ... Date 01 02 02 4 Bit per pixel Monochrome Mode Figure 11 3 4 Bit per pixel Monochrome Mode Data Output Path Green Look Up Table 256x4 00 01 02 03 FC FD FE FF 0000 0001 4 bit per pixel data 4 bit Grey Data from Image Buffer 0010 0011 04 05 06 07 0100 0101 0110 0111 08 09 0A 0B 0C 0D 0E 0F 1000 1001 1010 1011 1100 1101 1110 1111 ...

Page 135: ... 001 14 11 2 Color Modes 1 Bit per pixel Color Mode Figure 11 4 1 Bit per pixel Color Mode Data Output Path Red Look Up Table 256x4 00 01 FC FD FE FF 1 bit per pixel data from Image Buffer Green Look Up Table 256x4 00 01 FC FD FE FF Blue Look Up Table 256x4 00 01 FC FD FE FF 0 1 0 1 0 1 4 bit Red Data 4 bit Green Data 4 bit Blue Data ...

Page 136: ... per pixel Color Mode Figure 11 5 2 Bit per pixel Color Mode Data Output Path Red Look Up Table 256x4 00 01 02 03 FC FD FE FF 00 01 2 bit per pixel data 4 bit Red Data from Image Buffer 10 11 Green Look Up Table 256x4 00 01 02 03 FC FD FE FF 00 01 4 bit Green Data 10 11 Blue Look Up Table 256x4 00 01 02 03 FC FD FE FF 00 01 4 bit Blue Data 10 11 ...

Page 137: ... 4 bit Red Data from Image Buffer 0010 0011 04 05 06 07 0100 0101 0110 0111 08 09 0A 0B 0C 0D 0E 0F 1000 1001 1010 1011 1100 1101 1110 1111 Green Look Up Table 256x4 00 01 02 03 FC FD FE FF 0000 0001 4 bit Green Data 0010 0011 04 05 06 07 0100 0101 0110 0111 08 09 0A 0B 0C 0D 0E 0F 1000 1001 1010 1011 1100 1101 1110 1111 Blue Look Up Table 256x4 00 01 02 03 FC FD FE FF 0000 0001 4 bit Blue Data 00...

Page 138: ...fer 0000 0010 0000 0011 04 05 06 07 0000 0100 0000 0101 0000 0110 0000 0111 F8 F9 FA FB FC FD FE FF 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111 Green Look Up Table 256x4 00 01 02 03 0000 0000 0000 0001 4 bit Green Data 0000 0010 0000 0011 04 05 06 07 0000 0100 0000 0101 0000 0110 0000 0111 F8 F9 FA FB FC FD FE FF 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100...

Page 139: ... offset from the starting word of line n to the starting word of line n 1 is calculated as follows Ink Address Offset words REG 04h 1 Cursor Address Offset words 8 12 2 Ink Cursor Data Format The Ink Cursor image is always 2 bit per pixel The following diagram shows the Ink Cursor data format for a little endian system Figure 12 1 Ink Cursor Data Format Table 12 1 Ink Cursor Start Address Encoding...

Page 140: ...4 pixels The Cursor X Position and Cursor Y Position registers specify the position of the top left pixel The following diagram shows how to position a cursor Figure 12 2 Cursor Positioning where x REG 29h bits 1 0 REG 28h REG 29h bit 7 0 y REG 2Bh bits 1 0 REG 2Ah REG 2Bh bit 7 0 Note There is no means to set a negative cursor position If a cursor must be set to a negative position this must be d...

Page 141: ...ual image The following figures show how the programmer sees the image and how the image is actually stored in the display buffer The display is refreshed in the following sense C A D B The application image is written to the S1D13505 in the following sense A B C D The S1D13505 rotates and stores the application image in the following sense C A D B the same sense as display refresh Figure 13 1 Rel...

Page 142: ...ress Panning of the portrait window to the right by 1 pixel is achieved by adding 1024 pixels to the Display Start Address register or subtracting if panning to the left Panning to right by 1 pixel add current start address by 1024 16 bpp mode or 512 8 bpp mode Panning to left by 1 pixel subtract current start address by 1024 16 bpp mode or 512 8 bpp mode How far the portrait window can be panned ...

Page 143: ...hysical Memory Half Frame Buffer Memory 2048 for 16 bpp mode Physical Memory Half Frame Buffer Memory 1024 for 8 bpp mode For example a 640 480 single panel running 8 bpp mode requires 480K byte of image buffer and 0K byte of half frame buffer memory The virtual display size is 1024 1024 1M byte The programmer may use a 512K byte DRAM which is smaller than the 1M byte virtual display but greater t...

Page 144: ...e Required for SwivelView Panel Size Panel Type Display Mode Display Buffer Size Half Frame Buffer Size Minimum DRAM Size Sprite Ink Layer Buffer Size Ink Cursor Layer Location 320 240 Single Color 8 bpp 240KB 0KB 512KB 1KB 18 75KB 496KB 480KB 16 bpp 480KB Mono 8 bpp 240KB 16 bpp 480KB Dual Color 8 bpp 240KB 18 75KB 480KB 464KB 16 bpp 480KB 480KB Mono 8 bpp 240KB 4 69KB 496KB 480KB 16 bpp 480KB 64...

Page 145: ... with Half Frame Buffer Enabled Simultaneous CRT Dual Color Panel with Half Frame Buffer Enable 5 MCLK 2 MCLK 2 MCLK 2 MCLK 3 MCLK 3 4 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 3 3 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 3 on Single Panel CRT Dual Monochrome Color Panel with Half Frame Buffer Disabled Simultaneous CRT Single Panel Simultaneous CRT Dual Monochrome Color Panel with Half Frame Buffer Disabled 5 MCLK...

Page 146: ...r Enabled Simultaneous CRT Dual Color Panel with Half Frame Buffer Enable 5 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 3 4 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 3 3 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 2 on Single Panel CRT Dual Monochrome Color Panel with Half Frame Buffer Disabled Simultaneous CRT Single Panel Simultaneous CRT Dual Monochrome Color Panel with Half Frame Buffer Disabled 5 MCLK 2 MCLK 2 MCLK 2 MCLK ...

Page 147: ... Type1 Speed Grade Display Resolution Color Depth bpp Maximum Pixel Clock MHz Minimum Panel HNDP Ts Maximum Frame Rate Hz Panel4 CRT 50ns EDO DRAM MClk 40MHz NRC 4 NRP 1 5 NRCD 2 Single Panel CRT Dual Monochrome Color Panel with Half Frame Buffer Disabled 5 Simultaneous CRT Single Panel Simultaneous CRT Dual Monochrome Color Panel with Half Frame Buffer Disabled 5 800x6002 1 2 4 8 40 32 80 60 15 1...

Page 148: ...Frame Buffer Enabled Dual Mono with Half Frame Buffer Enabled 800x6002 3 1 2 4 8 16 5 32 66 15 166 11 32 43 640x480 1 2 4 8 16 5 32 103 15 16 11 32 68 60ns FPM DRAM MClk 25MHz NRC 4 NRP 1 5 NRCD 2 Single Panel CRT Dual Mono Color Panel with Half Frame Buffer Disabled 5 Simultaneous CRT Single Panel Simultaneous CRT Dual Mono Color Panel with Half Frame Buffer Disabled 5 800x6002 1 2 4 8 25 32 50 1...

Page 149: ...efresh The CPU bandwidth during this period is called the bandwidth during non display period To calculate the average bandwidth calculate the percentage of time between display period and non display period The percentage of display period is multiplied with the bandwidth during display period The percentage of non display period is multiplied with the bandwidth during non display period The two ...

Page 150: ...achieved during non display periods Average Bandwidth All displays have a horizontal non display period and a vertical non display period The formula for calculating the percentage of non display period is as follows Percentage of non display period HTOT VTOT WIDTH HEIGHT HTOT VTOT Percentage of non display period for CRT 800 525 640 480 800 525 26 6 Percentage of non display period for single pan...

Page 151: ...th Half Frame Buffer Enabled 40 6 27 5 11 20 6 67 6 67 6 67 6 67 3 94 13 3 6 67 6 67 6 67 6 67 6 67 Simultaneous CRT Dual Mono Panel with Half Frame Buffer Enable 40 6 36 5 44 Dual Color Panel with Half Frame Buffer Enabled 20 6 67 6 67 6 27 6 27 13 3 6 67 6 67 6 67 6 67 6 67 60ns EDO DRAM MCLK 33MHz CRT Simultaneous CRT Single Panel Simultaneous CRT Dual Monochrome Color Panel with Half Frame Buf...

Page 152: ...Disabled 25 4 16 4 16 4 16 3 92 0 26 12 5 4 16 4 16 4 16 4 16 4 16 Dual Monochrome with Half Frame Buffer Enabled 25 3 92 3 19 12 5 4 16 4 16 4 16 4 16 2 46 8 3 4 16 4 16 4 16 4 16 4 16 Simultaneous CRT Dual Monochrome Panel with Half Frame Buffer Enable 25 3 97 3 40 Dual Color Panel with Half Frame Buffer Enabled 12 5 4 16 4 16 4 16 3 92 8 33 4 16 4 16 4 16 4 16 4 16 Table 14 6 Theoretical Maximu...

Page 153: ...ware suspend then revert the polarity bits back to the configuration state For hardware suspend an external hardware solution would be to use an AND gate on the sync signal One input of the AND gate is connected to a sync signal the other input would be tied to the panel s logic power supply When the panel s logic power supply is removed the sync signal is forced low Table 15 1 Power Save Mode Fun...

Page 154: ...are Functional Specification X23A A 001 14 Issue Date 01 02 02 16 Mechanical Data Figure 16 1 Mechanical Drawing QFP15 128 pin QFP15 surface mount package 1 32 96 65 64 33 97 128 Index 0 10 14 0 0 1 14 0 0 1 16 0 0 4 16 0 0 4 0 4 0 16 0 1 1 4 0 1 0 125 0 1 1 0 0 5 0 2 Unit mm 0 1 ...

Page 155: ...cument but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Eps...

Page 156: ...Page 2 Epson Research and Development Vancouver Design Center S1D13505 Programming Notes and Examples X23A G 003 07 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 157: ... Organization for Fifteen Bit Per Pixel 32768 Colors 16 Gray Shades 18 3 1 6 Memory Organization for Sixteen Bit Per Pixel 65536 Colors 16 Gray Shades 19 4 Look Up Table LUT 20 4 1 Look Up Table Registers 20 4 2 Look Up Table Organization 21 5 Advanced Techniques 29 5 1 Virtual Display 29 5 1 1 Registers 30 5 1 2 Examples 31 5 2 Panning and Scrolling 31 5 2 1 Registers 32 5 2 2 Examples 33 5 3 Spl...

Page 158: ...us Display 51 10 Identifying the S1D13505 52 11 Hardware Abstraction Layer HAL 53 11 1 Introduction 53 11 2 Contents of the HAL_STRUCT 53 11 3 Using the HAL library 54 11 4 API for 13505HAL 54 11 5 Initialization 56 11 5 1 General HAL Support 58 11 5 2 Advanced HAL Functions 62 11 5 3 Register Memory Access 64 11 5 4 Color Manipulation 67 11 5 5 Drawing 69 11 5 6 Hardware Cursor 71 11 5 7 Ink Laye...

Page 159: ...xamples S1D13505 Issue Date 01 02 05 X23A G 003 07 12 Sample Code 84 12 1 Introduction 84 12 1 1 Sample code using the S1D13505 HAL API 84 12 1 2 Sample code without using the S1D13505 HAL API 86 12 1 3 Header Files 95 Appendix A Supported Panel Values 107 A 1 Supported Panel Values 107 ...

Page 160: ...Page 6 Epson Research and Development Vancouver Design Center S1D13505 Programming Notes and Examples X23A G 003 07 Issue Date 01 02 05 ...

Page 161: ...6 Color Palette 24 Table 4 6 Recommended LUT Values for 1 Bpp Gray Shade 26 Table 4 7 Suggested Values for 2 Bpp Gray Shade 26 Table 4 8 Suggested LUT Values for 4 Bpp Gray Shade 27 Table 5 1 Number of Pixels Panned Using Start Address 33 Table 5 2 Active Pixel Pan Bits 33 Table 6 1 Suspend Refresh Selection 41 Table 7 1 Ink Cursor Mode 44 Table 7 2 Cursor Ink Start Address Encoding 46 Table 11 1 ...

Page 162: ...Page 8 Epson Research and Development Vancouver Design Center S1D13505 Programming Notes and Examples X23A G 003 07 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 163: ...age for 8 Bpp 256 Colors 16 Gray Shades in One Byte of Display Buffer 18 Figure 3 5 Pixel Storage for 15 Bpp 32768 Colors 16 Gray Shades in Two Bytes of Display Buffer 18 Figure 3 6 Pixel Storage for 16 Bpp 65536 Colors 16 Gray Shades in Two Bytes of Display Buffer 19 Figure 5 1 Viewport Inside a Virtual Display 30 Figure 5 2 Memory Address Offset Registers 30 Figure 5 3 Screen 1 Start Address Reg...

Page 164: ...Page 10 Epson Research and Development Vancouver Design Center S1D13505 Programming Notes and Examples X23A G 003 07 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 165: ...nced techniques used and the special features of the S1D13505 The guide also introduces the Hardware Abstraction Layer HAL which is designed to simplify the programming of the S1D13505 Most S1D1350x and S1D1370x products support the HAL allowing OEMs to switch chips with relative ease This document is updated as appropriate Please check the Epson Electronics America Website at http www eea epson c...

Page 166: ...0000h For further information on ISA evaluation boards refer to the S5U13505B00C Rev 1 0 ISA Bus Evaluation Board User Manual document number X23A G 004 xx The following table represents the sequence and values written to the S1D13505 registers to control a configuration with these specifications 640x480 color dual passive format 1 LCD 75Hz 8 bit data interface 8 bit per pixel bpp 256 colors 31 5 ...

Page 167: ...set to 0 This will start the display in the first byte of the display buffer 11 0000 0000 12 0000 0000 13 0000 0000 Screen 2 Start Address Regs 13h 14h and 15h to offset 0 Screen 2 Start Address in not used at this time 14 0000 0000 15 0000 0000 16 0100 0000 Memory Address Offset Regs 17h 16h 640 pixels 640 bytes 320 words 140h words Note When setting a horizontal resolution greater than 767 pixel...

Page 168: ...ite them to zero as this is the power up value for the registers 26 0000 0000 27 0000 0000 28 0000 0000 29 0000 0000 2A 0000 0000 2B 0000 0000 2C 0000 0000 2D 0000 0000 2E 0000 0000 2F 0000 0000 30 0000 0000 31 0000 0000 23 0000 0000 Enable FIFO mask in appropriate FIFO threshold bits S1D13505 Hardware Functional Specification document number X23A A 001 xx 0D 0000 1101 Display mode hardware portra...

Page 169: ...aks can disrupt the display buffer fetches This disruption produces a visible flicker on the display To avoid this set the Memory Address Offset Reg 16h and Reg 17h to 200h This sets a 1024 pixel line which aligns the memory page breaks and reduces any flicker Half Frame Buffer Disable The half frame buffer stores the display data for dual drive LCD panels During LCD only or simultaneous display u...

Page 170: ...further information on the display buffer see the S1D13505 Hardware Functional Specification document number X23A A 001 xx 3 1 1 Memory Organization for One Bit Per Pixel 2 Colors Gray Shades Figure 3 1 Pixel Storage for 1 Bpp 2 Colors Gray Shades in One Byte of Display Buffer In this memory format each byte of display buffer contains eight adjacent pixels Setting or resetting any pixel will requi...

Page 171: ...e Look Up Table 3 1 3 Memory Organization for Four Bit Per Pixel 16 Colors Gray Shades Figure 3 3 Pixel Storage for 4 Bpp 16 Colors Gray Shades in One Byte of Display Buffer In this memory format each byte of display buffer contains two adjacent pixels Setting or resetting any pixel will require reading the entire byte masking out the upper or lower nibble 4 bits and setting the appropriate bits t...

Page 172: ...ation for Fifteen Bit Per Pixel 32768 Colors 16 Gray Shades Figure 3 5 Pixel Storage for 15 Bpp 32768 Colors 16 Gray Shades in Two Bytes of Display Buffer In 15 bit per pixel mode the S1D13505 is capable of displaying 32768 colors The 32768 color pixel is divided into four parts one reserved bit five bits for red five bits for green and five bits for blue In this mode the Look Up Table is bypassed...

Page 173: ...tor The full color range is only available on TFT D TFD or CRT displays Passive LCD displays are limited to using the four most significant bits from each of the red green and blue portions of each color The result is 4096 24 24 24 possible colors When monochrome mode is selected the green component of the LUT is used to determine the gray shade intensity The green indices with only four bits can ...

Page 174: ...nto the LUT and the amount of green at that index controls the intensity Monochrome mode look ups are done for the panel interface only The CRT interface always receives the RGB values from the Look Up Table 4 1 Look Up Table Registers LUT Address The LUT address register selects which of the 256 LUT entries will be accessed Writing to this register will select the red bank After three successive ...

Page 175: ... entry of 0Fh into the red LUT entry will result in a bright red output while a LUT entry of 5 would result in a dull red Table 4 1 Look Up Table Configurations Display Mode 4 Bit Wide Look Up Table Effective Gray Shade Colors on an Passive Panel RED GREEN BLUE 1 bpp gray 2 2 gray shades 2 bpp gray 4 4 gray shades 4 bpp gray 16 16 gray shades 8 bpp gray 16 16 gray shades 15 bpp gray 16 gray shades...

Page 176: ... in the LUT 1 index value being displayed The following table shows the recommended values for obtaining a black and white mode while in 1 bpp on a color panel 2 bpp color When the S1D13505 is configured for 2 bpp color mode only the first 4 entries of the LUT are used These four entries can be set to any desired values Each byte in the display buffer contains 4 adjacent pixels Each pair of bits i...

Page 177: ... and lower nibbles of the byte are used as indices into the LUT The following table shows LUT values that will simulate those of a VGA operating in 16 color mode Table 4 4 Suggested LUT Values to Simulate VGA Default 16 Color Palette Index Red Green Blue 00 00 00 00 01 00 00 0A 02 00 0A 00 03 00 0A 0A 04 0A 00 00 05 0A 00 0A 06 0A 0A 00 07 0A 0A 0A 08 00 00 00 09 00 00 0F 0A 00 0F 00 0B 00 0F 0F 0...

Page 178: ...0 70 81 40 30 70 C1 00 40 10 02 00 A0 00 42 F0 B0 70 82 50 30 70 C2 00 40 20 03 00 A0 A0 43 F0 D0 70 83 60 30 70 C3 00 40 30 04 A0 00 00 44 F0 F0 70 84 70 30 70 C4 00 40 40 05 A0 00 A0 45 D0 F0 70 85 70 30 60 C5 00 30 40 06 A0 50 00 46 B0 F0 70 86 70 30 50 C6 00 20 40 07 A0 A0 A0 47 90 F0 70 87 70 30 40 C7 00 10 40 08 50 50 50 48 70 F0 70 88 70 30 30 C8 20 20 40 09 50 50 F0 49 70 F0 90 89 70 40 30...

Page 179: ...70 60 EA 40 30 20 2B F0 B0 00 6B 50 00 70 AB 50 70 60 EB 40 30 20 2C F0 F0 00 6C 70 00 70 AC 50 70 70 EC 40 40 20 2D B0 F0 00 6D 70 00 50 AD 50 60 70 ED 30 40 20 2E 70 F0 00 6E 70 00 30 AE 50 60 70 EE 30 40 20 2F 40 F0 00 6F 70 00 10 AF 50 50 70 EF 30 40 20 30 00 F0 00 70 70 00 00 B0 00 00 40 F0 20 40 20 31 00 F0 40 71 70 10 00 B1 10 00 40 F1 20 40 30 32 00 F0 70 72 70 30 00 B2 20 00 40 F2 20 40 3...

Page 180: ...rtant to ensure that the red and blue components of the Look Up Table be set to the same intensity as the green component 1 bpp gray shade In 1 bpp gray shade mode only the first two entries of the green LUT are used All other LUT entries are unused 2 bpp gray shade In 2 bpp gray shade mode the first four green elements are used to provide values to the panel The remaining indices are unused Table...

Page 181: ...d in 8 and 16 bpp modes 15 bpp gray shade The Look Up Table is bypassed at this color depth hence programming the LUT is not necessary As with 8 bpp there are limitations to the colors which can be displayed In this mode the four most significant bits of green are used to set the absolute intensity of the image Four bits of green resolves to 16 colors Now however each pixel requires two bytes Tabl...

Page 182: ...he Look Up Table is bypassed at this color depth hence programming the LUT is not necessary As with 8 bpp there are limitations to the colors which can be displayed In this mode the four most significant bits of green are used to set the absolute intensity of the image Four bits of green resolves to 16 colors Now however each pixel requires two bytes ...

Page 183: ...set registers are used to determine the number of horizontal pixels in the virtual image The offset registers can be set for a maximum of 211 or 2048 words In 1 bpp display modes these 2048 words cover 16 384 pixels At 16 bpp 2048 words cover 1024 pixels The maximum vertical size of the virtual image is the result of a number of variables In its simplest the number of lines is the total display bu...

Page 184: ...does not necessarily represent the number of words to be shown on the display The display width is set in the Horizontal Display Width register If the offset is set to the same as the display width then there is no virtual width To maintain a constant virtual width as color depth changes the memory address offset must also change At 1 bpp each word contains 16 pixels at 16 bpp each word contains o...

Page 185: ...troduction on page 11 2 Determine the offset register value pixels_per_word 16 bpp 16 4 4 offset pixels_per_line pixels_per_word 640 4 160 words 0A0h words Register 17h will be written with 00h and register 16h will be written with A0h 3 Check that we have enough memory for the required virtual height Each line uses 160 words and we need 480 lines for a total of 160 480 76 800 words This display c...

Page 186: ...ine and must be set during the vertical non display period The correct sequence for programing these registers is 1 Wait until just after a vertical non display period read register 0Ah and watch bit 7 for the non display status 2 Update the start address registers 3 Wait until the next vertical non display period 4 Update the pixel paning register 5 2 1 Registers Figure 5 3 Screen 1 Start Address...

Page 187: ... pixel pan value is equal to the current color depth then set the pixel pan value to zero and increment the start address value To pan to the left decrement the pixel pan value If the pixel pan value is less than zero set it to the color depth bpp less one and decrement the start address Note Scrolling operations are easier to follow if a value call it pan_value is used to track both the pixel pan...

Page 188: ...egisters using the procedure outlined in the registers section Example 4 Scrolling Up and Down To scroll down increase the value in the Screen 1 Display Start Address Register by the number of words in one virtual scan line To scroll up decrease the value in the Screen 1 Display Start Address Register by the number of words in one virtual scan line Example 5 Scroll down one line for a 16 color 640...

Page 189: ...e 100 to scan line 239 Although this example picks specific values image 1 and image 2 can be shown as varying portions of the screen Figure 5 5 320x240 Single Panel For Split Screen 5 3 1 Registers The other registers required for split screen operations 10h through 12h Screen 1 Display Start Address and 18h Pixel Panning Register are described in Section 5 2 1 on page 32 Figure 5 6 Screen 1 Line...

Page 190: ...t to the first word in the display buffer that will be shown in the screen 2 portion of the display Screen 1 memory is always displayed first at the top of the screen followed by screen 2 memory The start address for the screen 2 image may be lower in memory than that of screen 1 i e screen 2 could be coming from offset 0 in the display buffer while screen 1 was coming from an offset located sever...

Page 191: ...n 1 is coming from offset 0 in the display buffer Although not necessary ensure that the screen 1 start address is set to zero Write 00h to registers 10h 11h and 12h 3 Calculate the size of the screen 1 image so we know where the screen 2 image is lo cated This calculation must be performed on the virtual size offset register of the display Since a virtual size was not specified assume the virtual...

Page 192: ...e LCD signals are shut down Power on requires the LCD signals to be active prior to applying power to the LCD This time interval varies depending on the LCD bias power supply design For example the LCD bias power supply on the S5U13505 Evaluation board requires approximately 0 5 seconds to fully discharge Your power supply design may vary For most applications internal power sequencing is the appr...

Page 193: ... 0 should be set to 1 to allow the S1D13505 to power on the LCD using the automatic LCD Power Sequencing 6 1 2 LCD Power Disable If the LCD bias power supply timing requirements are different than those timings built into the S1D13505 power disable sequence it may be necessary to manually power off an LCD panel One of two situations may be true Delay is too short Delay is too long Different proced...

Page 194: ...document number X23A A 001 xx at this time any clocks can be disabled 5 Enable any clocks that were disabled in step 4 6 Set REG 1Ah bit 0 to 0 Disables power save mode 7 Set REG 04h to original setting Set REG 08h to original setting Re initializes the original resolution 8 Set REG 023h bit 7 to 0 Un blanks screen by enabling the FIFO 6 2 Software Power Save The S1D13505 supports a software initi...

Page 195: ...d off and the memory is in a suspend memory refresh mode When this bit returns a 0 the S1D13505 is either powered on in transition of powering on or in transition of powering off REG 1Ah Power Save Configuration Register Power Save Status RO n a n a n a LCD Power Disable Suspend Refresh Select Bit 1 Suspend Refresh Select Bit 0 Software Suspend Mode Enable REG 1Ah Power Save Configuration Register...

Page 196: ... 3 Hardware Power Save The S1D13505 supports a hardware suspend power save mode This mode is not program mable by software It is controlled directly by the S1D13505 SUSPEND pin While hardware suspend is enabled the following conditions apply display s are inactive registers are not accessible memory is not accessible LUT is not accessible ...

Page 197: ...shape Contrast that with the hardware assisted system where the operating system must simply update the cursor X and cursor Y position registers An ink layer is used to support stylus or pen input Without an ink layer the operating system would have to save an area possibly all of the display buffer where pen input was to occur After the system recognized the user entered characters the display wo...

Page 198: ... 29h control the horizontal position of the hardware cursor The value in this register specifies the location of the left edge of the cursor When ink mode is selected these registers should be set to zero Cursor X Position bits 9 0 determine the horizontal location of the cursor With 10 bits of resolution the horizontal cursor range is 1024 pixels REG 27h Ink Cursor Control Register Ink Cursor Mod...

Page 199: ...tion Register 0 Reserved n a n a n a n a n a Cursor Y Position bit 9 Cursor Y Position bit 8 REG 2Ch Ink Cursor Color 0 Register 0 Cursor Color 0 bit 7 Cursor Color 0 bit 6 Cursor Color 0 bit 5 Cursor Color 0 bit 4 Cursor Color 0 bit 3 Cursor Color 0 bit 2 Cursor Color 0 bit 1 Cursor Color 0 bit 0 REG 2Dh Ink Cursor Color 0 Register 1 Cursor Color 0 bit 15 Cursor Color 0 bit 14 Cursor Color 0 bit ...

Page 200: ... to one will cause undefined cursor behavior 7 3 3 Reg 30h Bit 7 of register 30h is write only therefore programs cannot determine the current cursor ink layer start address by reading register 30h It is suggested that values written to this register be stored elsewhere and used when the current state of this register is required 7 3 4 No Top Left Clipping on Hardware Cursor The S1D13505 does not ...

Page 201: ...View option allows only 90 rotation The display image is rotated 90 in a clockwise direction allowing the panel to be mounted 90 counter clockwise from its normal orientation SwivelView also provides 180 and 270 rotation on some S1D13x0x products however the S1D13505 does not support 180 or 270 rotation 8 2 S1D13505 SwivelView The S1D13505 provides hardware support for SwivelView in 8 15 and 16 bp...

Page 202: ...grammer is accessing the Hardware Cursor or the Ink Layer Split screen images appear side by side i e when SwivelView is enabled the screen is split vertically Pixel panning works vertically REG 0Dh Display Mode Register SwivelView Enable Simultaneous Display Option Select Bit 1 Simultaneous Display Option Select Bit 0 Bit Per Pixel Select Bit 2 Bit Per Pixel Select Bit 1 Bit Per Pixel Select Bit ...

Page 203: ... Start Address registers form a pointer to a word therefore the value to set the start Write C0h 192 or 1024 480 2 to registers 10h 11h and 12h That is write Ch to register 10h 00h to register 11h and 00h to register 12h 3 Enable SwivelView by setting bit 7 of register 0Dh 4 The display is now configured for SwivelView Offset zero into display memory will correspond to the upper left corner of the...

Page 204: ...YTE dwAddr FFh SetRegister REG_SCRN1_DISP_START_ADDR1 BYTE dwAddr 8 FFh SetRegister REG_SCRN1_DISP_START_ADDR2 BYTE dwAddr 16 0Fh do register ReadRegister 0Ah while 80h register 80h 4 Write the pixel pan value during the vertical non display portion of the frame a Coming from the above code wait for beginning of the non display period do register ReadRegister 0Ah while 80h register 80h b Write the...

Page 205: ...ntact the Video Electronics Standards association on the world wide web at www vesa org 9 1 1 CRT Only All CRT output should meet VESA timing specifications The VESA specification details all the parameters of the display and non display times as well as the input clock required to meet the times Given a proper VESA input clock the configuration program 13505CFG EXE will generate correct VESA timi...

Page 206: ...en enabled The steps to identify the S1D13505 are 1 If using an ISA evaluation board in a PC follow steps a and b a If a reset has occurred confirm that 16 bit mode is enabled by writing to address F8 0000h b If hardware suspend is enabled then disable the suspend by writing to address F0 0000h 2 Enable the host interface by writing 00h to REG 1Bh 3 Read REG 00h 4 The production version of the S1D...

Page 207: ...ogram for a new target display or environment Using the HAL keeps sample code simpler although some programmers may find the HAL functions to be limited in their scope and may wish to program the S1D13505 without using the HAL 11 2 Contents of the HAL_STRUCT The HAL_STRUCT below is contained in the file hal h and is required to use the HAL library typedef struct tagHalStruct char szIdString 16 WOR...

Page 208: ...he HAL library functions have pointers as parameters The programmer should be aware that little validation of these pointers is performed so it is up to the programmer to ensure that they adhere to the interface and use valid pointers Programmers are recommended to use the highest warning levels of their compiler in order to verify the parameter types 11 4 API for 13505HAL This section is a descri...

Page 209: ...r seGetWordReg Read a Word value from the specified S1D13505 register seGetDwordReg Read a Dword value from the specified S1D13505 register seWriteDisplayBytes Write one or more bytes to the display buffer at the specified offset seWriteDisplayWords Write one or more words to the display buffer at the specified offset seWriteDisplayDwords Write one or more dwords to the display buffer at the speci...

Page 210: ...at x y from top left corner of cursor seDrawCursorLine Draw a line into the cursor memory from x1 y1 to x2 y2 in specified color seDrawCursorRect Draw a rectangle into the cursor memory from x1 y1 to x2 y2 in specified color seDrawCursorEllipse Draw an ellipse into the cursor memory centered at xc yc of radius xr yr in specified color seDrawCursorCircle Draw a circle into the cursor memory centere...

Page 211: ...oblems seSetInit int DevID Description This routine sets the S1D13505 registers for operation using the default settings Initialization of the S1D13505 is a two step process consisting of initializing the HAL seInitHal and initializing the S1D13505 registers seSetInit Unlike the HAL the registers do not necessarily require initialization at program startup and may be initialized as needed e g 1350...

Page 212: ... blank screen except for cursor or ink layer DISP_FIFO_ON default turn on display FIFO Return Value ERR_OK no problems encountered ERR_FAILED unable to complete operation Occurs as a result of an invalid register in the HAL_STRUCT See Also seDisplayFifo for enabling disabling the FIFO Example seSetDisplayMode DevID DISP_MODE_LCD CLEAR_MEM DISP_FIFO_OFF The above example will initialize for the LCD...

Page 213: ...inters of const char type to pass as parameters see Example below Parameters pVersion pointer to string of HAL version code pStatus pointer to string of HAL status code NULL is release pStatusRevision pointer to string of HAL statusRevision Return Value None Example const char pVersion pStatus pStatusRevision seGetHalVersion pVersion pStatus pStatusRevision Note This document was written for HAL v...

Page 214: ... Call seGetLastUsableByte any time the true end of usable memory is required Parameters DevID registered device ID pLastByte pointer to a DWORD to receive the offset to the last usable byte of display buffer Return Value ERR_OK operation completed with no problems int seGetBytesPerScanline int DevID UINT pBytes Description Determines the number of bytes per scan line of the current display mode It...

Page 215: ...not set to 8 or 16 Note This call applies to the S1D13505 ISA evaluation cards only int seGetHostBusWidth int DevID int Width Description This function retrieves the default as set by 13505CFG EXE value for the host bus interface width and returns it in Width Parameters DevID registered device ID Width integer to hold the returned value of the host bus width Return Value ERR_OK the function comple...

Page 216: ...cess the timers was not always immediately available we use the frame rate for timing calculations The S1D13505 registers must be initialized for this function to work correctly The PC platform version of seDelay calls the C timing functions and is therefore independent of the register settings Parameters DevID registered device ID Seconds time to delay in seconds Return Value ERR_OK operation com...

Page 217: ...he register values are used internally on the S1D13505 Setting the line compare register to zero results in one line of screen 1 being displayed followed by screen 2 Parameters DevID registered device ID WhichScreen must be set to 1 or 2 or use the constants SCREEN1 or SCREEN2 to identify which screen to base calculations on VisibleScanlines number of lines to show for the selected screen Return V...

Page 218: ... top left corner of the applicable display Parameter DevID registered device ID WhichScreen must be set to 1 or 2 or use the constants SCREEN1 or SCREEN2 to identify which screen to base calculations on x new starting X position in pixels y new starting Y position in pixels Return Value ERR_OK operation completed with no problems ERR_HAL_BAD_ARG there are several reasons for this return value 1 Wh...

Page 219: ...gister index to read pValue return value of the register Return Value ERR_OK operation completed with no problems int seGetWordReg int DevID int Index WORD pValue Description Reads the WORD sized value in the register specified by index Parameters DevID registered device ID Index register index to read pValue return value of the register Return Value ERR_OK operation completed with no problems int...

Page 220: ...o write Count number of words to write Return Value ERR_OK operation completed with no problems ERR_HAL_BAD_ARG if the value for Offset is greater than the amount of installed memory Note If offset count 2 memory size this function will limit the writes to the end of memory int seWriteDisplayDwords int DevID DWORD Offset DWORD Value DWORD Count Description Writes one or more dwords to the display ...

Page 221: ...rd int DevID DWORD Offset DWORD pDword Description Reads a dword from the display buffer at the specified offset and returns the value in pDword Parameters DevID registered device ID Offset offset from start of the display buffer pDword return value of the display buffer location Return Value ERR_OK operation completed with no problems ERR_HAL_BAD_ARG if the value for Offset is greater than the am...

Page 222: ...roblems int seSetLutEntry int DevID int Index BYTE pEntry Description This routine writes one LUT entry Unlike seSetLut the LUT entry indicated by Index can be any value from 0 to 255 A Look Up Table entry consists of three bytes one each for Red Green and Blue The color information is stored in the four most significant bits of each byte Parameters DevID registered device ID Index index to LUT en...

Page 223: ...ermine the current color depth and returns the result in pBitsPerPixel Determines the color depth of current display mode Parameters DevID registered device ID pBitsPerPixel return value is the current color depth 1 2 4 8 15 16 bpp Return Value ERR_OK operation completed with no problems 11 5 5 Drawing The Drawing section covers HAL functions that deal with displaying pixels lines and shapes int s...

Page 224: ...bpp Color refers to the pixel value which stores the red green and blue intensities within a WORD Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid int seDrawRect int DevID long x1 long y1 long x2 long y2 DWORD Color BOOL SolidFill Description This routine draws and optionally fills a rectangular area of display buffer The upper right corn...

Page 225: ...nter located at xc yc and a radius of Radius The circle will be drawn in the color specified in Color Parameters DevID registered device ID xc yc The center of the circle in pixels Radius the circles radius in pixels Color The color to draw the ellipse At 1 2 4 and 8 bpp Color is an index into the Look Up Table At 15 16 bpp Color defines the color directly i e rrrrrggggggbbbbb for 16 bpp SolidFill...

Page 226: ...led the cursor is invisible Parameters DevID a registered device ID Return Value ERR_OK operation completed with no problems int seGetCursorStartAddr int DevID DWORD Offset Description This function retrieves the offset to the first byte of hardware cursor memory Parameters DevID a registered device ID Offset a DWORD to hold the return value Return Value ERR_OK the operation completed with no prob...

Page 227: ...long y1 long x2 long y2 DWORD Color Description Draws a line between the two endpoints x1 y1 and x2 y2 in the hardware cursor display buffer using color Color The value of Color must be 0 to 3 Values 0 and 1 refer to the two user definable colors If Color is 2 then the pixel will be transparent and if the value is 3 the pixel will be an inversion of the underlying screen color Parameters DevID a r...

Page 228: ...of the underlying screen color Currently seDrawCursorEllipse does not support solid fill of the ellipse Parameters DevID a registered device ID xc yc center of the ellipse in pixels xr horizontal radius in pixels yr vertical radius in pixels Color 0 to 3 value to draw the pixels with SolidFill flag to solid fill the ellipse not currently used Return Value ERR_OK operation completed with no problem...

Page 229: ...to the transparent color and enabling the ink layer When this function returns the ink layer is enabled transparent and ready to be drawn on Parameters DevID a registered device ID Return Value ERR_OK operation completed with no problems ERR_FAILED if the ink layer cannot be enabled due to timing constraints this value will be returned int seInkOn int DevID Description Enables the ink layer after ...

Page 230: ...inable colors If Color is 2 then the pixel will be transparent and if the value is 3 the pixel will be an inversion of the underlying screen color Parameters DevID a registered device ID x y coordinates of the pixel to draw Color a 0 to 3 value to draw the pixel with Return Value ERR_OK operation completed with no problems int seDrawInkLine int DevID long x1 long y1 long x2 long y2 DWORD Color Des...

Page 231: ...e value is 3 the pixel will be an inversion of the underlying screen color This solid fill option is not yet available for this function Parameters DevID a registered device ID xc yc center point for the ellipse in pixels xr horizontal radius of the ellipse in pixels yr vertical radius of the ellipse in pixels Color a two bit value 0 to 3 to draw the rectangle with SolidFill flag to enable filling...

Page 232: ...DevID BOOL Suspend Description Causes the S1D13505 to enter leave hardware suspend mode This option in only supported on S1D13505B0B ISA evaluation boards When hardware suspend mode is engaged the display is disabled and display buffer is inaccessible and the registers and LUT are inaccessible Parameters DevID a registered device ID Suspend boolean flag to indicate which state to engage enter susp...

Page 233: ...ailable on the Epson Electronics America Website at http www eea epson com 11 6 1 Building the LIBSE library for SH3 target example In the LIBSE files there are three main types of files C files that contain the library functions assembler files that contain the target specific code makefiles that describe the build process to construct the library The C files are generic to all platforms although...

Page 234: ...ng a complete application for the target example The following source code is available on the Epson Electronics America Website at http www eea epson com include stdio h include Hal h include Appcfg h include Hal_regs h int main void define RED16BPP 0xf800 define GREEN16BPP 0x07e0 define BLUE16BPP 0x001f int main void int DevId UINT height width Bpp const char p1 p2 p3 DWORD color_red color_blue ...

Page 235: ...height ERR_OK printf r nERROR Unable to get screen size r n return 1 Determine the Bpp mode and set colors appropriately Note if less than 15Bpp set the color Lookup Table LUT local color variables contain either index into LUT or RGB value seGetBitsPerPixel DevId Bpp if verbose printf Bpp is d n Bpp switch Bpp case 1 Can t really do red and blue here seSetLut DevId BYTE RedBlue Lut 0 0 3 color_re...

Page 236: ...x y x1 width 4 x2 width 2 x1 y1 height 4 y2 height 2 y1 seDrawRect DevId x1 y1 x2 y2 color_red TRUE Draw a box around the screen if seDrawLine DevId 0 0 width 1 0 color_blue ERR_OK seDrawLine DevId 0 height 1 width 1 height 1 color_blue ERR_OK seDrawLine DevId 0 0 0 height 1 color_blue ERR_OK seDrawLine DevId width 1 0 width 1 height 1 color_blue ERR_OK printf r nERROR Unable to draw box r n retur...

Page 237: ...d Development Page 83 Vancouver Design Center Programming Notes and Examples S1D13505 Issue Date 01 02 05 X23A G 003 07 Delay for 2 seconds seDelay DevId DWORD 2 Move the cursor seMoveCursor DevId width 1 63 0 return 0 ...

Page 238: ...e some of the structures used clearer 12 1 1 Sample code using the S1D13505 HAL API Sample code using 1355HAL API Created 1998 Epson Research Development Vancouver Design Centre Copyright c Epson Research and Development Inc 1998 All rights reserved The HAL API code is configured for the following 25 175 MHz ClkI 640x480 8 bit dual color STN panel 60Hz 50 ns EDO 32 ms self refresh time Initial col...

Page 239: ...d an SED1355 seGetId Device ChipId if ID_SED1355F0A ChipId printf nERROR Did not detect SED1355 exit 1 Initialize the SED1355 This step will actually program the registers with values taken from the default register table in appcfg h if ERR_OK seSetInit Device printf nERROR Could not initialize device exit 1 The default initialization clears the display Draw a 100x100 red rectangle in the upper le...

Page 240: ...ple code demonstrating the initialization of the SED1355 Beta release 2 0 98 10 29 The code in this example will perform initialization to the following specification 640 x 480 dual 16 bit color passive panel 75 Hz frame rate 8 BPP 256 colors 33 MHz input clock 2 MB of 60 ns EDO memory This is sample code only This means 1 Generic C is used I assume that pointers can access the relevant memory add...

Page 241: ...00 0x00 0x70 0x00 0x00 0x80 0x00 0x00 0x90 0x00 0x00 0xA0 0x00 0x00 0xB0 0x00 0x00 0xC0 0x00 0x00 0xD0 0x00 0x00 0xE0 0x00 0x00 0xF0 0x00 0x00 Black to green 0x00 0x00 0x00 0x00 0x10 0x00 0x00 0x20 0x00 0x00 0x30 0x00 0x00 0x40 0x00 0x00 0x50 0x00 0x00 0x60 0x00 0x00 0x70 0x00 0x00 0x80 0x00 0x00 0x90 0x00 0x00 0xA0 0x00 0x00 0xB0 0x00 0x00 0xC0 0x00 0x00 0xD0 0x00 0x00 0xE0 0x00 0x00 0xF0 0x00 Bl...

Page 242: ... 0xF0 Black to magenta blue and red 0x00 0x00 0x00 0x10 0x00 0x10 0x20 0x00 0x20 0x30 0x00 0x30 0x40 0x00 0x40 0x50 0x00 0x50 0x60 0x00 0x60 0x70 0x00 0x70 0x80 0x00 0x80 0x90 0x00 0x90 0xA0 0x00 0xA0 0xB0 0x00 0xB0 0xC0 0x00 0xC0 0xD0 0x00 0xD0 0xE0 0x00 0xE0 0xF0 0x00 0xF0 Black to cyan blue and green 0x00 0x00 0x00 0x00 0x10 0x10 0x00 0x20 0x20 0x00 0x30 0x30 0x00 0x40 0x40 0x00 0x50 0x50 0x00 ...

Page 243: ...et DISP_MEM_SIZE X 8192 We want the offset to be just past the end of display memory so 640 480 DISP_MEMORY_SIZE X 8192 CURSOR_START DISP_MEMORY_SIZE 640 480 8192 define CURSOR_START 218 void main void unsigned char pRegs REGISTER_OFFSET unsigned char pMem unsigned char pLUT unsigned char pTmp unsigned char pCursor long lpCnt int idx int rgb long x y Initialize the chip Step 1 Enable the host inte...

Page 244: ... Horizontal Display Width HDP 640 pixels 640 8 1 79t 4Fh pRegs 0x04 0x4f 0100 1111 Register 5 Horizontal Non Display Period HNDP PCLK Frame Rate HDP HNDP VDP VNDP 16 500 000 640 HNDP 480 VNDP HNDP and VNDP must be calculated such that the desired frame rate is achieved pRegs 0x05 0x1F 0001 1111 Register 6 HRTC FPLINE Start Position applicable to CRT TFT only pRegs 0x06 0x00 0000 0000 Register 7 HR...

Page 245: ...d pRegs 0x0D 0x0C 0000 1100 Registers E F Screen 1 Line Compare unless setting up for split screen operation use 0x3FF pRegs 0x0E 0xFF 1111 1111 pRegs 0x0F 0x03 0000 0011 Registers 10 12 Screen 1 Display Start Address start at the first byte in display memory pRegs 0x10 0x00 0000 0000 pRegs 0x11 0x00 0000 0000 pRegs 0x12 0x00 0000 0000 Register 13 15 Screen 2 Display Start Address not applicable u...

Page 246: ...only but it s OK to write a 0 to keep the register configuration logic simpler pRegs 0x1C 0x00 0000 0000 pRegs 0x1D 0x00 0000 0000 Register 1E 1F General I O Pins Configuration pRegs 0x1E 0x00 0000 0000 pRegs 0x1F 0x00 0000 0000 Register 20 21 General I O Pins Control pRegs 0x20 0x00 0000 0000 pRegs 0x21 0x00 0000 0000 Registers 24 26 LUT control For this example do a typical 8 BPP LUT setup Setup...

Page 247: ... Registers 2E 2F Ink Cursor Color 1 green pRegs 0x2E 0xE0 1110 0000 pRegs 0x2F 0x07 0000 0111 Register 30 Ink Cursor Start Address Select pRegs 0x30 0x00 0000 0000 Register 31 Alternate FRM Register pRegs 0x31 0x00 Register 23 Performance Enhancement display FIFO enabled optimum performance The FIFO threshold is set to 0x00 for 15 16 bpp modes set the FIFO threshold to a higher value such as 0x1B ...

Page 248: ...lf frame buffer Additionally the HW cursor can be turned into an ink layer quite easily from this location pRegs 0x30 CURSOR_START pTmp pCursor pMem DISP_MEMORY_SIZE CURSOR_START 8192L Set the contents of the cursor memory such that the cursor is transparent To do so write a 10101010b pattern in each byte The cursor is 2 bpp so a 64x64 cursor requires 64 4 64 1024 bytes of memory for lpCnt 0 lpCnt...

Page 249: ...wait while in VDP Now update the position registers pRegs 0x28 100 Set Cursor X 100 pRegs 0x29 0x00 pRegs 0x2A 100 Set Cursor Y 100 pRegs 0x2B 0x00 Enable the hardware cursor pRegs 0x27 0x40 12 1 3 Header Files The following header files are included as they help to explain some of the structures used when programming the S1D13505 The following header file defines the structure used to store the c...

Page 250: ...0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 CRT 0x00 0x50 0x16 0x00 0x4F 0x13 0x01 0x0B 0xDF 0x01 0x2B 0x09 0x01 0x0E 0xFF 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x40 0x01 0x00 0x00 0x02 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x48 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 SIMUL 0xFF 0x50 0x16 0x00 0x4F 0x13 0x01 0x0B 0xDF 0x01 0x2B 0x09 0x01 0x0F 0xFF 0x03 0x00 ...

Page 251: ..._CONFIG 0x01 define REG_PANEL_TYPE 0x02 define REG_MOD_RATE 0x03 define REG_HORZ_DISP_WIDTH 0x04 define REG_HORZ_NONDISP_PERIOD 0x05 define REG_HRTC_START_POSITION 0x06 define REG_HRTC_PULSE_WIDTH 0x07 define REG_VERT_DISP_HEIGHT0 0x08 define REG_VERT_DISP_HEIGHT1 0x09 define REG_VERT_NONDISP_PERIOD 0x0A define REG_VRTC_START_POSITION 0x0B define REG_VRTC_PULSE_WIDTH 0x0C define REG_DISPLAY_MODE 0...

Page 252: ...T_DATA 0x26 define REG_INK_CURSOR_CONTROL 0x27 define REG_CURSOR_X_POSITION0 0x28 define REG_CURSOR_X_POSITION1 0x29 define REG_CURSOR_Y_POSITION0 0x2A define REG_CURSOR_Y_POSITION1 0x2B define REG_INK_CURSOR_COLOR0_0 0x2C define REG_INK_CURSOR_COLOR0_1 0x2D define REG_INK_CURSOR_COLOR1_0 0x2E define REG_INK_CURSOR_COLOR1_1 0x2F define REG_INK_CURSOR_START_ADDR 0x30 define REG_ALTERNATE_FRM 0x31 W...

Page 253: ...typedef int BOOL ifdef INTEL typedef BYTE far LPBYTE typedef WORD far LPWORD typedef DWORD far LPDWORD else typedef BYTE LPBYTE typedef WORD LPWORD typedef DWORD LPDWORD endif ifndef LOBYTE define LOBYTE w BYTE w endif ifndef HIBYTE define HIBYTE w BYTE UINT w 8 0xFF endif ifndef LOWORD define LOWORD l WORD DWORD l endif ifndef HIWORD define HIWORD l WORD DWORD l 16 0xFFFF endif ifndef MAKEWORD de...

Page 254: ...VERSION is the size of the version string eg 1 00 SIZE_STATUS is the size of the status string eg b for beta SIZE_REVISION is the size of the status revision string eg 00 define SIZE_VERSION 5 define SIZE_STATUS 2 define SIZE_REVISION 3 ifdef ENABLE_DPF Debug_printf define DPF exp printf exp n define DPF1 exp printf exp d n exp define DPF2 exp1 exp2 printf exp1 d exp2 d n exp1 exp2 define DPFL exp...

Page 255: ...AL_BAD_ARG ERR_TOOMANY_DEVS ERR_INVALID_STD_DEVICE Definitions for seGetId enum ID_UNKNOWN ID_SED1355 ID_SED1355F0A define MAX_DEVICE 10 SE_RESERVED is for reserved device define SE_RESERVED 0 DetectEndian is used to determine whether the most significant and least significant bytes are reversed by the given compiler define ENDIAN 0x1234 define REV_ENDIAN 0x3412 Definitions for Internal calculatio...

Page 256: ...m HAL_STDOUT HAL_STDIN HAL_DEVICE_ERR define FONT_NORMAL 0x00 define FONT_DOUBLE_WIDTH 0x01 define FONT_DOUBLE_HEIGHT 0x02 enum RED GREEN BLUE Definitions for seSplitScreen enum SCREEN1 1 SCREEN2 Definitions for sePowerSaveMode define PWR_CBR_REFRESH 0x00 define PWR_SELF_REFRESH 0x01 define PWR_NO_REFRESH 0x02 enum DISP_MODE_LCD 0 DISP_MODE_CRT DISP_MODE_SIMULTANEOUS ...

Page 257: ...ss of display buffer memory WORD wPanelFrameRate Desired panel frame rate WORD wCrtFrameRate Desired CRT rate WORD wMemSpeed Memory speed in ns WORD wTrc Ras to Cas Delay in ns WORD wTrp Ras Precharge time in ns WORD wTrac Ras Access Charge time in ns WORD wHostBusWidth Host CPU bus width in bits HAL_STRUCT typedef HAL_STRUCT PHAL_STRUCT ifdef INTEL typedef HAL_STRUCT far LPHAL_STRUCT else typedef...

Page 258: ...BOOL val int seSelectBusWidth int seReserved1 int width int seDelay int seReserved1 DWORD Seconds int seGetLastUsableByte int seReserved1 DWORD LastByte int seDisplayEnable int seReserved1 BYTE NewState int seSplitInit int seReserved1 DWORD wScrn1Addr DWORD wScrn2Addr int seSplitScreen int nReserved1 int WhichScreen long VisibleScanlines int seVirtInit int seReserved1 DWORD xVirt DWORD yVirt int s...

Page 259: ...erved1 long x long y DWORD color int seDrawCursorLine int seReserved1 long x1 long y1 long x2 long y2 DWORD color int seDrawCursorRect int seReserved1 long x1 long y1 long x2 long y2 DWORD color BOOL SolidFill int seDrawCursorEllipse int seReserved1 long xc long yc long xr long yr DWORD color BOOL SolidFill int seDrawCursorCircle int seReserved1 long xCenter long yCenter long radius DWORD color BO...

Page 260: ...t seSetLutEntry int seReserved1 int index BYTE pEntry int seGetLutEntry int seReserved1 int index BYTE pEntry C Like Support int seDrawText int seReserved1 char fmt int sePutChar int seReserved1 int ch int seGetChar void XLIB Support int seGetLinearDispAddr int seReserved1 DWORD pDispLogicalAddr int InitLinear int seReserved1 endif _HAL_H_ ...

Page 261: ...ight bits 9 8 REG 0Ah 0011 1110 0011 1110 0011 1110 0011 1110 set vertical non display period REG 0Dh 0000 1101 0000 1101 0000 1101 0000 1101 set 8 bpp and LCD enable REG 19h 0000 0011 0000 0011 0000 0011 0000 0011 set MCLK and PCLK divide REG 1Bh 0000 0001 0000 0001 0000 0001 0000 0001 disable half frame buffer REG 24h 0000 0000 0000 0000 0000 0000 0000 0000 set Look Up Table address to 0 REG 26h...

Page 262: ... REG 19h 0000 0010 0000 0010 0000 0010 0000 0010 set MCLK and PCLK divide REG 1Bh 0000 0000 0000 0000 0000 0000 0000 0000 enable half frame buffer REG 24h 0000 0000 0000 0000 0000 0000 0000 0000 set Look Up Table address to 0 REG 26h load LUT load LUT load LUT load LUT load Look Up Table Table 12 4 TFT Single Panel 640x480 with 25 175 MHz Pixel Clock Register Color 16 Bit 640X480 60Hz Notes REG 02...

Page 263: ...STER 2 RW n a n a n a n a Screen 2 Start Address Bit 19 Bit 18 Bit 17 Bit 16 REG 16h MEMORY ADDRESS OFFSET REGISTER 0 RW Memory Address Offset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 17h MEMORY ADDRESS OFFSET REGISTER 1 RW n a n a n a n a n a Memory Address Offset Bit 10 Bit 9 Bit 8 REG 18h PIXEL PANNING REGISTER RW Screen 2 Pixel Panning Screen 1 Pixel Panning Bit 3 Bit 2 Bit 1 Bit 0 ...

Page 264: ...LCD Panel Data Width Size TFT Panel Data Width Size 00 4 bit 9 bit 01 8 bit 12 bit 10 16 bit 16 bit 11 Reserved Reserved Simultaneous Display Option Select Bits 1 0 Simultaneous Display Mode 00 Normal 01 Line Doubling 10 Interlace 11 Even Scan Only Bit Per Pixel Select Bits 2 0 Color Depth Bit Per Pixel 000 1 bpp 001 2 bpp 010 4 bpp 011 8 bpp 100 15 bpp 101 16 bpp 110 111 Reserved PCLK Divide Sele...

Page 265: ...valuating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows ...

Page 266: ...Page 2 Epson Research and Development Vancouver Design Center S1D13505 13505CFG Configuration Program X23A B 001 04 Issue Date 01 03 29 THIS PAGE LEFT BLANK ...

Page 267: ... 13505CFG 5 S1D13505 Supported Evaluation Platforms 5 Installation 6 Usage 6 13505CFG Configuration Tabs 7 General Tab 7 Preferences Tab 9 Memory Tab 10 Clocks Tab 12 Panel Tab 15 CRT TV Tab 19 Registers Tab 20 13505CFG Menus 21 Open 21 Save 22 Save As 22 Configure Multiple 23 Export 24 Enable Tooltips 25 ERD on the Web 25 About 13505CFG 25 Comments 25 ...

Page 268: ...Page 4 Epson Research and Development Vancouver Design Center S1D13505 13505CFG Configuration Program X23A B 001 04 Issue Date 01 03 29 THIS PAGE LEFT BLANK ...

Page 269: ...ration information can be saved in a variety of text file formats for use in other applications S1D13505 Supported Evaluation Platforms 13505CFG runs on PC systems running Windows 9x ME NT 2000 and can modify the executable files based on the S1D13505 HAL for the following evaluation platforms PC system with an Intel 80x86 processor M68EC000IDP Integrated Development Platform board revision 3 0 wi...

Page 270: ...llation To start 13505CFG from a Windows command prompt change to the directory 13505cfg exe was installed to and type the command 13505cfg The basic procedure for using 13505CFG is 1 Start 13505CFG as described above 2 Open an existing file to serve as a starting reference point this step is optional 3 Modify the configuration For specific information on editing the configuration see 13505CFG Con...

Page 271: ...luation board specific information The values presented are used for configuring HAL based executable utilities The settings on this tab specify where in CPU address space the registers and display buffer are located Decode Addresses Selecting one of the listed evaluation platforms changes the values for the Register address and Display buffer address fields The values used for each evalu ation pl...

Page 272: ...e start of register decode space in hexadecimal This field is automatically set according to the Decode Address unless the User Defined decode address is selected Display Buffer Address The physical address of the start of display buffer decode space in hexadecimal This field is automatically set according to the Decode Address unless the User Defined decode address is selected ...

Page 273: ...T tab may cause selections on this tab to be grayed out The selections None and Panel are always available Panel SwivelView The S1D13505 SwivelView feature is capable of rotating the image displayed on an LCD panel 90 in a clockwise direction This sets the initial orientation of the panel This setting is greyed out when any display device other than Panel is selected as the Initial Display Panel C...

Page 274: ...tion on how to determine the op timal memory clock Memory Configuration These four settings must be configured based on the specification of the DRAM being used For each of the following settings refer to the DRAM manufacturer s specification unless otherwise noted Access Time Selects the access time of the DRAM The S1D13505 evaluation boards use 50ns DRAM Memory Type Selects the memory type eithe...

Page 275: ...05 Hardware Functional Specifi cation document number X23A A 001 xx and the DRAM manufacturer s specification Suspend Mode Refresh Selects the DRAM refresh method used during power save mode The S5U13505 evaluation boards use DRAM requiring Self Refresh For all other implementations refer to the manufacturer s specification for DRAM refresh requirements CAS before RAS Select this setting for DRAM ...

Page 276: ...settings In this mode the required frequencies for the input clocks are displayed in blue in the Auto section of each group It is the responsibility of the system designer to ensure that the correct CLKI frequencies are supplied to the S1D13505 Making a selection other than Auto indicates that the value for CLKI is known and is fixed by the system design Options for LCD and CRT frame rates are lim...

Page 277: ...requency must be fixed to a particular rate set this value by selecting a preset frequency from the drop down list or entering the desired frequency in MHz BUSCLK This setting determines the frequency of the bus interface clock BUSCLK The BUSCLK frequency must be specified Set this value by selecting a preset frequency from the drop down list or entering the desired frequency in MHz LCD PCLK These...

Page 278: ...nfigu ration program to calculate the best clock divisor Unless a very specific clocking is required it is best to leave this setting on Auto Timing This field shows the actual CRT PCLK frequency used by the configuration process calculations MCLK These settings select the signal source and input clock divisor for the memory clock MCLK Source The MCLK source is CLKI Divide Specifies the divide rat...

Page 279: ...ve TFT panel types Several options may change or become unavailable when the STN TFT setting is switched Therefore confirm all settings on this tab after the Panel Type is changed EL Support Enable Electro Luminescent panel support This option is only available when the selected panel type is STN Panel Type EL Support Panel Dimensions HRTC FPLINE VRTC FPFRAME Panel Data Width FPLINE FPFRAME Frame ...

Page 280: ...Panel Buffer is used with dual STN panels to improve image quality by buffering display data in a format directly usable by the panel This option is primarily intended for testing purposes It is not recommended that the Dual Panel Buffer be disabled as a reduction of display quality results Mono Color Selects between a monochrome or color panel Format 2 Selects color STN panel format 2 This option...

Page 281: ... without adjustment However manual adjustment may be required to fine tune the non display width and the non display height As a general rule passive LCD panels and some CRTs are tolerant of a wide range of non display times Active panels and some CRTs are far less tolerant of changes to the non display period Frame Rate Select the desired frame rate in Hz from the drop down list The values in the...

Page 282: ...E lines These settings allow fine tuning the TFT frame pulse parameters and are only available when the selected panel type is TFT Refer to S1D13505 Hardware Functional Specification document number X23A A 001 xx for a complete description of the FPFRAME pulse settings Start pos Specify the delay in lines from the start of the vertical non display period to the leading edge of the FPFRAME pulse Pu...

Page 283: ...the Clocks tab must be changed Simultaneous Display Options When both the LCD and CRT are operating in simulta neous display mode a method of displaying both images must be selected based on the vertical resolution height of the images If both displays are the same resolution select Normal Otherwise refer to the S1D13505 Hardware Functional Specification document number X23A A 001 xx for informati...

Page 284: ...e listing Manual changes to the registers are not checked for errors so caution is warranted when directly editing these values It is strongly recommended that the S1D13505 Hardware Functional Specification document number X23A A 001 xx be referred to before making an manual register settings Manually entered values may be changed by 13505CFG if further configuration changes are made on the other ...

Page 285: ... to quickly arrive at a starting point for register configuration The only requirement is that the file being opened must contain a valid S1D13505 HAL library information block 13505CFG supports a variety of executable file formats Select the file type s 13505CFG should display in the Files of Type drop down list and then select the filename from the list and click on the Open button Note 13505CFG...

Page 286: ...13505cfg exe and config uring the copy It is not possible to configure the original while it is running Save As From the Menu Bar select File then Save As to display the Save As Dialog Box Save as is very similar to Save except a dialog box is displayed allowing the user to name the file before saving Using this technique a tester can configure a number of files differing only in configuration inf...

Page 287: ...from Windows Explorer Selecting Show all files displays all files in the selected directory whereas selecting Show conf files only will display only files that can be configured using 13505CFG The configuration values can be saved to a specific EXE file for Intel platforms or to a specific S9 or ELF file for non Intel platforms The file must have been compiled using the 13505 HAL library Checking ...

Page 288: ...splay drivers for other operating systems such as Linux QNX and VxWorks UGL or WindML a comma delimited text file containing an offset a value and a description for each S1D13505 register After selecting the file format click the Export As button to display the file dialog box which allows the user to enter a filename before saving Before saving the configuration file clicking the Preview button s...

Page 289: ...ption from the Help menu displays the about dialog box for 13505CFG The about dialog box contains version information and the copyright notice for 13505CFG Comments On any tab particular options may be grayed out if selecting them would violate the operational specification of the S1D13505 i e Selecting extremely low CLKI frequen cies on the Clocks tab may result in no possible CRT options Selecti...

Page 290: ...Page 26 Epson Research and Development Vancouver Design Center S1D13505 13505CFG Configuration Program X23A B 001 04 Issue Date 01 03 29 THIS PAGE LEFT BLANK ...

Page 291: ...ment but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson...

Page 292: ...Page 2 Epson Research and Development Vancouver Design Center S1D13505 13505SHOW Demonstration Program X23A B 002 05 Issue Date 01 02 02 THIS PAGE LEFT BLANK ...

Page 293: ...s assumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications where the PC uses a terminal program to send control commands and information to the target processor Alternatively the PC can program an EPROM which is then placed in the target platform Some target platforms can also communicate with the PC via a parall...

Page 294: ...e Pressing the ESC key will exit the program 13505SHOW Examples The 13505SHOW demonstration program is designed to both demonstrate and test some of the features of the S1D13505 Some examples follow showing how to use the program in both instances Using 13505SHOW For Demonstration 1 To show color patterns which must be manually stepped through all bit per pixel modes type the following 13505SHOW T...

Page 295: ...y press ESC The s switch can be used in combination with other command line switches Using 13505SHOW For Testing 1 To show a test grid over the color pattern type the following 13505SHOW b 8 g The program will display the 8 bit per pixel color pattern overlaid with a one pixel wide white grid and then exit The grid makes it obvious if the image is shifted or if pixels are missing Note the grid is ...

Page 296: ...PC with the S5U13505 evaluation board the PC must not have more than 12M bytes of system memory 13505SHOW uses the panel color setup to determine whether to display a mono or color image on both the panel and the CRT When editing in 13505CFG with CRT enabled and panel disabled select Color from the Panel dialog box if you want the CRT to show color For simultaneous display select both lcd and crt ...

Page 297: ...ad the revision code register on the S1D13505 Ensure that the S1D13505 hardware is installed and that the hardware platform has been set up correctly ERROR Continual screen read will not work with the a switch The continual screen read function reads one screen indefinitely so it is not possible to automatically cycle through the video modes WARNING b option used with noinit so bit per pixel and d...

Page 298: ...Page 8 Epson Research and Development Vancouver Design Center S1D13505 13505SHOW Demonstration Program X23A B 002 05 Issue Date 01 02 02 THIS PAGE LEFT BLANK ...

Page 299: ...t but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Co...

Page 300: ...Page 2 Epson Research and Development Vancouver Design Center S1D13505 13505SPLT Display Utility X23A B 003 03 Issue Date 01 02 02 THIS PAGE LEFT BLANK ...

Page 301: ...5 utilities This software is designed to work in both embedded and personal computer PC environments For the embedded environment it is assumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications The PC uses a terminal program to send control commands and information to the target processor Alternatively the PC can ...

Page 302: ...oves Screen 2 up one line moves Screen 2 down one line CTRL moves Screen 2 up several lines CTRL moves Screen 2 down several lines HOME Screen 2 moved up as high as possible END Screen 2 moved down as low as possible Automatic and Manual modes b changes the color depth bit per pixel ESC exits 13505SPLT 13505SPLT Example 1 Type 13505splt a to automatically move the split screen 2 Press b to change ...

Page 303: ...ectly ERROR Too many devices registered There are too many display devices attached to the HAL The HAL currently supports only one device ERROR Could not register S1D13505FOA device A S1D13505 device was not found at the configured addresses Check the configuration address using the 13505CFG configuration program ERROR Could not set bit per pixel display mode This message generally means that the ...

Page 304: ...Page 6 Epson Research and Development Vancouver Design Center S1D13505 13505SPLT Display Utility X23A B 003 03 Issue Date 01 02 02 THIS PAGE LEFT BLANK ...

Page 305: ...t but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Co...

Page 306: ...Page 2 Epson Research and Development Vancouver Design Center S1D13505 13505VIRT Display Utility X23A B 004 04 Issue Date 01 02 02 THIS PAGE LEFT BLANK ...

Page 307: ...sumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications where the PC uses a terminal program to send control commands and information to the target processor Alternatively the PC can program an EPROM which is then placed in the target platform Some target platforms can also communicate with the PC via a parallel p...

Page 308: ...the maximum height is based on the display memory a panning and scrolling is performed automatically displays the help screen The following keyboard commands are for navigation within the program Manual mode scrolls up scrolls down pans to the left pans to the right CTRL scrolls up several lines CTRL scrolls down several lines CTRL pans to the left several lines CTRL pans to the right several line...

Page 309: ...re than 12M bytes of system memory Program Messages ERROR Did not find a 13505 device The HAL was unable to read the revision code register on the S1D13505 Ensure that the S1D13505 hardware is installed and that the hardware platform has been set up correctly ERROR Too many devices registered There are too many display devices attached to the HAL The HAL currently supports only one device ERROR Co...

Page 310: ...Page 6 Epson Research and Development Vancouver Design Center S1D13505 13505VIRT Display Utility X23A B 004 04 Issue Date 01 02 02 THIS PAGE LEFT BLANK ...

Page 311: ...nt but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson C...

Page 312: ...Page 2 Epson Research and Development Vancouver Design Center S1D13550 13505PLAY Diagnostic Utility X23A B 005 04 Issue Date 01 02 02 THIS PAGE LEFT BLANK ...

Page 313: ...information on configuring S1D13505 utilities This software is designed to work in both embedded and personal computer PC environments For the embedded environment it is assumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications where the PC uses a terminal program to send control commands and information to the ta...

Page 314: ...he data specified Data can be multiple values e g F 0 20 1 2 3 4 fills 0 to 0x20 with a repeating pattern of 1 2 3 4 h lines Halts after lines of display This feature halts the display during long read operations to prevent data from scrolling off the display Similar to the DOS MORE command Set to 0 to disable this feature i LCD CRT Initializes the chip with the specified configuration The configu...

Page 315: ... 1 2 3 4 writes the byte values 1 2 3 4 starting at address 0 x w index data Reads writes bytes or words w to from the registers Writes data to REG index when data is specified Reads data from REG index when data is not specified Some platforms may provide upredictable results when non aligned word addresses are entered xa Reads all registers Displays Help information 13505PLAY Example 1 Type 1350...

Page 316: ... causes the file dumpregs scr to be interpreted as commands by 13505PLAY and the results to be sent to the file results Example Create an ASCII text file that contains the commands i xa and q This file initializes the S1D13505 and reads the registers Note after a semicolon all characters on a line are ignored Note all script files must end with the q command i xa q Comments All numeric values are ...

Page 317: ... hardware software setup violates the timing limitations described in the S1D13505 Hardware Functional Specification document number X23A A 001 xx ERROR Too many devices registered There are too many display devices attached to the HAL The HAL currently supports only one device ERROR Could not register S1D13505F00A device A S1D13505 device was not found at the configured addresses Check the config...

Page 318: ...Page 8 Epson Research and Development Vancouver Design Center S1D13550 13505PLAY Diagnostic Utility X23A B 005 04 Issue Date 01 02 02 THIS PAGE LEFT BLANK ...

Page 319: ...ent but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson ...

Page 320: ...Page 0 Epson Research and Development Vancouver Design Center S1D13505 13505BMP Demonstration Program X23A B 006 04 Issue Date 01 02 02 THIS PAGE LEFT BLANK ...

Page 321: ...o configure 13505BMP Consult the 13505CFG users guide document number X23A B 001 xx for more information on configuring S1D13505 utilities S1D13505 Supported Evaluation Platforms 13505BMP supports the following S1D13505 evaluation platforms PC system with an Intel 80x86 processor Note The 13505BMP source code may be modified by the OEM to support other evaluation platforms Installation Copy the fi...

Page 322: ...505BMP requires the BMP images for the Hardware Cursor and the Ink Layer to be stored in specific formats The Hardware Cursor BMP image must have a color depth of four bit per pixel and be 64x64 pixels in resolution The Ink Layer BMP image must have a color depth of four bit per pixel and be the same resolution as the displayed image Both images are stored at a color depth of four bit per pixel al...

Page 323: ...05BMP lcd bmpfile bmp 13505BMP t cursor noinit arrow bmp To control the cursor with the mouse include the mouse option when loading the cursor image Comments 13505BMP displays only Windows BMP format images The PC must not have more than 12M bytes of memory when used with the S5U13505 evalua tion board A 24 bit true color bitmap will be displayed at a color depth of 16 bit per pixel Only the green...

Page 324: ...mplete image Either increase the amount of display memory or select an image with a lower bit per pixel value ERROR Cannot use p option with hardware cursor and ink layer Instead rotate BMP file manually and load without p option Because the Hardware Cursor and Ink Layer are not automatically rotated in portrait mode 13505BMP does not support the p option Instead rotate the BMP with a paint progra...

Page 325: ...nk Layer ERROR BMP file is bit per pixel ink layer requires 4 bit per pixel BMP file The Ink Layer BMP image must always have a color depth of four bit per pixel ERROR Could not change to bit per pixel The HAL library detected that the requested color depth bit per pixel will violate the S1D13505 hardware specification for clocks To reprogram the clocks run 13505CFG and select the desired color de...

Page 326: ...Page 6 Epson Research and Development Vancouver Design Center S1D13505 13505BMP Demonstration Program X23A B 006 04 Issue Date 01 02 02 THIS PAGE LEFT BLANK ...

Page 327: ...this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Se...

Page 328: ...Page 2 Epson Research and Development Vancouver Design Center S1D13505 13505PWR Software Suspend Power Sequencing Utility X23A B 007 03 Issue Date 01 02 02 THIS PAGE LEFT BLANK ...

Page 329: ...uide document number X23A B 001 xx for more information on configuring S1D13505 utilities This software is designed to work in both embedded and personal computer PC environments For the embedded environment it is assumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications where the PC uses a terminal program to sen...

Page 330: ...e deactivates software suspend hardware suspend or the LCD i initializes registers 0 GPIO1 triggers on falling edge 1 0 1 GPIO1 triggers on rising edge 0 1 displays this usage message Note 13505PWR will automatically finish execution and return to the prompt 13505PWR Examples To enable software suspend mode type the following 13505PWR software enable To disable software suspend mode type the follo...

Page 331: ...nsure that the S1D13505 hardware is installed and that the hardware platform has been set up correctly ERROR Unknown command line argument An invalid command line argument was entered Enter a valid command line argument ERROR Already selected SOFTWARE Command line argument software was selected more than once Select software only once ERROR Already selected HARDWARE Command line argument hardware ...

Page 332: ... 03 Issue Date 01 02 02 ERROR Too many devices registered There are too many display devices attached to the HAL The HAL currently supports only one device ERROR Could not register S1D13505F00A device A S1D13505 device was not found at the configured addresses Check the configuration address using the 13505CFG configuration program ...

Page 333: ...luating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows ar...

Page 334: ...Page 2 Epson Research and Development Vancouver Design Center S1D13505 Windows CE 2 x Display Drivers X23A E 001 06 Issue Date 01 05 25 THIS PAGE LEFT BLANK ...

Page 335: ...ystem The driver is capable of 4 8 and 16 bit per pixel landscape modes no rotation and 8 and 16 bit per pixel SwivelView 90 degree mode This document and the source code for the Windows CE drivers are updated as appropriate Before beginning any development please check the Epson Electronics America Website at www eea epson com or the Epson Research and Development Website at www erd epson com for...

Page 336: ...oject by following the procedure documented in Creating a New Project Directory from the Windows CE ETK V2 0 Alternately use the current DEMO7 project included with the ETK v2 0 Follow the steps below to create a X86 DEMO7 shortcut on the Windows NT v4 0 desktop which uses the current DEMO7 project a Right click on the Start menu on the taskbar b Click on the item Open All Users and the Start Menu...

Page 337: ...5 contains the register values required to set the screen resolution color depth bpp display type active display LCD CRT TV display rotation etc Before building the display driver refer to the descriptions in the file MODE0 H for the default settings of the driver If the default does not match the configuration you are building for then MODE0 H will have to be regenerated with the correct informa ...

Page 338: ...le project icon i e X86 DEMO7 13 Type BLDDEMO ENTER at the command prompt of the X86 DEMO7 window to generate a Windows CE image file NK BIN Build for CEPC X86 on Windows CE Platform Builder 2 1x using a Command Line Interface Throughout this section 2 1x refers to either 2 11 or 2 12 as appropriate 1 Install Microsoft Windows NT v4 0 or 2000 2 Install Microsoft Visual C C version 5 0 or 6 0 3 Ins...

Page 339: ...xcopy s e x wince public maxall wince public epson c Rename x wince public epson maxall bat to epson bat d Edit EPSON BAT to add the following lines to the end of the file echo on set CEPC_DDI_S1D13505 1 echo off 6 Make an S1D13505 directory under x wince platform cepc drivers display and copy the S1D13505 driver source code into x wince platform cepc drivers dis play S1D13505 7 Edit the file x wi...

Page 340: ...User Manual document number X23A B 001 xx available at www erd epson com After selecting the desired configuration export the file as a C Header File for S1D13505 WinCE Drivers Save the new configuration as MODE0 H in x wince platform cepc drivers display S1D13505 replacing the original configura tion file 10 Edit the file PLATFORM REG to match the screen resolution color depth bpp ac tive display...

Page 341: ...ay Drivers S1D13505 Issue Date 01 05 25 X23A E 001 06 12 Generate the proper building environment by double clicking on the Epson project icon Build Epson for x86 13 Type BLDDEMO ENTER at the command prompt of the Build Epson for x86 window to generate a Windows CE image file NK BIN ...

Page 342: ...ice a himem sys c Edit AUTOEXEC BAT on the floppy disk to contain the following lines mode com1 9600 n 8 1 loadcepc B 9600 C 1 c nk bin d Copy LOADCEPC EXE and HIMEM SYS to the bootable floppy disk Search for the loadCEPC utility in your Windows CE directories e Copy NK BIN to c f Boot the system from the bootable floppy disk 2 To start CEPC after booting from a hard drive a Copy LOADCEPC EXE to C...

Page 343: ...isplay driver The switches are added or removed from the compile options in the file SOURCES WINCEVER This option is automatically set to the numerical version of WinCE for version 2 12 or later If the environment variable _WINCEOSVER is not defined then WINCEVER will default 2 11 The display driver may test against this option to support different WinCE version specific features EpsonMessages Thi...

Page 344: ...ou do not add any registry values the display driver will default to the first mode table in your list To select which display mode the display driver should use upon boot add the following lines to your PLATFORM REG file HKEY_LOCAL_MACHINE Drivers Display S1D13505 Width dword 280 Height dword 1E0 Bpp dword 8 Rotation dword 0 RefreshRate dword 3C Flags dword 2 Note that all dword values are in hex...

Page 345: ...al Windows CE Platform Builder supported platforms When using 13505CFG EXE to produce multiple MODE tables make sure you change the Mode Number in the WinCE tab for each mode table you generate The display driver supports multiple mode tables but only if each mode table has a unique mode number At this time the drivers have been tested on the x86 CPUs and have been run with version 2 0 of the ETK ...

Page 346: ...Page 14 Epson Research and Development Vancouver Design Center S1D13505 Windows CE 2 x Display Drivers X23A E 001 06 Issue Date 01 05 25 THIS PAGE LEFT BLANK ...

Page 347: ...ocument but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Ep...

Page 348: ...Page 2 Epson Research and Development Vancouver Design Center S1D13505 Wind River WindML v2 0 Display Drivers X23A E 002 03 Issue Date 01 04 06 THIS PAGE LEFT BLANK ...

Page 349: ...is generated by the configuration utility 13505CFG This design allows for easy customization of display type clocks decode addresses rotation etc by OEMs For further information on 13505CFG see the 13505CFG Configuration Program User Manual document number X23A B 001 xx Note The WindML display drivers are provided as reference source code only They are in tended to provide a basis for OEMs to deve...

Page 350: ...get config pcPentium config h with the file x 13505 8bpp File config h or x 13505 16bpp File config h The new config h file removes networking components and configures the build image for booting from a floppy disk Note Rather than simply replacing the original config h file rename it so the file can be kept for reference purposes 3 Build a boot ROM image From the Tornado tool bar select Build Bu...

Page 351: ...line comments follow these steps a In the Tornado Workspace Views window click on the Builds tab b Expand the 8bpp Builds or 16bpp Builds view by clicking on the next to it The expanded view will contain the item default Right click on default and select Properties A Properties window will appear c Select the C C compiler tab to display the command switches used in the build Remove the ansi switch...

Page 352: ...Page 6 Epson Research and Development Vancouver Design Center S1D13505 Wind River WindML v2 0 Display Drivers X23A E 002 03 Issue Date 01 04 06 THIS PAGE LEFT BLANK ...

Page 353: ...valuating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows ...

Page 354: ...Page 2 Epson Research and Development Vancouver Design Center S1D13505 Wind River UGL v1 2 Display Drivers X23A E 003 02 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 355: ...ent driver for mass production The UGL display drivers are designed around a common configuration include file called mode0 h which is generated by the configuration utility 13505CFG This design allows for easy customization of display type clocks addresses rotation etc by OEMs For further information on 13505CFG see the 13505CFG Configuration Program User Manual document number X23A B 001 xx This...

Page 356: ... file x Tornado target config pcPentium config h with the file x 13505 8bpp File config h or x 13505 16bpp File config h The new config h file removes networking components and configures the build image for booting from a floppy disk Note Rather than simply replacing the original config h file rename it so the file can be kept for reference purposes 3 Build a boot ROM image From the Tornado tool ...

Page 357: ...Builds or 16bpp Builds view by clicking on the next to it The expanded view will contain the item default Right click on default and select Properties A properties win dow will appear c Select the C C compiler tab to display the command switches used in the build Remove the ansi switch from the line that con tains g mpentium ansi nostdinc DRW_MULTI_THREAD Refer to GNU ToolKit user s guide for deta...

Page 358: ...Page 6 Epson Research and Development Vancouver Design Center S1D13505 Wind River UGL v1 2 Display Drivers X23A E 003 02 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 359: ...luating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows ar...

Page 360: ...Page 2 Epson Research and Development Vancouver Design Center S1D13505 Windows CE 3 x Display Drivers X23A E 006 01 Issue Date 01 05 17 THIS PAGE LEFT BLANK ...

Page 361: ...sion 3 0 The driver is capable of 4 8 and 16 bit per pixel landscape modes no rotation and 8 and 16 bit per pixel SwivelView 90 degree mode This document and the source code for the Windows CE drivers are updated as appropriate Before beginning any development please check the Epson Electronics America Website at www eea epson com or the Epson Research and Development Website at www erd epson com ...

Page 362: ...ng on the Microsoft Windows CE Platform Builder icon 4 Create a new project a Select File New b In the dialog box select the Platforms tab c In the platforms dialog box select WCE Platform set a location for the project such as x myproject set the platform name such as myplatform and set the Processors to Win32 WCE x86 d Click the OK button e In the dialog box WCE Platform Step 1 of 2 select CEPC ...

Page 363: ...he Workspace window select the ComponentView tab b Show the tree for MYPLATFORM components by clicking on the sign at the root of the tree c Right click on the ddi_flat component d Select Delete e From the File menu select Save Workspace 10 From the Workspace window click on ParameterView Tab Show the tree for MY PLATFORM Parameters by clicking on the sign at the root of the tree Expand the the WI...

Page 364: ...rogram User Manual document number X23A B 001 xx available at www erd epson com After selecting the desired configuration export the file as a C Header File for S1D13505 WinCE Drivers Save the new configuration as MODE0 H in the wince300 platform cepc drivers display replacing the original configuration file 12 From the Platform window click on ParameterView Tab Show the tree for MY PLATFORM Param...

Page 365: ...n oak misc call wince x86 i486 CE MINSHELL CEPC set IMGNODEBUGGER 1 set WINCEREL 1 set CEPC_DDI_S1D13X0X 1 4 Generate the build environment by calling cepath bat 5 Create a new folder called S1D13505 under x wince300 platform cepc drivers dis play and copy the S1D13505 driver source code into x wince300 platform cepc driv ers display S1D13505 6 Edit the file x wince300 platform cepc drivers displa...

Page 366: ...information on how to use 13505CFG refer to the 13505CFG Configuration Program User Manual document number X23A B 001 xx available at www erd epson com After selecting the desired configuration export the file as a C Header File for S1D13505 WinCE Drivers Save the new configuration as MODE0 H in the wince300 platform cepc drivers display replacing the original configuration file 9 Edit the file PL...

Page 367: ...vers S1D13505 Issue Date 01 05 17 X23A E 006 01 10 Delete all the files in the x wince300 release directory and delete the file x wince300 platform cepc bif 11 Type BLDDEMO ENTER at the command prompt to generate a Windows CE image file The file generated will be x wince300 release nk bin ...

Page 368: ...ice a himem sys c Edit AUTOEXEC BAT on the floppy disk to contain the following lines mode com1 9600 n 8 1 loadcepc B 9600 C 1 c nk bin d Copy LOADCEPC EXE and HIMEM SYS to the bootable floppy disk Search for the loadCEPC utility in your Windows CE directories e Copy NK BIN to c f Boot the system from the bootable floppy disk 2 To start CEPC after booting from a hard drive a Copy LOADCEPC EXE to C...

Page 369: ...n specific features EnablePreferVmem This option enables the use of off screen video memory When this option is enabled WinCE can optimize some BLT operations by using off screen video memory to store images You may need to disable this option for systems with 512K bytes of video memory and VGA 640x480 panels ENABLE_ANTIALIASED_FONTS This option enables the display driver support of antialiased fo...

Page 370: ...register information to control the desired display mode The MODE tables must be generated by the configuration program 13505CFG EXE The display driver comes with example MODE tables By default only MODE0 H is used by the display driver New mode tables can be created using the 13505CFG program Edit the include section of MODE H to add the new mode table If you only support a single display mode yo...

Page 371: ...erformance and power off capabilities The section Simple Display Driver Configuration on page 15 provides a configuration which should work with most Windows CE platforms This section is only intended as a means of getting started Once the developer has a functional system it is recommended to optimize the display driver configuration as described below in Description of Windows CE Display Driver ...

Page 372: ... mode cannot be used if power to the display memory is turned off b PORepaint 1 This is the default mode for Windows CE This mode tells Windows CE to save the main display data to the system memory on suspend This mode is used if display memory power is going to be turned off when the system is suspended and there is enough system memory to save the image Any off screen data in display memory is L...

Page 373: ...ay Driver Configuration The following display driver configuration should work with most platforms running Windows CE This configuration disables the use of off screen display memory and forces the system to redraw the main display upon power on 1 This step disables the use of off screen display memory Edit the file x wince300 platform cepc drivers display S1D13505 sources and change the line CDEF...

Page 374: ... several Windows CE Platform Builder supported platforms If you are running 13505CFG EXE to produce multiple MODE tables make sure you change the Mode Number in the WinCE tab for each mode table you generate The display driver supports multiple mode tables but only if each mode table has a unique mode number At this time the drivers have been tested on the x86 CPUs and have been built with Plat fo...

Page 375: ...se this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of...

Page 376: ...Page 2 Epson Research and Development Vancouver Design Center S1D13505 S5U13505B00C Rev 1 0 ISA Bus Evaluation Board User Manual X23A G 004 05 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 377: ...nterface Pin Mapping 12 6 Technical Description 13 6 1 ISA Bus Support 13 6 2 Non ISA Bus Support 13 6 3 DRAM Support 14 6 4 Decode Logic 14 6 5 Clock Input Support 14 6 6 Monochrome LCD Panel Support 14 6 7 Color Passive LCD Panel Support 14 6 8 Color TFT D TFD LCD Panel Support 15 6 9 CRT Support 15 6 10 Power Save Modes 15 6 11 Adjustable LCD Panel Negative Power Supply 15 6 12 Adjustable LCD P...

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Page 379: ...le 2 2 Host Bus Selection 8 Table 2 3 Jumper Settings 8 Table 3 1 LCD Signal Connector J6 9 Table 4 1 CPU BUS Connector H1 Pinout 10 Table 4 2 CPU BUS Connector H2 Pinout 11 Table 5 1 CPU Interface Pin Mapping 12 List of Figures Figure 1 S1D13505B00C Schematic Diagram 1 of 4 19 Figure 2 S1D13505B00C Schematic Diagram 2 of 4 20 Figure 3 S1D13505B00C Schematic Diagram 3 of 4 21 Figure 4 S1D13505B00C...

Page 380: ...Page 6 Epson Research and Development Vancouver Design Center S1D13505 S5U13505B00C Rev 1 0 ISA Bus Evaluation Board User Manual X23A G 004 05 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 381: ...bus support For more information regarding the S1D13505 refer to the S1D13505 Hardware Functional Speci fication document number X23A A 001 xx 1 1 Features 128 pin QFP15 surface mount package SMT technology for all appropriate devices 4 8 bit monochrome passive LCD panel support 4 8 16 bit color passive LCD panel support 9 12 18 bit LCD TFT D TFD panel support Embedded RAMDAC for CRT support 16 bi...

Page 382: ... DIP Switch Settings Switch Signal Closed 1 Open 0 SW1 1 MD1 See Host Bus Selection table below See Host Bus Selection table below SW1 2 MD2 SW1 3 MD3 SW1 4 MD4 Little Endian Big Endian SW1 5 MD5 Wait signal is active high Wait signal is active low SW1 6 MD13 Reserved SW1 7 MD14 SW1 8 MD15 Table 2 2 Host Bus Selection MD3 SW1 3 MD2 SW1 2 MD1 SW1 1 Host Bus Interface open 0 open 0 open 0 SH 3 SH 4 ...

Page 383: ...D2 LD2 LD2 FPDAT3 7 G2 G3 G5 LD3 LD3 LD3 FPDAT4 9 G1 G2 G4 UD0 UD0 UD0 UD0 UD0 FPDAT5 11 G0 G1 G3 UD1 UD1 UD1 UD1 UD1 FPDAT6 13 B2 B3 B5 UD2 UD2 UD2 UD2 UD2 FPDAT7 15 B1 B2 B4 UD3 UD3 UD3 UD3 UD3 FPDAT8 17 B0 B1 B3 LD4 FPDAT9 19 R0 R2 LD5 FPDAT10 21 R1 LD6 FPDAT11 23 G0 G2 LD7 FPDAT12 25 G1 UD4 FPDAT13 27 G0 UD5 FPDAT14 29 B0 B2 UD6 FPDAT15 31 B1 UD7 FPSHIFT 33 FPSHIFT DRDY 35 FPSHIFT2 FPLINE 37 F...

Page 384: ...nnected to DB6 of the S1D13505 10 Connected to DB7 of the S1D13505 11 Ground 12 Ground 13 Connected to DB8 of the S1D13505 14 Connected to DB9 of the S1D13505 15 Connected to DB10 of the S1D13505 16 Connected to DB11 of the S1D13505 17 Ground 18 Ground 19 Connected to DB12 of the S1D13505 20 Connected to DB13 of the S1D13505 21 Connected to DB14 of the S1D13505 22 Connected to DB15 of the S1D13505...

Page 385: ...round 11 Connected to AB8 of the S1D13505 12 Connected to AB9 of the S1D13505 13 Connected to AB10 of the S1D13505 14 Connected to AB11 of the S1D13505 15 Connected to AB12 of the S1D13505 16 Connected to AB13 of the S1D13505 17 Ground 18 Ground 19 Connected to AB14 of the S1D13505 20 Connected to AB14 of the S1D13505 21 Connected to AB16 of the S1D13505 22 Connected to AB17 of the S1D13505 23 Con...

Page 386: ... A 19 13 A 19 13 SA 19 13 A 12 18 A 19 13 AB 12 1 A 12 1 A 12 1 A 12 1 A 12 1 A 12 1 SA 12 1 A 19 30 A 12 1 AB0 A0 A0 LDS A0 A0 SA0 A31 A0 DB 15 0 D 15 0 D 15 0 D 15 0 D 31 16 D 15 0 SD 15 0 D 0 15 D 15 0 WE1 WE1 WE1 UDS DS WE1 SBHE BI CE2 M R External Decode CS External Decode BUSCLK CKIO CKIO CLK CLK BCLK CLK CLKOUT CLKI BS BS BS AS AS VDD VDD TS VDD RD WR RD WR RD WR R W R W RD1 VDD RD WR CE1 R...

Page 387: ...register addresses 4 The hardware suspend enable disable address is at location F00000h A read to this location will enable the hardware suspend a write to the same location will disable it Note Due to backwards compatibility with the S5U13505B00B Evaluation Board which supports both an 8 and a 16 bit CPU interface third party software must perform a write at address F80000h in order to enable a 1...

Page 388: ...must be isolated from the ISA bus do not plug the card into a computer Voltage lines are provided on the header strips For the ISA bus a 22V10 PAL U4 socketed is currently used to provide the S1D13505 CS pin 4 M R pin 5 and other decode logic signals This functionality must now be provided externally Remove the PAL from its socket to eliminate conflicts resulting from two different outputs driving...

Page 389: ...505 supports up to a 40 0Mhz input clock frequency A 40 0MHz oscillator U2 socketed is provided on the S5U13505 board as the clock CLKI source 6 6 Monochrome LCD Panel Support The S1D13505 supports 4 and 8 bit dual and single monochrome passive LCD panels All necessary signals are provided on the 40 pin ribbon cable header J6 The interface signals on the cable are alternated with grounds to reduce...

Page 390: ...ware suspend mode is controlled by the utility 13505PWR Software Suspend Power Sequencing The hardware suspend mode can be enabled by a memory read to location F00000h A memory write to the same location will disable it 6 11 Adjustable LCD Panel Negative Power Supply Most monochrome passive LCD panels require a negative power supply to provide between 18V and 23V Iout 45mA For ease of implementati...

Page 391: ...and Table 4 2 CPU BUS Connector H2 Pinout on page 11 for specific settings Note These headers only provide the CPU Bus interface signals from the S1D13505 When another host bus interface is selected through MD3 1 configuration appropriate external decode logic MUST be used to access the S1D13505 See the section Host Bus Interface Pin Mapping of the S1D13505 Hardware Functional Specification docume...

Page 392: ...9 3 D1 D2 D3 BAV99 Signal diode 10 2 H1 H2 HEADER 17X2 11 2 JP1 JP2 HEADER 3 12 1 J1 VGA connector 13 1 J2 AT CON A 14 1 J3 AT CON B 15 1 J4 AT CON C 16 1 J5 AT CON D 17 1 J6 CON40A 18 6 L1 L2 L3 L4 L5 L7 Ferrite bead Philips BDS3 3 8 9 4S2 19 1 L6 Inductor 1µH 20 2 Q1 Q3 MMBT2222A 21 1 Q2 MMBT2907A 22 10 R1 R2 R21 R26 R30 R31 R32 R33 R 34 R35 10K 0805 resistor 23 2 R3 R4 39 Ohms 0805 resistor 24 ...

Page 393: ...d User Manual S1D13505 Issue Date 01 02 05 X23A G 004 05 38 1 U3 MT4C1M16E5DJS 5 50ns self refresh EDO DRAM 39 1 U4 PAL22V10 15 40 1 U5 RD 0412 Xentek RD 0412 41 1 U6 EPN001 Xentek EPN001 42 3 U7 U8 U9 74AHC244 43 1 U10 LT1117CM 3 3 5V to 3 3V regulator 800mA Item Qty board Designation Part Value Description ...

Page 394: ... R3 39 R4 39 R6 150 1 R5 150 1 R7 150 1 U1 S1D13505F00A AB0 3 AB1 2 AB2 1 AB3 128 AB4 127 AB5 126 AB6 125 AB7 124 AB8 123 AB9 122 AB10 121 AB11 120 AB12 119 AB13 118 AB14 117 AB15 116 AB16 115 MA0 61 MA1 63 MA2 65 MA3 67 MA4 66 MA5 64 MA6 62 MA7 60 MD0 35 MD1 37 MD2 39 MD3 41 MD4 43 MD5 45 MD6 47 MD7 49 MD8 48 MD9 46 MD10 44 MD12 40 MD13 38 FPFRAME 73 FPLINE 74 FPSHIFT 77 FPDAT0 79 FPDAT1 80 FPDAT...

Page 395: ...1 A2 A3 A4 A5 A6 A7 A8R A8 A9R A9 A10 NC A11 NC RAS UCAS LCAS W NC NC NC OE DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 VCC VCC VCC VSS VSS VSS R20 15K R19 15K R15 15K R14 15K R13 15K R12 15K R11 15K U4 22V10 1 2 3 4 5 6 7 8 9 10 11 13 23 22 21 20 19 18 17 16 15 14 I1 CLK I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 R21 10K S1 SW DIP 8 1 2 3 4 5 6 7 ...

Page 396: ... SD0 9 IOCHRDY 10 AEN 11 SA19 12 SA18 13 SA17 14 SA16 15 SA15 16 SA14 17 SA13 18 SA12 19 SA11 20 SA10 21 SA9 22 SA8 23 SA7 24 SA6 25 SA5 26 SA4 27 SA3 28 SA2 29 SA1 30 SA0 31 J3 AT CON B GND 1 RESET 2 5V 3 IRQ9 4 5V 5 DRQ2 6 12V 7 OWS 8 12V 9 GND 10 SMEMW 11 SMEMR 12 IOW 13 IOR 14 DACK3 15 DRQ3 16 DACK1 17 DRQ1 18 REFRESH 19 CLK 20 IRQ7 21 IRQ6 22 IRQ5 23 IRQ4 24 IRQ3 25 DACK2 26 T C 27 BALE 28 5V...

Page 397: ... 12V 12V VCC VCC JP1 HEADER 3 1 2 3 J6 CON40A 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 H1 HEADER 17X2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 H2 HEADER 17X2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 U9 74AHC244 1A1 2 1Y1 18 1A...

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Page 399: ...son EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of...

Page 400: ...Page 2 Epson Research and Development Vancouver Design Center S5U13505 D9000 Evaluation Board User Manual X23A G 002 04 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 401: ...roller 8 2 1 1 Display Buffer 8 2 1 2 LCD Display Support 9 2 1 3 Touchscreen Support 11 2 1 4 CRT Support 11 2 1 5 Jumper Selection 11 2 1 6 Adjustable LCD BIAS Power Supply 11 3 D9000 Specifics 13 3 1 Interface Signals 13 3 1 1 Connector Pinout for Channel A6 and A7 13 3 1 2 Memory Address CS M R Decoding 17 3 2 FPGA Code Functionality 17 3 3 Board Dimensions 17 4 Parts List 18 5 Schematic Diagr...

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Page 403: ...10 Table 2 2 Touchscreen Header TS1 Pinout 11 Table 2 3 Touchscreen Header Pinout 11 Table 3 1 Connectors Pinout for Channel A7 13 Table 3 2 Connectors Pinout for Channel A6 15 List of Figures Figure 5 1 S5U13505 D9000 Schematic Diagram 1 of 3 19 Figure 5 2 S5U13505 D9000 Schematic Diagram 2 of 3 20 Figure 5 3 S5U13505 D9000 Schematic Diagram 3 of 3 21 Figure 6 1 Component Placement 22 ...

Page 404: ...Page 6 Epson Research and Development Vancouver Design Center S5U13505 D9000 Evaluation Board User Manual X23A G 002 04 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 405: ...crosoft Windows CE ODO Reference Platform uses expansion boards to interface peripherals to the FPGA processor combination This manual describes how the S5U13505 D9000 Evaluation Board is used to provide a color LCD CRT solution for the Windows CE environment Reference S1D13505 Hardware Functional Specification document number X23A A 001 xx D9000 Development System Hardware User Manual Hitachi ...

Page 406: ...voltage power supply SmallTypeZ x 2 form factor requires two side by side SmallTypeZ slots 2 1 S1D13505 Embedded RAMDAC LCD CRT Controller The S1D13505 is a low cost low power color monochrome LCD CRT controller with an embedded RAMDAC capable of interfacing to a wide range of CPUs and LCD displays The S1D13505 supports LCD interfaces with data widths up to 16 bits Using Frame Rate Modulation FRM ...

Page 407: ...e of flexibility for display type and resolution Display types include 4 8 bit monochrome passive 4 8 16 bit color passive 9 12 18 bit Active matrix TFT D TFD other EL REC etc Display resolutions range from 4x1 to 800x600 with color depths from black and white to 64K colors The LCD connector is a 2 x 20 pin 0 100 straight header Pinout assignment is shown in the following table LCD Connector Pinou...

Page 408: ...LD3 LD3 9 FPDAT 4 G1 G2 G4 UD0 UD0 UD0 UD0 UD0 11 FPDAT 5 G0 G1 G3 UD1 UD1 UD1 UD1 UD1 13 FPDAT 6 B2 B3 B5 UD2 UD2 UD2 UD2 UD2 15 FPDAT 7 B1 B2 B4 UD3 UD3 UD3 UD3 UD3 17 FPDAT 8 B0 B1 B3 LD4 19 FPDAT 9 R0 R2 LD5 21 FPDAT 10 R1 LD6 23 FPDAT 11 G0 G2 LD7 25 FPDAT 12 G1 UD4 27 FPDAT 13 G0 UD5 29 FPDAT 14 B0 B2 UD6 31 FPDAT 15 B1 UD7 33 FPSHIFT FPSHIFT 35 or 38 DRDY DRDY MOD FPSHIFT2 Jumper selectable...

Page 409: ...tion Jumpers labelled LCDVCC1 and FPS2 provide LCD logic supply voltage and connector pinout options respectively Jumper options are described in the table below Note Setting the panel supply voltage to 5V does not affect the signalling voltage which remains at 3 3V 2 1 6 Adjustable LCD BIAS Power Supply Many color passive LCD panels require a positive power supply to provide the LCD BIAS voltage ...

Page 410: ...e 01 02 05 LCDPWR is an output signal which follows a pre defined power up power down sequence designed to protect the LCD panel from damage caused by the power supply being enabled in the absence of control signals Determine the panel s specific power requirements and set the potentiometer accordingly before connecting the panel ...

Page 411: ...Connectors Pinout for Channel A7 Channel A7 Pin FPGA Signal S1D13505 Signal Pin FPGA Signal S1D13505 Signal SmXY 1 chA7p1 BCLK 21 dc5v DC5V 2 chA7p2 N C 22 GND GND 3 chA7p3 N C 23 dc3v DC3V 4 chA7p4 N C 24 GND GND 5 chA7p5 N C 25 dc3v DC3V 6 chA7p6 N C 26 GND GND 7 chA7p7 N C 27 dc3vs N C 8 chA7p8 N C 28 GND GND 9 chA7p9 N C 29 dc12v DC12V 10 chA7p10 N C 30 GND GND 11 ib8 N C 31 battery N C 12 ib7...

Page 412: ... GND 7 chA7p17 N C 27 chA7p33 A15 8 chA7p18 A14 28 GND GND 9 chA7p19 A13 29 GND GND 10 chA7p20 A12 30 GND GND 11 chA7p21 A11 31 chA7p32 A10 12 chA7p22 A9 32 GND GND 13 chA7p23 A8 33 GND GND 14 chA7p24 A7 34 GND GND 15 chA7p25 A6 35 GND GND 16 chA7p26 A5 36 chA7p31 A4 17 chA7p27 A3 37 GND GND 18 chA7p28 A2 38 GND GND 19 chA7p29 A1 39 GND GND 20 chA7p30 A0 40 GND GND Table 3 1 Connectors Pinout for ...

Page 413: ... 21 dc5v DC5V 2 chA6p2 BS 22 GND GND 3 chA6p3 WE0 23 dc3v DC3V 4 chA6p4 RD WR 24 GND GND 5 chA6p5 WAIT 25 dc3v DC3V 6 chA6p6 N C 26 GND GND 7 chA6p7 N C 27 dc3vs N C 8 chA6p8 N C 28 GND GND 9 chA6p9 N C 29 dc12v DC12V 10 chA6p10 N C 30 GND GND 11 ib1 XL 31 battery N C 12 ib2 XR 32 GND GND 13 ib3 YU 33 dcXA N C 14 ib4 YL 34 base5vDc N C 15 ib5 N C 35 dcXB N C 16 ib6 N C 36 GND GND 17 ib7 N C 37 dcX...

Page 414: ...D GND 7 chA6p17 N C 27 chA6p33 D15 8 chA6p18 D14 28 GND GND 9 chA6p19 D13 29 GND GND 10 chA6p20 D12 30 GND GND 11 chA6p21 D11 31 chA6p32 D10 12 chA6p22 D9 32 GND GND 13 chA6p23 D8 33 GND GND 14 chA6p24 D7 34 GND GND 15 chA6p25 D6 35 GND GND 16 chA6p26 D5 36 chA6p31 D4 17 chA6p27 D3 37 GND GND 18 chA6p28 D2 38 GND GND 19 chA6p29 D1 39 GND GND 20 chA6p30 D0 40 GND GND Table 3 2 Connectors Pinout for...

Page 415: ...at the center of the system and sits between the CPU and all other peripherals Most peripherals except analog components are implemented within the FPGA In order to support several different CPUs any peripherals that connect to the system have to use a common Register Interface This interface is similar to a standard bus in that it allows the CPU to read and write registers associated with the per...

Page 416: ...9 signal diode 8 2 FPS2 LCDVCC1 Header Header 3x1 1 9 1 JP2 JP3 JP4 JP5 D9000 SmallTypeX Y Z connector D9000 SmallTypeX Y Z connector Samtec TFM 120 11 S D 10 1 J1 PS 2 Connector 15 pin VGA connector 11 1 LCD1 Header Header 20x2 1 12 5 L1 L2 L3 L4 L5 Ferrite bead Ferrite bead on wire 13 1 L6 1uH 1uH inductor 14 1 Q1 MMBT2222A MMBT2222A 15 7 R1 R2 R5 R6 R7 R8 R17 15K 15K 16 3 R9 R10 R11 150 1 150 1...

Page 417: ... 15 D3 BAV99 1 3 2 D2 BAV99 1 3 2 D1 BAV99 1 3 2 R12 39 R13 39 L5 L4 L3 R10 150 1 R9 150 1 R11 150 1 U1 S1D13505F00A AB0 3 AB1 2 AB2 1 AB3 128 AB4 127 AB5 126 AB6 125 AB7 124 AB8 123 AB9 122 AB10 121 AB11 120 AB12 119 AB13 118 AB14 117 AB15 116 AB16 115 MA0 61 MA1 63 MA2 65 MA3 67 MA4 66 MA5 64 MA6 62 MA7 60 MD0 35 MD1 37 MD2 39 MD3 41 MD4 43 MD5 45 MD6 47 MD7 49 MD8 48 MD9 46 MD10 44 MD12 40 MD13...

Page 418: ...DAT8 FPDAT9 FPDAT10 FPDAT11 FPDAT12 FPDAT13 FPDAT14 FPDAT15 CK2 MD5 MD3 RAS MA 0 9 WE UCAS MD 0 15 LCAS VDDH FPDAT 0 15 FPSHIFT FPSHIFT2 FPLINE FPFRAME LCDBACK XL YU LCDPWR XY XR YL VDDH LCDPWR DC3V DC3V DC5V DC12V DC5V DC3V U2 DRAM1MX16 SOJ 3 3V A0 17 A1 18 A2 19 A3 20 A4 23 A5 24 A6 25 A7 26 A8R A8 27 A9R A9 28 A10 NC 16 A11 NC 15 RAS 14 UCAS 30 LCAS 31 W 13 NC 11 NC 12 NC 32 OE 29 DQ0 2 DQ1 3 D...

Page 419: ...T XL XY BCLK RESET M R WE1 RD A 0 20 D 0 15 XR YU YL BS DC3V DC5V DC5V DC3V DC3V DC3V DC12V DC12V JP2 A11_SmZ 1 21 2 22 3 23 4 24 5 25 6 26 7 27 8 28 9 29 10 30 11 31 12 32 13 33 14 34 15 35 16 36 17 37 18 38 19 39 20 40 JP4 A10_SmZ 1 21 2 22 3 23 4 24 5 25 6 26 7 27 8 28 9 29 10 30 11 31 12 32 13 33 14 34 15 35 16 36 17 37 18 38 19 39 20 40 JP5 A10_SmXY 1 21 2 22 3 23 4 24 5 25 6 26 7 27 8 28 9 2...

Page 420: ...Page 22 Epson Research and Development Vancouver Design Center S5U13505 D9000 Evaluation Board User Manual X23A G 002 04 Issue Date 01 02 05 6 Component Placement Figure 6 1 Component Placement ...

Page 421: ...t only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corpor...

Page 422: ...Page 2 Epson Research and Development Vancouver Design Center S1D13505 Power Consumption X23A G 006 03 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 423: ...e the higher the consumption Display mode the resolution and color depth affect power consumption the higher the resolution color depth the higher the consumption Internal CLK divide internal registers allow the input clock to be divided before going to the internal logic blocks the higher the divide the lower the power consumption There are two power save modes in the S1D13505 Software and Hardwa...

Page 424: ...umption depends on the CPU Interface and Input Clock state In a typical design environment the S1D13505 can be configured to be an extremely power efficient LCD Controller with high performance and flexibility Table 1 1 S1D13505 Total Power Consumption Test Condition VDD 3 3V ISA Bus 8MHz Gray Shades Colors Total Power Consumption Active Power Save Mode Software Hardware 1 Input Clock 6MHz LCD Pan...

Page 425: ...d use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark...

Page 426: ...Page 2 Epson Research and Development Vancouver Design Center S1D13505 Interfacing to the Philips MIPS PR31500 PR31700 Processor X23A G 001 07 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 427: ...31500 PR31700 Host Bus Interface Signals 10 4 Direct Connection to the Philips PR31500 PR31700 11 4 1 Hardware Description 11 4 2 S1D13505 Configuration 12 4 3 Memory Mapping and Aliasing 13 5 System Design Using the IT8368E PC Card Buffer 14 5 1 Hardware Description 14 5 2 IT8368E Configuration 15 5 3 S1D13505 Configuration 15 6 Software 16 7 References 17 7 1 Documents 17 7 2 Document Sources 17...

Page 428: ...Page 4 Epson Research and Development Vancouver Design Center S1D13505 Interfacing to the Philips MIPS PR31500 PR31700 Processor X23A G 001 07 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 429: ...A G 001 07 List of Tables Table 3 1 PR31500 PR31700 Host Bus Interface Pin Mapping 9 Table 4 1 S1D13505 Configuration for Direct Connection 12 Table 4 2 PR31500 PR31700 to PC Card Slots Address Remapping for Direct Connection 13 List of Figures Figure 4 1 Typical Implementation of Direct Connection 11 Figure 5 1 IT8368E Implementation Block Diagram 14 ...

Page 430: ...Page 6 Epson Research and Development Vancouver Design Center S1D13505 Interfacing to the Philips MIPS PR31500 PR31700 Processor X23A G 001 07 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 431: ... Embedded RAMDAC LCD CRT Controller and the Philips MIPS PR31500 PR31700 Processor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development...

Page 432: ...o two PC Card PCMCIA slots It is through this host bus interface that the S1D13505 connects to the PR31500 PR31700 processor The S1D13505 can be successfully interfaced using one of the following configurations Direct connection to the PR31500 PR31700 see Section 4 Direct Connection to the Philips PR31500 PR31700 on page 11 System design using the ITE IT8368E PC Card GPIO buffer chip see Section 5...

Page 433: ...the Miscellaneous Disable Register REG 1Bh bit 7 is set to 1 This means that only REG 1Ah read only and REG 1Bh are accessible until a write to REG 1Bh sets bit 7 to 0 making all regis ters accessible When debugging a new hardware design this can sometimes give the appearance that the interface is not working so it is important to remember to clear this bit before proceeding with debugging 3 1 PR3...

Page 434: ...uts AB 16 13 and control inputs M R CS and BS must be tied to VDD as they are not used in this interface mode Address inputs AB 12 0 and the data bus DB 15 0 connect directly to the PR31500 PR31700 address and data bus respectively MD4 must be set to select the proper endian mode on reset see Section 4 2 S1D13505 Configuration on page 12 Because of the PR31500 PR31700 data bus naming convention an...

Page 435: ...r this processor making additional logic unnecessary To further reduce the need for external components the S1D13505 has an optional BUSCLK divide by 2 feature allowing the high speed DCLKOUT from the processor to be directly connected to the BUSCLK input of the S1D13505 An optional external oscillator may be used for BUSCLK since the S1D13505 will accept host bus control signals asynchronously wi...

Page 436: ...ough MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the S1D13505 Hardware Functional Specification document number X23A A 001 xx The table below shows those configuration settings relevant to the Philips PR31500 PR31700 host bus interface Table 4 1 S1D13505 Configuration for Direct Connection S1D13505 Pin Name V...

Page 437: ...3505 on its PC Card slot as described in the table below Table 4 2 PR31500 PR31700 to PC Card Slots Address Remapping for Direct Connection S1D13505 Uses PC Card Slot Philips Address Size Function 1 0800 0000h 16M byte Card 1 IO or Attribute 0900 0000h 8M byte S1D13505 registers aliased 4 times at 2M byte intervals 0980 0000h 8M byte S1D13505 display buffer aliased 4 times at 2M byte intervals 0A0...

Page 438: ... interfaced so as to share one of the PC Card slots 5 1 Hardware Description The IT8368E can be programmed to allocate the same portion of the PC Card Attribute and IO space to the S1D13505 as in the direct connection implementation described in Section 4 Direct Connection to the Philips PR31500 PR31700 on page 11 Following is a block diagram showing an implementation using the IT8368E PC Card buf...

Page 439: ...Philips PR31500 PR31700 on page 11 can be used The IT8368E must have both Fix Attribute IO and VGA modes enabled When both these modes are enabled a 16M byte portion of the system PC Card attribute and IO space is allocated to address the S1D13505 When the IT8368E senses that the S1D13505 is being accessed it does not propagate the PC Card signals to its PC Card device This makes S1D13505 accesses...

Page 440: ...lable for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13505CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13505 test utilities and Windows CE v2 0 display drivers are ava...

Page 441: ...h and Development Inc S1D13505 Hardware Functional Specification Document Number X23A A 001 xx Epson Research and Development Inc S5U13505B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X23A G 004 xx Epson Research and Development Inc S1D13505 Programming Notes and Examples Document Number X23A G 003 xx 7 2 Document Sources Philips Electronics Website http www us2 semiconductors ...

Page 442: ...chnology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electr...

Page 443: ...cument but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Eps...

Page 444: ...Page 2 Epson Research and Development Vancouver Design Center S1D13505 Interfacing to the PC Card Bus X23A G 005 06 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 445: ...2 1 2 Memory Access Cycles 8 3 S1D13505 Host Bus Interface 11 3 1 PC Card Host Bus Interface Pin Mapping 11 3 2 PC Card Host Bus Interface Signals 12 4 PC Card to S1D13505 Interface 13 4 1 Hardware Description 13 4 2 S1D13505 Hardware Configuration 15 4 3 Performance 15 4 4 Register Memory Mapping 16 5 Software 17 6 References 18 6 1 Documents 18 6 2 Document Sources 18 7 Technical Support 19 7 1 ...

Page 446: ...Page 4 Epson Research and Development Vancouver Design Center S1D13505 Interfacing to the PC Card Bus X23A G 005 06 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 447: ... 06 List of Tables Table 3 1 PC Card Host Bus Interface Pin Mapping 11 Table 4 1 Summary of Power On Reset Options 15 Table 4 2 Register Memory Mapping for Typical Implementation 16 List of Figures Figure 2 1 PC Card Read Cycle 9 Figure 2 2 PC Card Write Cycle 10 Figure 4 1 Typical Implementation of PC Card to S1D13505 Interface 14 ...

Page 448: ...Page 6 Epson Research and Development Vancouver Design Center S1D13505 Interfacing to the PC Card Bus X23A G 005 06 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 449: ...edded RAMDAC LCD CRT Controller and the PC Card PCMCIA bus The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comm...

Page 450: ...bit being the most significant Therefore signals A25 and D15 are the most significant bits for the address and data busses respectively Support is provided for on chip DMA controllers To find further information on these topics refer to Section 6 References on page 18 PC Card bus signals are asynchronous to the host CPU bus signals Bus cycles are started with the assertion of the CE1 and or the CE...

Page 451: ... A write cycle is specified by driving OE high and driving the write enable signal WE low The cycle can be lengthened by driving WAIT low for the time needed to complete the cycle Figure 2 1 illustrates a typical memory access read cycle on the PC Card bus Figure 2 1 PC Card Read Cycle A 25 0 CE1 OE WAIT ADDRESS VALID DATA VALID Hi Z Hi Z D 15 0 REG CE2 Transfer Start Transfer Complete ...

Page 452: ...terfacing to the PC Card Bus X23A G 005 06 Issue Date 01 02 05 Figure 2 2 illustrates a typical memory access write cycle on the PC Card bus Figure 2 2 PC Card Write Cycle A 25 0 CE1 OE WAIT ADDRESS VALID DATA VALID Hi Z Hi Z D 15 0 REG CE2 Transfer Start Transfer Complete WE ...

Page 453: ...ite to REG 1Bh sets bit 7 to 0 making all regis ters accessible When debugging a new hardware design this can sometimes give the appearance that the interface is not working so it is important to remember to clear this bit before proceeding with debugging 3 1 PC Card Host Bus Interface Pin Mapping The following table shows the functions of each host bus interface signal Note 1 The bus signal A0 is...

Page 454: ...ress line allowing system address A21 to be connected to the M R line Chip Select CS must be driven low whenever the S1D13505 is accessed by the PC Card bus WE1 and RD WR connect to CE2 and CE1 the byte enables for the high order and low order bytes They are driven low when the PC Card bus is accessing the S1D13505 RD connects to OE the read enable signal from the PC Card bus WE0 connects to WE th...

Page 455: ...ESET signal on the S1D13505 is active low and must be inverted to support the active high RESET provided by the PC Card interface Although the S1D13505 supports an asynchronous bus interface a clock source is required on the BUSCLK input pin In this implementation the address inputs AB 20 0 and data bus DB 15 0 connect directly to the CPU address A 20 0 and data bus D 15 0 M R is treated as an add...

Page 456: ... 4 1 Typical Implementation of PC Card to S1D13505 Interface WE0 RD DB 15 0 WAIT BUSCLK S1D13505 RESET AB 20 0 OE D 15 0 WAIT A 21 0 PC Card socket 15K CLKI Oscillator WE1 RD WR M R CS WE CE1 CE2 RESET A21 BS VDD A 20 0 Note When connecting the S1D13505 RESET pin the system designer should be aware of all conditions that may reset the S1D13505 e g CPU reset can be asserted during wake up from powe...

Page 457: ...st bus interface 4 3 Performance The S1D13505 PC Card Interface specification supports a BCLK up to 50MHz and therefore can provide a high performance display solution Table 4 1 Summary of Power On Reset Options S1D13505 Pin Name value on this pin at rising edge of RESET is used to configure 1 0 1 0 MD0 8 bit host bus interface 16 bit host bus interface MD 3 1 111 PC Card host bus interface select...

Page 458: ...rface on page 14 has Chip Select CS connected to ground always enabled and the Memory Register select pin M R connected to address bit A21 This provides the following decoding The PC Card socket provides 64M byte of address space Without further resolution on the decoding logic M R connected to A21 the entire register set is aliased for every 64 byte boundary within the specified address range abo...

Page 459: ... the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13505CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13505 test utilities and Windows CE v2 0 display drivers are available from yo...

Page 460: ...pment Inc S1D13505 Hardware Functional Specification Document Number X23A A 001 xx Epson Research and Development Inc S1D13505 Programming Notes and Examples Document Number X23A G 003 xx Epson Research and Development Inc S5U13505B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X23A G 004 xx 6 2 Document Sources PC Card Website http www pc card com Epson Electronics America Websi...

Page 461: ... 4346 Taiwan R O C Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 North America Epson Electronics...

Page 462: ...Page 20 Epson Research and Development Vancouver Design Center S1D13505 Interfacing to the PC Card Bus X23A G 005 06 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 463: ...wn use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other t...

Page 464: ...Page 2 Epson Research and Development Vancouver Design Center S1D13505 Interfacing to the NEC VR4102 VR4111 Microprocessors X23A G 007 06 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 465: ...view 8 2 1 2 LCD Memory Access Cycles 9 3 S1D13505 Host Bus Interface 10 3 1 Host Bus Interface Pin Mapping 10 3 2 Host Bus Interface Signals Descriptions 11 4 VR4102 VR4111 to S1D13505 Interface 12 4 1 Hardware Description 12 4 2 S1D13505 Hardware Configuration 13 4 3 NEC VR4102 VR4111 Configuration 13 5 Software 14 6 References 15 6 1 Documents 15 6 2 Document Sources 15 7 Technical Support 16 7...

Page 466: ...Page 4 Epson Research and Development Vancouver Design Center S1D13505 Interfacing to the NEC VR4102 VR4111 Microprocessors X23A G 007 06 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 467: ...1 Microprocessors S1D13505 Issue Date 01 02 05 X23A G 007 06 List of Tables Table 3 1 Host Bus Interface Pin Mapping 10 Table 4 1 Summary of Power On Reset Options 13 List of Figures Figure 2 1 NEC VR4102 VR4111 Read Write Cycles 9 Figure 4 1 NEC VR4102 VR4111 to S1D13505 Configuration Schematic 12 ...

Page 468: ...Page 6 Epson Research and Development Vancouver Design Center S1D13505 Interfacing to the NEC VR4102 VR4111 Microprocessors X23A G 007 06 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 469: ...MDAC LCD CRT Controller and the NEC VR4102TM µPD30102 or VR4111TM µPD30111 Microprocessors The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Electronics America Website at http www eea epson com for the latest revision of this document before beginning any dev...

Page 470: ...o establish interface requirements 2 1 1 Overview The NEC VR4102 VR4111 is designed around the RISC architecture developed by MIPS This microprocessor is based on the 66MHz VR4100 CPU core which supports 64 bit processing The CPU communicates with the Bus Control Unit BCU using its internal SysAD bus The BCU in turn communicates with external devices using its ADD and DAT buses which can be dynami...

Page 471: ...DCS is driven low The read or write enable signals RD or WR are driven low for the appropriate cycle and LCDRDY is driven low to insert wait states into the cycle The high byte enable SHB in conjunction with address bit 0 allows for byte steering The following figure illustrates typical NEC VR4102 VR4111 memory read and write cycles to the LCD controller interface Figure 2 1 NEC VR4102 VR4111 Read...

Page 472: ...tion on page 13 Note At reset the Host Interface Disable bit in the Miscellaneous Disable Register REG 1Bh bit 7 is set to 1 This means that only REG 1Ah read only and REG 1Bh are accessible until a write to REG 1Bh sets bit 7 to 0 making all regis ters accessible When debugging a new hardware design this can sometimes give the appearance that the interface is not working so it is important to rem...

Page 473: ...cessed by the VR4102 VR4111 WE1 connects to SHB the high byte enable signal from the VR4102 VR4111 which in conjunction with address bit 0 allows byte steering of read and write operations WE0 connects to WR the write enable signal from the VR4102 VR4111 and must be driven low when the VR4102 VR4111 is writing data to the S1D13505 RD connects to RD the read enable signal from the VR4102 VR4111 and...

Page 474: ...he diagram below shows a typical implementation utilizing the S1D13505 Figure 4 1 NEC VR4102 VR4111 to S1D13505 Configuration Schematic Note For pin mapping see Table 3 1 Host Bus Interface Pin Mapping on page 10 WE1 WE0 DB 15 0 WAIT RD BUSCLK S1D13505 CS M R RESET AB 20 0 ADD21 SHB WR DAT 15 0 LCDCS RD BUSCLK LCDRDY ADD 25 0 NEC VR4102 VR4111 Pull up BS RD WR VDD VDD System RESET Note When connec...

Page 475: ...0h to 0AFF FFFFh 16M bytes is reserved for an external LCD controller The S1D13505 supports up to 2M bytes of display buffer The NEC VR4102 VR4111 address line A21 is used to select between the S1D13505 display buffer A21 1 and internal registers A21 0 The NEC VR4102 VR4111 has a 16 bit internal register named BCUCNTREG2 located at address 0B00 0002h It must be set to the value of 0001h to indicat...

Page 476: ...le for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13505CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13505 test utilities and Windows CE v2 0 display drivers are availa...

Page 477: ...nary Users Manual Document Number U13137EJ2V0UM00 Epson Research and Development Inc S1D13505 Hardware Functional Specification Document Number X23A A 001 xx Epson Research and Development Inc S5U13505B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X23A G 004 xx Epson Research and Development Inc S1D13505 Programming Notes and Examples Document Number X23A G 003 xx 6 2 Document S...

Page 478: ...i Hong Kong Tel 2585 4600 Fax 2827 4346 Taiwan R O C Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 1...

Page 479: ...e this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of ...

Page 480: ...Page 2 Epson Research and Development Vancouver Design Center S1D13505 Interfacing to the Motorola MPC821 Microprocessor X23A G 008 05 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 481: ... Purpose Chip Select Module GPCM 11 2 3 2 User Programmable Machine UPM 12 3 S1D13505 Host Bus Interface 13 3 1 PowerPC Host Bus Interface Pin Mapping 13 3 2 PowerPC Host Bus Interface Signals 14 4 MPC821 to S1D13505 Interface 15 4 1 Hardware Description 15 4 2 Hardware Connections 16 4 3 S1D13505 Hardware Configuration 18 4 4 Register Memory Mapping 18 4 5 MPC821 Chip Select Configuration 19 4 6 ...

Page 482: ...Page 4 Epson Research and Development Vancouver Design Center S1D13505 Interfacing to the Motorola MPC821 Microprocessor X23A G 008 05 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 483: ... 008 05 List of Tables Table 3 1 PowerPC Host Bus Interface Pin Mapping 13 Table 4 1 List of Connections from MPC821ADS to S1D13505 16 Table 4 2 Summary of Power On Reset Options 18 List of Figures Figure 2 1 Power PC Memory Read Cycle 9 Figure 2 2 Power PC Memory Write Cycle 10 Figure 4 1 Typical Implementation of MPC821 to S1D13505 Interface 15 ...

Page 484: ...Page 6 Epson Research and Development Vancouver Design Center S1D13505 Interfacing to the Motorola MPC821 Microprocessor X23A G 008 05 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 485: ... Embedded RAMDAC LCD CRT Controller and the Motorola MPC821 processor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Electronics America Website at http www eea epson com for the latest revision of this document before beginning any development We appreciat...

Page 486: ...ming generators the General Purpose Chip Select Module GPCM or the User Programmable Machine UPM Examples are given using the GPCM It should be noted that all Power PC microprocessors including the MPC8xx family use bit notation opposite from the convention used by most other microprocessor systems Bit numbering for the MPC8xx always starts with zero as the most significant bit and incre ments in ...

Page 487: ...cles and low for write cycles AT 0 3 Address Type Signals provides more detail on the type of transfer being attempted When the peripheral device being accessed has completed the bus transfer it asserts TA Transfer Acknowledge for one clock cycle to complete the bus transaction Once TA has been asserted the MPC821 will not start another bus cycle until TA has been de asserted The minimum length of...

Page 488: ...lines A30 and A31 are ignored For 16 bit transfers data lines D 0 15 are used and address line A31 is ignored For 8 bit transfers data lines D 0 7 are used and all address lines A 0 31 are used Note This assumes that the Power PC core is operating in big endian mode typically the case for embedded systems 2 2 2 Burst Cycles Burst memory cycles are used to fill on chip cache memory and to carry out...

Page 489: ...utput it can generate active low Output Enable OE and Write Enable WE signals compatible with most memory and x86 style peripherals The MPC821 bus controller also provides a Read Write RD WR signal which is compatible with most 68K peripherals The GPCM is controlled by the values programmed into the Base Register BR and Option Register OR of the respective chip select The Option Register sets the ...

Page 490: ...rol address multiplexing wait state gener ation and five general purpose output lines on the MPC821 Up to 64 pattern locations are available each 32 bits wide Separate patterns may be programmed for normal accesses burst accesses refresh timer events and exception conditions This flexibility allows almost any type of memory or peripheral device to be accommodated by the MPC821 In this application ...

Page 491: ...ote At reset the Host Interface Disable bit in the Miscellaneous Disable Register REG 1Bh bit 7 is set to 1 This means that only REG 1Ah read only and REG 1Bh are accessible until a write to REG 1Bh sets bit 7 to 0 making all regis ters accessible When debugging a new hardware design this can sometimes give the appearance that the interface is not working so it is important to remember to clear th...

Page 492: ... the S1D13505 is accessed by the PowerPC bus RD WR connects to RD WR which indicates whether a read or a write access is being performed on the S1D13505 WE1 connects to BI burst inhibit signal WE1 is output by the S1D13505 to indicate whether the S1D13505 is able to perform burst accesses WE0 and RD connect to TSIZ1 and TSIZ0 high and low byte enable signals These signals must be driven by the Pow...

Page 493: ...y buffer the S1D13505 can reduce system power consumption improve image quality and increase system performance as compared to the MPC821 s on chip LCD controller The S1D13505 through the use of the MPC821 chip selects can share the system bus with all other MPC821 peripherals The following figure demonstrates a typical implementation of the S1D13505 to MPC821 interface Figure 4 1 Typical Implemen...

Page 494: ...stem no buffering is necessary 4 2 Hardware Connections The following table details the connections between the pins and signals of the MPC821 and the S1D13505 Table 4 1 List of Connections from MPC821ADS to S1D13505 MPC821 Signal Name MPC821ADS Connector and Pin Name S1D13505 Signal Name Vcc P6 A1 P6 B1 Vcc A10 P6 C23 M R A11 P6 A22 AB20 A12 P6 B22 AB19 A13 P6 C21 AB18 A14 P6 C20 AB17 A15 P6 D20 ...

Page 495: ...2 A15 DB7 D9 P12 C15 DB6 D10 P12 D15 DB5 D11 P12 A14 DB4 D12 P12 B14 DB3 D13 P12 D14 DB2 D14 P12 B13 DB1 D15 P12 C13 DB0 SRESET P9 D15 RESET SYSCLK P9 C2 BUSCLK CS4 P6 D13 CS TS P6 B7 BS TA P6 B6 WAIT R W P6 D8 RD WR TSIZ0 P6 B18 RD TSIZ1 P6 C18 WE0 BI P6 B9 WE1 Gnd P12 A1 P12 B1 P12 A2 P12 B2 P12 A3 P12 B3 P12 A4 P12 B4 P12 A5 P12 B5 P12 A6 P12 B6 P12 A7 Vss Table 4 1 List of Connections from MPC...

Page 496: ...1 ADS board extends from address 0 through 3F FFFFh so the S1D13505 is addressed starting at 40 0000h A total of 4M bytes of address space is used where the lower 2M bytes is reserved for the S1D13505 on chip registers and the upper 2M bytes is used to access the S1D13505 display buffer Table 4 2 Summary of Power On Reset Options S1D13505 Pin Name value on this pin at rising edge of RESET is used ...

Page 497: ...te protect MS 0 1 0 0 select General Purpose Chip Select module to control this chip select V 1 set valid bit to enable chip select The following options were selected in the option register OR4 AM 0 16 1111 1111 1100 0000 0 mask all but upper 10 address bits S1D13505 consumes 4M byte of address space ATM 0 2 0 ignore address type bits CSNT 0 normal CS WE negation ACS 0 1 1 1 delay CS assertion by...

Page 498: ...d If the data cache is enabled then the MMU must be set so that the S1D13505 memory block is tagged as non cacheable This ensures the MPC821 does not attempt to cache any data read from or written to the S1D13505 or its display buffer BR4 equ 120 CS4 base register OR4 equ 124 CS4 option register MemStart equ 40 upper word of S1D13505 start address DisableReg equ 1b address of S1D13505 Disable Regi...

Page 499: ...ble for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13505CFG or by directly modifying the source The Windows CE display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13505 test utilities and Windows CE display drivers are available from ...

Page 500: ...tems Microprocessor User s Manual Motorola Publication no MPC821UM AD Epson Research and Development Inc S1D13505 Hardware Functional Specification Document Number X23A A 001 xx Epson Research and Development Inc S5U13505B00B Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X19A G 001 xx 6 2 Document Sources Motorola Literature Distribution Center 800 441 2447 Epson Electronics America...

Page 501: ... Fax 042 587 5564 http www epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 Taiwan R O C Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 33...

Page 502: ...Page 24 Epson Research and Development Vancouver Design Center S1D13505 Interfacing to the Motorola MPC821 Microprocessor X23A G 008 05 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 503: ...e this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of ...

Page 504: ...Page 2 Epson Research and Development Vancouver Design Center S1D13505 Interfacing to the Toshiba MIPS TX3912 Processor X23A G 010 04 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 505: ...3912 Host Bus Interface Signals 10 4 Direct Connection to the Toshiba TX3912 11 4 1 Hardware Description 11 4 2 S1D13505 Configuration 12 4 3 Memory Mapping and Aliasing 13 5 System Design Using the IT8368E PC Card Buffer 14 5 1 Hardware Description 14 5 2 IT8368E Configuration 15 5 3 S1D13505 Configuration 15 6 Software 16 7 References 17 7 1 Documents 17 7 2 Document Sources 17 8 Technical Suppo...

Page 506: ...Page 4 Epson Research and Development Vancouver Design Center S1D13505 Interfacing to the Toshiba MIPS TX3912 Processor X23A G 010 04 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 507: ...5 X23A G 010 04 List of Tables Table 3 1 TX3912 Host Bus Interface Pin Mapping 9 Table 4 1 S1D13505 Configuration for Direct Connection 12 Table 4 2 TX3912 to PC Card Slots Address Remapping for Direct Connection 13 List of Figures Figure 4 1 Typical Implementation of Direct Connection 11 Figure 5 1 IT8368E Implementation Block Diagram 14 ...

Page 508: ...Page 6 Epson Research and Development Vancouver Design Center S1D13505 Interfacing to the Toshiba MIPS TX3912 Processor X23A G 010 04 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 509: ... Embedded RAMDAC LCD CRT Controller and the Toshiba MIPS TX3912 Processor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appre...

Page 510: ...o two PC Card PCMCIA slots It is through this host bus interface that the S1D13505 connects to the TX3912 processor The S1D13505 can be successfully interfaced using one of the following configurations Direct connection to the TX3912 see Section 4 Direct Connection to the Toshiba TX3912 on page 11 System design using the ITE IT8368E PC Card GPIO buffer chip see Section 5 System Design Using the IT...

Page 511: ...the Miscellaneous Disable Register REG 1Bh bit 7 is set to 1 This means that only REG 1Ah read only and REG 1Bh are accessible until a write to REG 1Bh sets bit 7 to 0 making all regis ters accessible When debugging a new hardware design this can sometimes give the appearance that the interface is not working so it is important to remember to clear this bit before proceeding with debugging 3 1 TX3...

Page 512: ...16 13 and control inputs M R CS and BS must be tied to VDD as they are not used in this interface mode Address inputs AB 12 0 and the data bus DB 15 0 connect directly to the TX3912 address and data bus respectively MD4 must be set to select the proper endian mode on reset see Section 4 2 S1D13505 Configuration on page 12 Because of the TX3912 data bus naming convention and endian mode S1D13505 DB...

Page 513: ...ocessor making additional logic unnecessary To further reduce the need for external components the S1D13505 has an optional BUSCLK divide by 2 feature allowing the high speed DCLKOUT from the processor to be directly connected to the BUSCLK input of the S1D13505 An optional external oscillator may be used for BUSCLK since the S1D13505 will accept host bus control signals asynchronously with respec...

Page 514: ... MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the S1D13505 Hardware Functional Specification document number X23A A 001 xx The table below shows those configuration settings relevant to the Toshiba TX3912 host bus interface Table 4 1 S1D13505 Configuration for Direct Connection S1D13505 Pin Name V...

Page 515: ...C Card slot as described in the table below Table 4 2 TX3912 to PC Card Slots Address Remapping for Direct Connection S1D13505 Uses PC Card Slot Toshiba Address Size Function 1 0800 0000h 16M byte Card 1 IO or Attribute 0900 0000h 8M byte S1D13505 registers aliased 4 times at 2M byte intervals 0980 0000h 8M byte S1D13505 display buffer aliased 4 times at 2M byte intervals 0A00 0000h 32M byte Card ...

Page 516: ...an be interfaced so as to share one of the PC Card slots 5 1 Hardware Description The IT8368E can be programmed to allocate the same portion of the PC Card Attribute and IO space to the S1D13505 as in the direct connection implementation described in Section 4 Direct Connection to the Toshiba TX3912 on page 11 Following is a block diagram showing an implementation using the IT8368E PC Card buffer ...

Page 517: ...Toshiba TX3912 on page 11 can be used The IT8368E must have both Fix Attribute IO and VGA modes enabled When both these modes are enabled a 16M byte portion of the system PC Card attribute and IO space is allocated to address the S1D13505 When the IT8368E senses that the S1D13505 is being accessed it does not propagate the PC Card signals to its PC Card device This makes S1D13505 accesses transpar...

Page 518: ... for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13505CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13505 test utilities and Windows CE v2 0 display drivers are availabl...

Page 519: ... Development Inc S1D13505 Hardware Functional Specification Document Number X23A A 001 xx Epson Research and Development Inc S5U13505B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X23A G 004 xx Epson Research and Development Inc S1D13505 Programming Notes and Examples Document Number X23A G 003 xx 7 2 Document Sources Toshiba America Electrical Components Website http www toshib...

Page 520: ...x 2827 4346 Taiwan R O C Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www ...

Page 521: ...se in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trade...

Page 522: ...Page 2 Epson Research and Development Vancouver Design Center S1D13505 Interfacing to the NEC VR4121 Microprocessor X23A G 011 04 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 523: ...2 LCD Memory Access Cycles 9 3 S1D13505 Host Bus Interface 10 3 1 Host Bus Interface Pin Mapping 10 3 2 Host Bus Interface Signal Descriptions 11 4 VR4121 to S1D13505 Interface 12 4 1 Hardware Description 12 4 2 S1D13505 Configuration 13 4 3 NEC VR4121 Configuration 13 4 4 Memory Mapping and Aliasing 14 5 Software 15 6 References 16 6 1 Documents 16 6 2 Document Sources 16 7 Technical Support 17 7...

Page 524: ...Page 4 Epson Research and Development Vancouver Design Center S1D13505 Interfacing to the NEC VR4121 Microprocessor X23A G 011 04 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 525: ...R4121 Microprocessor S1D13505 Issue Date 01 02 05 X23A G 011 04 List of Tables Table 3 1 Host Bus Interface Pin Mapping 10 Table 4 1 Summary of Power On Reset Options 13 List of Figures Figure 2 1 NEC VR4121 Read Write Cycles 9 Figure 4 1 NEC VR4121 to S1D13505 Configuration Schematic 12 ...

Page 526: ...Page 6 Epson Research and Development Vancouver Design Center S1D13505 Interfacing to the NEC VR4121 Microprocessor X23A G 011 04 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 527: ...dded RAMDAC LCD CRT Controller and the NEC VR4121TM µPD30121 microprocessor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We app...

Page 528: ...blish interface requirements 2 1 1 Overview The NEC VR4121 is designed around the RISC architecture developed by MIPS This microprocessor is based on the 166MHz VR4120 CPU core which supports 64 bit processing The CPU communicates with the Bus Control Unit BCU using its internal SysAD bus The BCU in turn communicates with external devices using its ADD and DATA buses which can be dynamically sized...

Page 529: ... LCDCS is driven low The read or write enable signals RD or WR are driven low for the appropriate cycle and LCDRDY is driven low to insert wait states into the cycle The high byte enable SHB in conjunction with address bit 0 allows for byte steering The following figure illustrates typical NEC VR4121 memory read and write cycles to the LCD controller interface Figure 2 1 NEC VR4121 Read Write Cycl...

Page 530: ...age 13 Note At reset the Host Interface Disable bit in the Miscellaneous Disable Register REG 1Bh bit 7 is set to 1 This means that only REG 1Ah read only and REG 1Bh are accessible until a write to REG 1Bh sets bit 7 to 0 making all regis ters accessible When debugging a new hardware design this can sometimes give the appearance that the interface is not working so it is important to remember to ...

Page 531: ...D13505 is accessed by the VR4121 WE1 connects to SHB the high byte enable signal from the VR4121 which in conjunction with address bit 0 allows byte steering of read and write operations WE0 connects to WR the write enable signal from the VR4121 and must be driven low when the VR4121 bus is writing data to the S1D13505 RD connects to RD the read enable signal from the VR4121 and must be driven low...

Page 532: ...diagram below shows a typical implementation utilizing the S1D13505 Figure 4 1 NEC VR4121 to S1D13505 Configuration Schematic Note For pin mapping see Table 3 1 Host Bus Interface Pin Mapping on page 10 WE1 WE0 DB 15 0 WAIT RD BUSCLK S1D13505 CS M R RESET AB 20 0 ADD21 SHB WR DAT 15 0 LCDCS RD BUSCLK LCDRDY ADD 25 0 NEC VR4121 Pull up BS RD WR VDD 3 3V System RESET VDD VDD3 3 3V 2 5V VDD2 Note Whe...

Page 533: ...us is used for LCD controller accesses The LCD interface must be set to operate using a 16 bit data bus This is accomplished by setting the NEC VR4121 register BCUCNTREG3 bit LCD32 ISA32 to 0 Note Setting the register BCUCNTREG3 bit LCD32 ISA32 to 0 affects both the LCD con troller and high speed ISA memory access The frequency of BUSCLK output is programmed from the state of pins TxD CLKSEL2 RTS ...

Page 534: ...h 16M bytes is reserved for use by an external LCD controller e g S1D13505 The S1D13505 supports up to 2M bytes of display buffer The NEC VR4121 address line ADD21 connected to M R is used to select between the S1D13505 display buffer ADD21 1 and the S1D13505 internal registers ADD21 0 NEC VR4121 address lines ADD 23 22 are ignored thus the S1D13505 is aliased four times at 4M byte intervals over ...

Page 535: ...or both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13505CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13505 test utilities and Windows CE v2 0 display drivers are available ...

Page 536: ...M00 Epson Research and Development Inc S1D13505 Hardware Functional Specification Document Number X23A A 001 xx Epson Research and Development Inc S5U13505B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X23A G 004 xx Epson Research and Development Inc S1D13505 Programming Notes and Examples Document Number X23A G 003 xx 6 2 Document Sources NEC Electronics Website http www necel ...

Page 537: ...5 4600 Fax 2827 4346 Taiwan R O C Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 North America Ep...

Page 538: ...Page 18 Epson Research and Development Vancouver Design Center S1D13505 Interfacing to the NEC VR4121 Microprocessor X23A G 011 04 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 539: ...in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademar...

Page 540: ...Page 2 Epson Research and Development Vancouver Design Center S1D13505 Interfacing to the NEC V832 Microprocessor X23A G 012 02 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 541: ... 2 Access Cycles 9 3 S1D13505 Host Bus Interface 10 3 1 Host Bus Interface Pin Mapping 10 3 2 Host Bus Interface Signal Descriptions 11 4 V832 to S1D13505 Interface 12 4 1 Hardware Description 12 4 2 S1D13505 Hardware Configuration 13 4 3 NEC V832 Configuration 14 4 4 Memory Mapping and Aliasing 15 5 Software 16 6 References 17 6 1 Documents 17 6 2 Document Sources 17 7 Technical Support 18 7 1 Ep...

Page 542: ...Page 4 Epson Research and Development Vancouver Design Center S1D13505 Interfacing to the NEC V832 Microprocessor X23A G 012 02 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 543: ... 012 02 List of Tables Table 3 1 Host Bus Interface Pin Mapping 10 Table 4 1 Summary of Power On Reset Options 13 Table 4 2 NEC V832 Wait States vs Bus Clock Frequency 14 Table 4 3 NEC V832 IO Address Range For Each CSn Line 15 List of Figures Figure 2 1 NEC V832 Read Write Cycles 9 Figure 4 1 NEC V832 to S1D13505 Configuration Schematic 12 ...

Page 544: ...Page 6 Epson Research and Development Vancouver Design Center S1D13505 Interfacing to the NEC V832 Microprocessor X23A G 012 02 Issue Date 01 02 05 THIS PAGE LEFT BLANK ...

Page 545: ...ded RAMDAC LCD CRT Controller and the NEC V832TM microprocessor µPD705102 The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Electronics America Website at http www eea epson com for the latest revision of this document before beginning any development We appre...

Page 546: ...chitecture developed by MIPS This microprocessor is based on the 32 bit V830 CPU core The CPU communicates with external devices via the Bus Control Unit BCU The BCU in turn communicates using its ADD and DATA buses which can be dynamically sized to 16 or 32 bit operation The NEC V832 features dedicated chip select pins which allow memory mapped IO operations A 16M byte block of addressing space c...

Page 547: ...orresponding chip select CSn is driven low The read or write enable signals IORD or IOWR are driven low and READY is driven low by the S1D13505 to insert wait states into the cycle The byte enable signals LLBEN and LUBEN allow byte steering The following figure illustrates typical NEC V832 memory mapped IO access cycles Figure 2 1 NEC V832 Read Write Cycles SDCLKOUT A 23 1 CSn IORD READY VALID VAL...

Page 548: ...t Interface Disable bit in the Miscellaneous Disable Register REG 1Bh bit 7 is set to 1 This means that only REG 1Ah read only and REG 1Bh are accessible until a write to REG 1Bh sets bit 7 to 0 making all regis ters accessible When debugging a new hardware design this can sometimes give the appearance that the interface is not working so it is important to remember to clear this bit before procee...

Page 549: ...s accessed by the V832 WE1 and RD WR connect to LUBEN and LLBEN the byte enables for the high order and low order bytes They are driven low when the V832 is accessing the S1D13505 RD connects to IORD the read enable signal from the V832 WE0 connects to IOWR the write enable signal from the V832 WAIT is a signal output from the S1D13505 that indicates the V832 must wait until data is ready read cyc...

Page 550: ...13505 The diagram below shows a typical implementation utilizing the S1D13505 Figure 4 1 NEC V832 to S1D13505 Configuration Schematic Note For pin mapping see Table 3 1 Host Bus Interface Pin Mapping on page 10 WE1 WE0 DB 15 0 WAIT RD BUSCLK S1D13505 CS M R RESET AB 20 1 A21 LUBEN IOWR D 15 0 CSn IORD SDCLKOUT READY A 25 1 NEC V832 Pull up BS VDD VDD 3 3V System RESET AB0 VDD_O 3 3V 2 5V VDD_I RD ...

Page 551: ...elow shows those configuration settings relevant to the PC Card host bus interface used by the NEC V832 microprocessor Table 4 1 Summary of Power On Reset Options S1D13505 Pin Name Value on this pin at rising edge of RESET is used to configure 1 0 1 0 MD0 8 bit host bus interface 16 bit host bus interface MD 3 1 111 PC Card host bus interface MD4 Little Endian Big Endian MD5 WAIT is active high 1 ...

Page 552: ...tes may be required These need to be programmed into the NEC V832 PWC0 and PWC1 registers in the bit field corresponding to the CSn line chosen for the S1D13505 For example if CS3 controls the S1D13505 and one wait state is required then bits 14 12 of the NEC V832 PWC0 register WS3 must be set to 001b one wait state If CS6 controls the S1D13505 and no wait state is needed then bits 11 8 of the NEC...

Page 553: ...ess range is 16M bytes therefore the S1D13505 is aliased four times over the address range Table 4 3 NEC V832 IO Address Range For Each CSn Line CSn Line NEC V832 IO Address S1D13505 Function CS3 0300 0000h to 03FF FFFFh 0300 0000h Registers 0320 0000h Display buffer 2M bytes CS4 0400 0000h to 04FF FFFFh 0400 0000h Registers 0420 0000h Display buffer 2M bytes CS5 0500 0000h to 05FF FFFFh 0500 0000...

Page 554: ...available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13505CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13505 test utilities and Windows CE v2 0 display drivers are...

Page 555: ...0 Epson Research and Development Inc S1D13505 Hardware Functional Specification Document Number X23A A 001 xx Epson Research and Development Inc S5U13505B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X23A G 004 xx Epson Research and Development Inc S1D13505 Programming Notes and Examples Document Number X23A G 003 xx 6 2 Document Sources NEC Electronics Website http www necel co...

Page 556: ... Tel 2585 4600 Fax 2827 4346 Taiwan R O C Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 North Am...

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