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EPSON

S1C63454 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Fig. 4.13.1 Configuration of the interrupt circuit

IT3

EIT3

IT2

EIT2

IT1

EIT1

IT0

EIT0

ISW1

EISW1

ISW10

EISW10

IPT0

EIPT0

IPT1

EIPT1

Interrupt

vector

generation

circuit

Program counter
(low-order 4 bits)

INT
interrupt request

NMI
interrupt request

Watchdog timer

Interrupt factor flag

Interrupt mask register

Input comparison register

Interrupt selection register

Interrupt flag

ISIF

EISIF

K00

KCP00

SIK00

K01

KCP01

SIK01

K02

KCP02

SIK02

K03

KCP03

SIK03

IK0

EIK0

Summary of Contents for S1C63454

Page 1: ...MF1074 03 Technical Manual CMOS 4 BIT SINGLE CHIP MICROCOMPUTER S1C63454 Technical Hardware S1C63454 ...

Page 2: ...uiring high level reliability such as medical products Moreover no license to any intellectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party This material or portions thereof may contain technology or the subject relating to...

Page 3: ...sions and Additions for this manual Section 7 5 Page 103 111 Item OSC1 crystal oscillation circuit Appendix Contents The table was revised The Appendix was added Chapter 7 Appendix S1C63454 Technical Manual ...

Page 4: ......

Page 5: ...al versions are not written in the manuals Previous No E0C63158 E0C63256 E0C63358 E0C63P366 E0C63404 E0C63406 E0C63408 E0C63F408 E0C63454 E0C63455 E0C63458 E0C63466 E0C63P466 New No S1C63158 S1C63256 S1C63358 S1C6P366 S1C63404 S1C63406 S1C63408 S1C6F408 S1C63454 S1C63455 S1C63458 S1C63466 S1C6P466 S1C63 Family peripheral products Previous No E0C63467 E0C63557 E0C63558 E0C63567 E0C63F567 E0C63658 E...

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Page 7: ...APTER 3 CPU ROM RAM________________________________________ 12 3 1 CPU 12 3 2 Code ROM 12 3 3 RAM 12 3 4 Data ROM 13 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION__________________________ 14 4 1 Memory Map 14 4 2 Watchdog Timer 19 4 2 1 Configuration of watchdog timer 19 4 2 2 Interrupt function 19 4 2 3 I O memory of watchdog timer 20 4 2 4 Programming notes 20 4 3 Oscillation Circuit 21 4 3 1 Con...

Page 8: ...ock Timer 50 4 8 1 Configuration of clock timer 50 4 8 2 Data reading and hold function 50 4 8 3 Interrupt function 51 4 8 4 I O memory of clock timer 52 4 8 5 Programming notes 54 4 9 Stopwatch Timer 55 4 9 1 Configuration of stopwatch timer 55 4 9 2 Count up pattern 55 4 9 3 Interrupt function 56 4 9 4 I O memory of stopwatch timer 57 4 9 5 Programming notes 58 4 10 Programmable Timer 59 4 10 1 ...

Page 9: ... DIAGRAM ____________________________ 98 CHAPTER 7 ELECTRICAL CHARACTERISTICS ________________________________ 99 7 1 Absolute Maximum Rating 99 7 2 Recommended Operating Conditions 99 7 3 DC Characteristics 100 7 4 Analog Circuit Characteristics and Power Current Consumption 101 7 5 Oscillation Characteristics 103 7 6 Serial Interface AC Characteristics 105 7 7 Timing Chart 106 CHAPTER 8 PACKAGE ...

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Page 11: ... bits RAM capacity Data memory 1 024 words 4 bits Display memory 680 bits 160 words 4 bits 40 1 bit Input port 4 bits Pull up resistors may be supplemented 1 Output port 4 bits It is possible to switch the 2 bits to special output 2 I O port 8 bits It is possible to switch the 4 bits to serial I F input output 2 Serial interface 1 port 8 bit clock synchronous system LCD driver 40 segments 8 16 or ...

Page 12: ...EST RESET P00 P03 P10 P13 R00 R03 Core CPU S1C63000 ROM 4 096 words 13 bits System Reset Control Interrupt Generator OSC RAM 1 024 words 4 bits Data ROM 2 048 words 4 bits LCD Driver 40 SEG 17 COM Power Controller Sound Generator Stopwatch Timer Clock Timer Programmable Timer Serial Interface Input Port I O Port Output Port Fig 1 2 1 Block diagram ...

Page 13: ...82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Name SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 BZ VSS OSC1 OSC2 VD1 OSC3 OSC4 Name VDD N C N C RESET TEST VREF R03 R02 R01 R00 P13 P12 P11 P10 P03 P02 P01 P00 K03 K02 K01 K00 N C N C N C Name VC1 VC2 VC3 VC4 VC5 CF CE CD CC CB CA COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 SEG39 SEG38 ...

Page 14: ...utput is possible by software Output port switching to FOUT signal output is possible by software LCD common output pin 1 8 1 16 1 17 duty can be selected by software LCD segment output pin Sound output pin Initial reset input pin Testing input pin In Out O I O I O I I O I O O O O O O O O I I 1 5 Mask Option Mask options shown below are provided for the S1C63454 Several hardware specifications are...

Page 15: ... I O port P10 P13 as the serial interface input output terminals the input specifica tion for the terminals that are used for the serial interface input can be selected from either normal input or with Schmitt trigger input This option is applied to the serial interface input terminals and is fixed at normal input when the terminals are used for the I O port P10 P13 Refer to Section 4 6 2 Mask opt...

Page 16: ...e K00 K01 K02 K03 3 Use K00 K01 K02 4 Use K00 K01 4 MULTIPLE KEY ENTRY RESET TIME AUTHORIZE 1 Not Use 2 Use 5 INPUT PORT PULL UP RESISTOR K00 1 With Resistor 2 Gate Direct K01 1 With Resistor 2 Gate Direct K02 1 With Resistor 2 Gate Direct K03 1 With Resistor 2 Gate Direct 6 OUTPUT PORT OUTPUT SPECIFICATION R00 1 Complementary 2 Nch OpenDrain R01 1 Complementary 2 Nch OpenDrain R02 1 Complementary...

Page 17: ...e 2 1 2 Table 2 1 2 Power supply circuits Circuit Oscillation and internal circuits LCD driver Power supply circuit Oscillation system voltage regulator LCD system voltage circuit Output voltage VD1 VC1 VC5 Note Do not drive external loads with the output voltage from the internal power supply circuits VC3 should be used only when the LCD drive voltage is supplied externally 1 5 bias when using th...

Page 18: ...5 for LCD driving VC1 VC5 are the LCD drive voltages for which either the voltage generated by the LCD system voltage circuit or voltage to be supplied from outside can be used The built in LCD system voltage circuit generates four voltages 1 4 bias VC1 VC2 VC4 and VC5 excluding VC3 These four output voltages can only be supplied to the externally expanded LCD driver When external voltages are sup...

Page 19: ...to a low level VSS After that the initial reset is released by setting the reset terminal to a high level VDD and the CPU starts operation The reset input signal is maintained by the RS latch and becomes the internal initial reset signal The RS latch is designed to be released by a 2 Hz signal high that is divided by the OSC1 clock Therefore in normal operation a maximum of 250 msec when fOSC1 32 ...

Page 20: ...at the same time When 3 or 4 is selected the initial reset is done when a key entry including a combination of selected input ports is made Further the time authorize circuit can be selected with the mask option The time authorize circuit checks the input time of the simultaneous low input and performs initial reset if that time is the defined time 1 to 2 sec or more If using this function make su...

Page 21: ...hese functions are selected by the software At initial reset these terminals are set to the general purpose output port terminals and I O port terminals Set them according to the system in the initial routine In addition take care of the initial status of output terminals when designing a system Table 2 2 4 1 shows the list of the shared terminal settings Table 2 2 4 1 List of shared terminal sett...

Page 22: ...s 0000H to 03FFH on the data memory map Addresses 0100H to 01FFH are 4 bit 16 bit data accessible areas and in other areas it is only possible to access 4 bit data When programming keep the following points in mind 1 Part of the RAM area is used as a stack area for subroutine call and register evacuation so pay attention not to overlap the data area and stack area 2 The S1C63000 core CPU handles t...

Page 23: ...bit data 0000H 00FFH 0100H 01FFH 0200H 03FFH 4 bits 4 bit access area SP2 stack area 4 bit access area Data area 4 16 bit access area SP1 stack area Fig 3 3 1 Configuration of data RAM 3 4 Data ROM The data ROM is a mask ROM for loading various static data such as a character generator and has a capacity of 2 048 words 4 bits The data ROM is assigned to addresses 8000H to 87FFH on the data memory ...

Page 24: ...y Figure 4 1 1 shows the overall memory map of the S1C63454 and Tables 4 1 1 a d the peripheral circuits I O space memory maps 0000H 0400H 8000H 8800H F000H FF00H FFFFH RAM area Unused area Unused area Data ROM area I O memory area Display memory area Unused area Unused area Peripheral I O area Peripheral I O area F000H F24FH FF00H FF80H FFC0H FFFFH Fig 4 1 1 Memory map Note Memory is not implemen...

Page 25: ...high impedance control FOUTE 1 R02 output high impedance control PTOUT 0 TOUT output high impedance control PTOUT 1 R01 output high impedance control R00 output high impedance control FF31H R03 R02 R01 R00 R W R03 R02 R01 R00 1 1 1 1 High High High High Low Low Low Low R03 output port data FOUTE 0 Fix at 1 when FOUT is used R02 output port data PTOUT 0 Fix at 1 when TOUT is used R01 output port da...

Page 26: ... 1 0 0 All Off All On F100 F14F Normal Normal F000 F04F General purpose register LCD all OFF control LCD all ON control Display memory area selection when 1 8 duty is selected functions as a general purpose register when 1 16 1 17 duty is selected FF62H LC3 LC2 LC1 LC0 R W LC3 LC2 LC1 LC0 2 2 2 2 LCD contrast adjustment 0 4096 0 1 3276 8 2 2730 7 3 2340 6 BZFQ2 1 0 Frequency Hz 4 2048 0 5 1638 4 6...

Page 27: ...D 1 100 sec SWD7 SWD6 SWD5 SWD4 0 0 0 0 Stopwatch timer data BCD 1 10 sec R FF7EH SWD7 SWD6 SWD5 SWD4 CHSEL PTOUT CKSEL1 CKSEL0 0 0 0 0 Timer1 On OSC3 OSC3 Timer0 Off OSC1 OSC1 TOUT output channel selection TOUT output control Prescaler 1 source clock selection Prescaler 0 source clock selection R W FFC1H CHSEL PTOUT CKSEL1 CKSEL0 PTPS01 PTPS00 PTRST0 3 PTRUN0 0 0 2 0 Reset Run Invalid Stop Presca...

Page 28: ... register Programmable timer 1 Interrupt mask register Programmable timer 0 FFE7H 0 0 EISW1 EISW10 R R W 0 3 0 3 EISW1 EISW10 2 2 0 0 Enable Enable Mask Mask Unused Unused Interrupt mask register Stopwatch timer 1 Hz Interrupt mask register Stopwatch timer 10 Hz FFE3H 0 0 0 EISIF R R W 0 3 0 3 0 3 EISIF 2 2 2 0 Enable Mask Unused Unused Unused Interrupt mask register Serial I F FFE4H 0 0 0 EIK0 R ...

Page 29: ... bit binary counter and generates the non maskable interrupt when the last stage of the counter 0 25 Hz overflows Watchdog timer reset processing in the program s main routine enables detection of program overrun such as when the main routine s watchdog timer processing is bypassed Ordinarily this routine is incorporated where periodic processing takes place just as for the timer interrupt routine...

Page 30: ...hen 0 is written Disabled Reading Valid When 1 is written to the WDEN register the watchdog timer starts count operation When 0 is written the watchdog timer does not count and does not generate the interrupt NMI At initial reset this register is set to 1 WDRST Watchdog timer reset FF07H D0 Resets the watchdog timer When 1 is written Watchdog timer is reset When 0 is written No operation Reading A...

Page 31: ...ing with the S1C63454 requires high speed operation the CPU operating clock can be switched from OSC1 to OSC3 by the software To stabilize operation of the internal circuits the operating voltage VD1 must be switched according to the oscillation circuit to be used Figure 4 3 1 1 is the block diagram of this oscillation system Oscillation circuit control signal CPU clock selection signal To CPU To ...

Page 32: ...1 oscillation circuit As shown in Figure 4 3 2 1 the crystal oscillation circuit can be configured simply by connecting the crystal oscillator X tal of 32 768 kHz Typ between the OSC1 and OSC2 terminals and the trimmer capacitor CGX between the OSC1 and VSS terminals when crystal oscillation is selected The CR oscillation circuit can be configured simply by connecting the resistor RCR1 between the...

Page 33: ...OSC4 OSC3 R RDC FC To CPU and some peripheral circuits Oscillation circuit control signal To CPU and some peripheral circuits Oscillation circuit control signal a CR oscillation circuit b Ceramic oscillation circuit Fig 4 3 3 1 OSC3 oscillation circuit As shown in Figure 4 3 3 1 the CR oscillation circuit can be configured simply by connecting the resistor RCR2 between the OSC3 and OSC4 terminals ...

Page 34: ... circuit is used When the CR oscillation circuit has been selected as the OSC1 oscillation circuit by mask option 2 2 V of VD1 necessary to operate with OSC1 and OSC3 OSC1 CR oscillation operation VD1 2 2 V OSC3 operation VD1 2 2 V Since the S1C63454 fixes the VD1 voltage value at 2 2 V when the CR oscillation circuit is selected as the OSC1 oscillation circuit by mask option it is not necessary t...

Page 35: ...en selected as the OSC1 oscillation circuit by mask option setting of this register does not affect the operating voltage VD1 and the VD1 voltage is fixed at 2 2 V At initial reset this register is set to 0 OSCC OSC3 oscillation control register FF00H D2 Controls oscillation ON OFF for the OSC3 oscillation circuit When 1 is written OSC3 oscillation ON When 0 is written OSC3 oscillation OFF Reading...

Page 36: ...witching the CPU operation clock from OSC1 to OSC3 do this after a minimum of 5 msec have elapsed since the OSC3 oscillation went ON Further the oscillation stabilization time varies depending on the external oscillator characteristics and conditions of use so allow ample margin when setting the wait time 3 When switching the clock form OSC3 to OSC1 use a separate instruction for switching the OSC...

Page 37: ...he mask option suits input from the push switch key matrix and so forth When Gate direct is selected the port can be used for slide switch input and interfacing with other LSIs 4 4 2 Interrupt function All four bits of the input ports K00 K03 provide the interrupt function The conditions for issuing an interrupt can be set by the software Further whether to mask the interrupt function can be selec...

Page 38: ...upt selection register SIK03 1 SIK02 1 SIK01 1 SIK00 0 Input port 1 Initial value Interrupt generation K03 1 K02 0 K01 1 K00 0 Input comparison register KCP03 1 KCP02 0 KCP01 1 KCP00 0 With the above setting the interrupt of K00 K03 is generated under the following condition 2 K03 1 K02 0 K01 1 K00 1 3 K03 0 K02 0 K01 1 K00 1 4 K03 0 K02 1 K01 1 K00 1 Because K00 interrupt is set to disable interr...

Page 39: ... being read K00 K03 K0 port input port data FF21H Input data of the input port terminals can be read with these registers When 1 is read High level When 0 is read Low level Writing Invalid The reading is 1 when the terminal voltage of the four bits of the input ports K00 K03 goes high VDD and 0 when the voltage goes low VSS These bits are dedicated for reading so writing cannot be done SIK00 SIK03...

Page 40: ...rupt is masked This flag is reset to 0 by writing 1 After an interrupt occurs the same interrupt will occur again if the interrupt enabled state I flag 1 is set or the RETI instruction is executed unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state At initial reset ...

Page 41: ...ial reset these are all set to the general purpose output port Table 4 5 1 1 shows the setting of the output terminals by function selection Table 4 5 1 1 Function setting of output terminals Terminal name R00 R01 R02 R03 Terminal status at initial reset R00 High output R01 High output R02 High output R03 High output Special output TOUT FOUT R00 R00 R01 R01 TOUT FOUT When using the output port R02...

Page 42: ...1 shows the configuration of the R02 and R03 output ports Table 4 5 4 1 Special output Terminal R03 R02 Special output FOUT TOUT Output control register FOUTE PTOUT Data bus Register PTOUT Register R02 TOUT R02 TOUT Register FOUTE Register R03 Register R03HIZ Register R02HIZ FOUT R03 FOUT Fig 4 5 4 1 Configuration of R02 and R03 output ports At initial reset the output port data register is set to...

Page 43: ...put from the oscillation circuit or a clock that the fOSC1 clock has divided in the internal circuit and can be used to provide a clock signal to an external device To output the FOUT signal fix the R03 register at 1 and the R03HIZ register at 0 and turn the signal ON and OFF using the FOUTE register The frequency of the output clock may be selected from among 4 types shown in Table 4 5 4 2 by set...

Page 44: ...R03 output port data FOUTE 0 Fix at 1 when FOUT is used R02 output port data PTOUT 0 Fix at 1 when TOUT is used R01 output port data R00 output port data 1 Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read R00HIZ R03HIZ R0 port high impedance control register FF30H Controls high impedance output of the output port When 1 is written High impedance When 0 is writ...

Page 45: ...TOUT output OFF Reading Valid By writing 1 to the PTOUT register when the R02 register has been set to 1 and the R02HIZ register has been set to 0 the TOUT signal is output from the R02 terminal When 0 is written the R02 termi nal goes high VDD When using the R02 output port for DC output fix this register at 0 At initial reset this register is set to 0 4 5 6 Programming notes 1 When using the out...

Page 46: ...nd P12 slave mode can be selected from either normal input or with Schmitt trigger input by mask option At initial reset these terminals are all set to the I O port Table 4 6 1 1 shows the setting of the input output terminals by function selection Table 4 6 1 1 Function setting of input output terminals Terminal P00 P03 P10 P11 P12 P13 Terminal status at initial reset P00 P03 Input pull up P10 In...

Page 47: ... an input port However when the pull up explained in the following section has been set by software the input line is pulled up only during this input mode To set the output mode write 1 is to the I O control register When an I O port is set to output mode it works as an output port it outputs a high level VDD when the port output data is 1 and a low level VSS when the port output data is 0 If per...

Page 48: ...ted P12 pull up control register ESIF 0 functions as a general purpose register when SIF master is selected SCLK I pull up control register when SIF slave is selected P11 pull up control register ESIF 0 functions as a general purpose register when SIF is selected P10 pull up control register ESIF 0 SIN pull up control register when SIF is selected FF46H P13 P12 P11 P10 R W P13 P12 P11 P10 2 2 2 2 ...

Page 49: ...l goes high VDD and when 0 is written the terminal goes low VSS Port data can be written also in the input mode When reading data When 1 is read High level When 0 is read Low level The terminal voltage level of the I O port is read out When the I O port is in the input mode the voltage level being input to the port terminal can be read out in the output mode the register value can be read When the...

Page 50: ...ode is set to enable in 1 bit units The pull up resistor is included into the ports selected by the mask option By writing 1 to the pull up control register the corresponding I O ports are pulled up during input mode while writing 0 turns the pull up function OFF At initial reset these registers are all set to 1 so the pull up function is set to ON The pull up control registers of the ports in whi...

Page 51: ...including VC3 Either the internal generated voltages or external voltages used for the LCD drive voltage can be selected by the mask option Turning the LCD system voltage circuit ON or OFF is controlled with the LPWR register This control is also necessary when supplying the voltage from outside When LPWR is set to 1 the LCD system voltage circuit outputs the LCD drive voltages VC1 VC5 to the LCD ...

Page 52: ...uit of external power for LCD driving when power is supplied externally 4 7 4 LCD display control ON OFF and switching of duty 1 Display ON OFF control The S1C63454 incorporates the ALON and ALOFF registers to blink display When 1 is written to ALON all the dots go ON and when 1 is written to ALOFF all the dots go OFF At such a time an ON waveform or an OFF waveform is output from SEG terminals Wh...

Page 53: ...m for 1 4 bias and 1 5 bias VC5 VC4 VC2 VC3 VC1 VSS VC5 VC4 VC2 VC3 VC1 VSS VC5 VC4 VC2 VC3 VC1 VSS VC5 VC4 VC2 VC3 VC1 VSS VC5 VC4 VC2 VC3 VC1 VSS Drive duty 1 8 1 16 1 17 0 0 0 1 1 1 2 2 2 3 3 3 7 15 16 Frame signal 0 0 0 1 1 1 2 2 2 3 3 3 7 15 16 32 Hz COM0 COM1 COM2 SEG0 SEG1 When fOSC1 32 768 kHz LPAGE 0 Fig 4 7 4 1 Drive waveform for 1 4 bias ...

Page 54: ... COM2 SEG0 SEG1 VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS 1 8 1 16 1 17 0 0 0 1 1 1 2 2 2 3 3 3 7 15 16 0 0 0 1 1 1 2 2 2 3 3 3 7 15 16 LPAGE 0 Drive duty Frame signal When fOSC1 32 768 kHz Fig 4 7 4 2 Drive waveform for 1 5 bias ...

Page 55: ...2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 F006H F007H F106H F107H F206H SEG39 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 F04EH F04FH F14EH F14FH F24EH 1 16 duty 1 17 duty Data bit a When 1 17 or 1 16 duty is selected COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 Unused SEG0 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 F000H LPAGE 0 LPAGE 1 F001H F1...

Page 56: ...F0FFH F150H F1FFH F201H F203H F24FH is made the operation is not guaranteed 4 7 6 LCD contrast adjustment In the S1C63454 the LCD contrast can be adjusted by the software It is realized by controlling the voltages VC1 VC2 VC4 and VC5 output from the LCD system voltage circuit When these voltages are supplied to the externally expanded LCD driver the expanded LCD contrast is adjusted at the same ti...

Page 57: ...COM3 COM7 D2 COM2 COM6 COM2 COM6 COM2 COM6 COM2 COM6 D1 COM1 COM5 COM1 COM5 COM1 COM5 COM1 COM5 D0 COM0 COM4 COM0 COM4 COM0 COM4 COM0 COM4 SEG0 SEG0 SEG1 SEG1 SEG2 SEG38 SEG39 SEG39 Not implemented COM0 COM7 F100H F101H F102H F103H F104H F14DH F14EH F14FH F150H F1FFH D3 COM11 COM15 COM11 COM15 COM11 COM15 COM11 COM15 D2 COM10 COM14 COM10 COM14 COM10 COM14 COM10 COM14 0 Unused area Always 0 No Oper...

Page 58: ...used COM0 COM7 COM0 COM15 COM0 COM16 Maximum segment number 320 40 8 640 40 16 680 40 17 At initial reset this register is set to 0 ALON LCD all ON control register FF61H D1 Displays the all LCD dots ON When 1 is written All LCD dots displayed When 0 is written Normal display Reading Valid By writing 1 to the ALON register all the LCD dots goes ON and when 0 is written it returns to normal display...

Page 59: ...d as a general purpose register At initial reset this register is set to 0 LC3 LC0 LCD contrast adjustment register FF62H Adjusts the LCD contrast LC3 LC0 0000B light LC3 LC0 1111B dark At room temperature use setting number 7 or 8 as standard When the LCD drive voltage is supplied from outside by the mask option selection this adjustment becomes invalid At initial reset LC0 LC3 are undefined 4 7 ...

Page 60: ...t be used for the clock function 4 8 2 Data reading and hold function The 8 bits timer data are allocated to the address FF79H and FF7AH FF79H D0 TM0 128 Hz D1 TM1 64 Hz D2 TM2 32 Hz D3 TM3 16 Hz FF7AH D0 TM4 8 Hz D1 TM5 4 Hz D2 TM6 2 Hz D3 TM7 1 Hz Since the clock timer data has been allocated to two addresses a carry is generated from the low order data within the count TM0 TM3 128 16 Hz to the ...

Page 61: ...nterrupt request Bit D0 D1 D2 D3 D0 D1 D2 D3 Frequency Clock timer timing chart 128 Hz 64 Hz 32 Hz 16 Hz 8 Hz 4 Hz 2 Hz 1 Hz Fig 4 8 3 1 Timing chart of clock timer As shown in Figure 4 8 3 1 interrupt is generated at the falling edge of the frequencies 32 Hz 8 Hz 2 Hz 1 Hz At this time the corresponding interrupt factor flag IT0 IT1 IT2 IT3 is set to 1 Selection of whether to mask the separate in...

Page 62: ...nterrupt mask register Clock timer 32 Hz FFF6H IT3 IT2 IT1 IT0 R W IT3 IT2 IT1 IT0 0 0 0 0 R Yes W Reset R No W Invalid Interrupt factor flag Clock timer 1 Hz Interrupt factor flag Clock timer 2 Hz Interrupt factor flag Clock timer 8 Hz Interrupt factor flag Clock timer 32 Hz 1 Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read TM0 TM7 Timer data FF79H FF7AH The...

Page 63: ...ask the interrupt to the separate frequencies 32 Hz 8 Hz 2 Hz 1 Hz At initial reset these registers are set to 0 IT0 32 Hz interrupt factor flag FFF6H D0 IT1 8 Hz interrupt factor flag FFF6H D1 IT2 2 Hz interrupt factor flag FFF6H D2 IT3 1 Hz interrupt factor flag FFF6H D3 These flags indicate the status of the clock timer interrupt When 1 is read Interrupt has occurred When 0 is read Interrupt ha...

Page 64: ... is set or the RETI instruction is executed unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state 3 When the CR oscillation circuit is selected as the OSC1 oscillation circuit by mask option the frequen cies and times differ from the values described in this section b...

Page 65: ...ction because the oscillation frequency will be 60 kHz Typ Therefore this timer can not be used for the stopwatch function 4 9 2 Count up pattern The stopwatch timer is configured of 4 bit BCD counters SWD0 SWD3 and SWD4 SWD7 The counter SWD0 SWD3 at the stage preceding the stopwatch timer has an approximated 100 Hz signal for the input clock It counts up every 1 100 sec and generates an approxima...

Page 66: ...0 SWD3 and SWD4 SWD7 through their respective overflows can generate 10 Hz approximate 10 Hz and 1 Hz interrupts Figure 4 9 3 1 shows the timing chart for the stopwatch timer Address FF7DH 1 100sec BCD 10 Hz Interrupt request Bit D0 D1 D2 D3 Stopwatch timer SWD0 3 timing chart Address FF7EH 1 10sec BCD 1 Hz Interrupt request Bit D0 D1 D2 D3 Stopwatch timer SWD4 7 timing chart Fig 4 9 3 1 Timing ch...

Page 67: ... reset 2 Not set in the circuit 3 Constantly 0 when being read SWD0 SWD7 Stopwatch timer data FF7DH FF7EH The 1 100 sec and the 1 10 sec data BCD can be read from SWD0 SWD3 and SWD4 SWD7 respec tively These eight bits are read only and writing operations are invalid At initial reset the timer data is initialized to 00H SWRST Stopwatch timer reset FF7CH D1 When 1 is written Stopwatch timer reset Wh...

Page 68: ...0 Hz and 1 Hz stopwatch timer interrupts respectively The software can judge from these flags whether there is a stopwatch timer interrupt However even if the interrupt is masked the flags are set to 1 by the overflow of the corresponding counters These flags are reset to 0 by writing 1 to them After an interrupt occurs the same interrupt will occur again if the interrupt enabled state I flag 1 is...

Page 69: ...g a TOUT signal output from the R02 output port terminal Generating the synchronous clock source for the serial interface timer 1 underflow is used and it is possible to set the transfer rate Reload data register RLD00 RLD07 Data buffer PTD00 PTD07 PTRUN0 FCSEL PLPOL Programmable timer 0 PTPS00 PTPS01 8 bit down counter Prescaler Selector CKSEL0 Timer 0 Run Stop Clock control circuit Timer functio...

Page 70: ...while stopped and can restart counting continuing from that data The counter data can be read via the data buffers PTD00 PTD07 timer 0 and PTD10 PTD17 timer 1 in optional timing However the counter has the data hold function the same as the clock timer that holds the high order data when the low order data is read in order to prevent the borrowing operation between low and high order reading there...

Page 71: ...tion Circuit for the control and notes of the OSC3 oscillation circuit At initial reset the OSC3 oscillation circuit is set in the OFF state 2 Selection of prescaler division ratio Select the division ratio for each prescaler from among 4 types This selection is done using the prescaler division ratio selection registers PTPS00 PTPS01 timer 0 and PTPS10 PTPS11 timer 1 Table 4 10 3 1 shows the corr...

Page 72: ... terminal Programmable clocks can be supplied to external devices Figure 4 10 5 2 shows the configuration of the output port R02 Data bus Register PTOUT Register R02 TOUT R02 TOUT Register R02HIZ Fig 4 10 5 2 Configuration of R02 The output of a TOUT signal is controlled by the PTOUT register When 1 is written to the PTOUT register the TOUT signal is output from the R02 output port terminal and wh...

Page 73: ... timer 1 into RUN state PTRUN 1 It is not necessary to control with the PTOUT register PTRUN1 Timer 1 underflow Source clock for serial I F Fig 4 10 6 1 Synchronous clock of serial interface A setting value for the RLD1X register according to a transfer rate is calculated by the following expres sion RLD1X fosc 2 bps division ratio of the prescaler 1 fosc Oscillation frequency OSC1 OSC3 bps Transf...

Page 74: ...data low order 4 bits LSB R W FFC4H RLD03 RLD02 RLD01 RLD00 RLD07 RLD06 RLD05 RLD04 0 0 0 0 MSB Programmable timer 0 reload data high order 4 bits LSB R W FFC5H RLD07 RLD06 RLD05 RLD04 RLD13 RLD12 RLD11 RLD10 0 0 0 0 MSB Programmable timer 1 reload data low order 4 bits LSB R W FFC6H RLD13 RLD12 RLD11 RLD10 RLD17 RLD16 RLD15 RLD14 0 0 0 0 MSB Programmable timer 1 reload data high order 4 bits LSB ...

Page 75: ...ts the division ratio of the prescaler Two bits of PTPS00 and PTPS01 are the prescaler division ratio selection register for timer 0 and two bits of PTPS10 and PTPS11 are for timer 1 The prescaler division ratios that can be set by these registers are shown in Table 4 10 7 2 Table 4 10 7 2 Selection of prescaler division ratio PTPS11 PTPS01 1 1 0 0 PTPS10 PTPS00 1 0 1 0 Prescaler division ratio So...

Page 76: ... invalid At initial reset these counter data are set to 00H PTRST0 Timer 0 reset reload FFC2H D1 PTRST1 Timer 1 reset reload FFC3H D1 Resets the timer and presets reload data to the counter When 1 is written Reset When 0 is written No operation Reading Always 0 By writing 1 to PTRST0 the reload data in the reload register PLD00 PLD07 is preset to the counter in timer 0 Similarly the reload data in...

Page 77: ... registers are used to select whether to mask the programmable timer interrupt or not When 1 is written Enabled When 0 is written Masked Reading Valid Timer 0 and timer 1 interrupts can be masked individually by the interrupt mask registers EIPT0 timer 0 and EIPT1 timer 1 At initial reset these registers are set to 0 IPT0 Timer 0 interrupt factor flag FFF2H D0 IPT1 Timer 1 interrupt factor flag FF...

Page 78: ... TOUT signal is generated asynchronously from the PTOUT register a hazard within 1 2 cycle is generated when the signal is turned ON and OFF by setting the register 4 When the OSC3 oscillation clock is selected for the clock source it is necessary to turn the OSC3 oscillation ON prior to using the programmable timer However the OSC3 oscillation circuit requires a time at least 5 msec from turning ...

Page 79: ...rial input output Also when the serial interface is used at slave mode SRDY signal which indicates whether or not the serial interface is available to transmit or receive can be output to the SRDY terminal SD0 SD7 SIN P10 SCLK or SCLK P12 SCS0 SCS1 Output latch Serial I F interrupt control circuit Interrupt request SOUT P11 SRDY or SRDY P13 SCTRG Serial I F activating circuit fOSC1 Serial clock co...

Page 80: ...ot be built in if positive polarity is selected In the following explanation it is assumed that negative polarity SCLK SRDY has been selected 4 11 3 Master mode and slave mode of serial interface The serial interface of the S1C63454 has two types of operation mode master mode and slave mode The master mode uses an internal clock as the synchronous clock for the built in shift register and outputs ...

Page 81: ...and SD4 SD7 FF73H and writing 1 to SCTRG bit FF70H D1 it synchronizes with the synchronous clock and the serial data is output to the SOUT P11 terminal The synchronous clock used here is as follows in the master mode internal clock which is output to the SCLK P12 terminal while in the slave mode external clock which is input from the SCLK P12 terminal Shift timing of serial data is as follows When...

Page 82: ...om data registers SD0 SD7 by software 3 Serial data input output permutation The S1C63454 allows the input output permutation of serial data to be selected by the SDP register FF71H D3 as to either LSB first or MSB first The block diagram showing input output permutation in case of LSB first and MSB first is provided in Figure 4 11 4 1 The SDP register should be set before setting data to SD0 SD7 ...

Page 83: ...ve mode SCTRG W SCTRG R SCLK SIN 8 bit shift register SOUT ISIF SRDY Slave mode b When SCPS 0 Fig 4 11 4 2 Serial interface timing chart when synchronous clock is negative polarity SCLK SCTRG W SCTRG R SCLK SIN 8 bit shift register SOUT ISIF SRDY Slave mode SCTRG W SCTRG R SCLK SIN 8 bit shift register SOUT ISIF SRDY Slave mode b When SCPS 0 Fig 4 11 4 3 Serial interface timing chart when synchron...

Page 84: ... R W SDP SCPS SCS1 SCS0 0 0 0 0 MSB first LSB first Serial I F data input output permutation Serial I F clock phase selection Negative polarity mask option Positive polarity mask option Serial I F clock mode selection FF70H 0 0 SCTRG ESIF R R W 0 3 0 3 SCTRG ESIF 2 2 0 0 Trigger Run SIF Invalid Stop I O Unused Unused Serial I F clock trigger writing Serial I F clock status reading Serial I F enabl...

Page 85: ...al clock When the programmable timer is selected the signal that is generated by dividing the underflow signal of the programmable timer timer 1 in 1 2 is used as the synchronous clock In this case the program mable timer must be controlled before operating the serial interface Refer to Section 4 10 Programmable Timer for the control of the programmable timer At initial reset external clock is sel...

Page 86: ...o input the external clock after the trigger When reading When 1 is read RUN during input output the synchronous clock When 0 is read STOP the synchronous clock stops Writing Invalid When this bit is read it indicates the status of serial interface clock After 1 is written to SCTRG this value is latched till serial interface clock stops 8 clock counts There fore if 1 is read it indicates that the ...

Page 87: ...to 0 4 11 6 Programming notes 1 Perform data writing reading to the data registers SD0 SD7 only while the serial interface is not running i e the synchronous clock is neither being input or output 2 As a trigger condition it is required that data writing or reading on data registers SD0 SD7 be performed prior to writing 1 to SCTRG The internal circuit of the serial interface is initiated through d...

Page 88: ...ound generator Note The buzzer signal is generated by dividing the OSC1 oscillation clock Since the frequencies and times that are described in this section are the values in the case of crystal oscillation 32 768 kHz Typ they differ when CR oscillation 60 kHz Typ is selected 4 12 2 Mask option Polarity of the BZ signal output from the BZ terminal can be selected as either positive polarity or neg...

Page 89: ...7 2340 6 2048 0 1638 4 1365 3 1170 3 BZFQ0 0 1 0 1 0 1 0 1 BZFQ1 0 0 1 1 0 0 1 1 BZFQ2 0 0 0 0 1 1 1 1 The buzzer sound level is changed by controlling the duty ratio of the buzzer signal The duty ratio can be selected from among the 8 types shown in Table 4 12 4 2 according to the setting of the buzzer duty selection registers BDTY0 BDTY2 Table 4 12 4 2 Duty ratio setting BDTY0 0 1 0 1 0 1 0 1 BD...

Page 90: ...n 0 has been written it is not added When a buzzer signal output is begun writing 1 into BZE after setting ENON the duty ratio shifts to level 1 maximum and changes in stages to level 8 When attenuated down to level 8 minimum it is retained at that level The duty ratio can be returned to maximum by writing 1 into register ENRST during output of a envelope attached buzzer signal The envelope attenu...

Page 91: ...BZSHT is 1 the one shot output circuit is in operation during one shot output and when it is 0 it shows that the circuit is in the ready outputtable status In addition it can also terminate one shot output prior to the elapsing of the set time This is done by writing a 1 into the one shot buzzer stop BZSTP In this case as well the buzzer signal goes OFF in synchronization with the 256 Hz signal Wh...

Page 92: ...ZSHT SHTPW R W R W 0 3 BZSTP 3 BZSHT SHTPW 2 0 0 0 Stop Trigger Busy 125 msec Invalid Invalid Ready 31 25 msec Unused 1 shot buzzer stop writing 1 shot buzzer trigger writing 1 shot buzzer status reading 1 shot buzzer pulse width setting 1 Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read BZE BZ output control register FF6CH D0 Controls the buzzer BZ signal out...

Page 93: ...No operation Reading Always 0 Writing 1 into ENRST resets envelope and the duty ratio becomes maximum If an envelope has not been added ENON 0 and if no buzzer signal is being output the reset becomes invalid Writing 0 is also invalid This bit is dedicated for writing and is always 0 for reading ENON Envelope ON OFF control register FF6CH D1 Controls the addition of an envelope onto the buzzer sig...

Page 94: ...t time extension When reading When 1 is read BUSY When 0 is read READY During reading BZSHT shows the operation status of the one shot output circuit During one shot output BZSHT becomes 1 and the output goes OFF it shifts to 0 At initial reset this bit is set to 0 BZSTP One shot buzzer stop FF6DH D2 Stops the one shot buzzer output When 1 is written Stop When 0 is written No operation Reading Alw...

Page 95: ...ting Also the interrupt mask register is not provided However it is possible to not generate NMI since software can stop the watchdog timer operation Figure 4 13 1 shows the configuration of the interrupt circuit Note After an initial reset all the interrupts including NMI are masked until both the stack pointers SP1 and SP2 are set with the software Be sure to set the SP1 and SP2 in the initializ...

Page 96: ... EIT0 ISW1 EISW1 ISW10 EISW10 IPT0 EIPT0 IPT1 EIPT1 Interrupt vector generation circuit Program counter low order 4 bits INT interrupt request NMI interrupt request Watchdog timer Interrupt factor flag Interrupt mask register Input comparison register Interrupt selection register Interrupt flag ISIF EISIF K00 KCP00 SIK00 K01 KCP01 SIK01 K02 KCP02 SIK02 K03 KCP03 SIK03 IK0 EIK0 ...

Page 97: ...errupt factor flag is provided Table 4 13 1 1 Interrupt factors Interrupt factor Programmable timer 1 counter 0 Programmable timer 0 counter 0 Serial interface 8 bit data input output completion K00 K03 input falling edge or rising edge Clock timer 1 Hz falling edge Clock timer 2 Hz falling edge Clock timer 8 Hz falling edge Clock timer 32 Hz falling edge Stopwatch timer 1 Hz Stopwatch timer 10 Hz...

Page 98: ... FFE6H D0 FFE7H D1 FFE7H D0 Interrupt mask register 4 13 3 Interrupt vector When an interrupt request is input to the CPU the CPU begins interrupt processing After the program being executed is terminated the interrupt processing is executed in the following order 1 The content of the flag register is evacuated then the I flag is reset 2 The address data value of program counter of the program to ...

Page 99: ...able Mask Mask Unused Unused Interrupt mask register Stopwatch timer 1 Hz Interrupt mask register Stopwatch timer 10 Hz FFE3H 0 0 0 EISIF R R W 0 3 0 3 0 3 EISIF 2 2 2 0 Enable Mask Unused Unused Unused Interrupt mask register Serial I F FFE4H 0 0 0 EIK0 R R W 0 3 0 3 0 3 EIK0 2 2 2 0 Enable Mask Unused Unused Unused Interrupt mask register K00 K03 FFF6H IT3 IT2 IT1 IT0 R W IT3 IT2 IT1 IT0 0 0 0 0...

Page 100: ... FFF7H D1 D0 Refer to Section 4 9 Stopwatch Timer 4 13 5 Programming notes 1 The interrupt factor flags are set when the interrupt condition is established even if the interrupt mask registers are set to 0 2 After an interrupt occurs the same interrupt will occur again if the interrupt enabled state I flag 1 is set or the RETI instruction is executed unless the interrupt factor flag is reset There...

Page 101: ...on system voltage regulator LCD system voltage circuit Control register HALT instruction CLKCHG OSCC VDC LPWR Refer to Chapter 7 Electrical Characteristics for current consumption Below are the circuit statuses at initial reset CPU Operating status CPU operating frequency Low speed side CLKCHG 0 OSC3 oscillation circuit is in OFF status OSCC 0 Oscillation system voltage regulator Low speed side 1 ...

Page 102: ...rther if either SP1 or SP2 is re set when both are set already the interrupts including NMI are masked again until the other is re set Therefore the settings of SP1 and SP2 must be done as a pair Watchdog timer 1 When the watchdog timer is being used the software must reset it within 3 second cycles 2 Because the watchdog timer is set in operation state by initial reset set the watchdog timer to d...

Page 103: ...e time constant of the pull up resistor and input gate capaci tance Hence when fetching input ports set an appropriate wait time Particular care needs to be taken of the key scan during key matrix configuration Make this waiting time the amount of time or more calculated by the following expression 10 C R C terminal capacitance 5 pF parasitic capacitance pF R pull up resistance 330 kΩ LCD driver 1...

Page 104: ...t is set in the OFF state 5 The counter mode selection register EVCNT should be set to 0 when timer 0 is used as a down counter Otherwise it will cause malfunction Serial interface 1 Perform data writing reading to the data registers SD0 SD7 only while the serial interface is halted i e the synchronous clock is neither being input or output 2 As a trigger condition it is required that data writing...

Page 105: ...pt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state 3 After an initial reset all the interrupts including NMI are masked until both the stack pointers SP1 and SP2 are set with the software Be sure to set the SP1 and SP2 in the initialize routine Further when re setting the stack poin...

Page 106: ...D drive voltage is supplied from outside the IC 2 When connecting between the VDD and VSS terminals with a bypass capacitor the terminals should be connected as short as possible VDD VSS Bypass capacitor connection example VDD VSS 3 Components which are connected to the VD1 and VC1 VC5 terminals such as capacitors and resistors should be connected in the shortest line In particular the VC1 VC5 vol...

Page 107: ... that shields the IC from visible radiation 3 As well as the face of the IC shield the back and side too Arrangement of Signal Lines In order to prevent generation of electromagnetic induction noise caused by mutual inductance do not arrange a large current signal line near the circuits that are sensitive to noise such as the oscillation unit When a signal line is parallel with a high speed line i...

Page 108: ...panel 40 17 1 Crystal oscillation 2 CR oscillation 3 Ceramic oscillation CGC VREF TEST V V V V V C1 C2 C3 C4 C5 BZ Piezo Coil Input I O Output X tal CGX RCR1 CR CGC CDC RCR2 C1 C8 C9 CP CRES Crystal oscillator Trimmer capacitor Resistor for OSC1 CR oscillation Ceramic oscillator Gate capacitor Drain capacitor Resistor for OSC3 CR oscillation Capacitor Capacitor Capacitor RESET terminal capacitor 3...

Page 109: ... VD1 0 3 10 20 to 70 65 to 150 260 C 10sec lead section 250 Unit V V V mA C C mW The permissible total output current is the sum total of the current average current that simultaneously flows from the output pin or is drawn in In case of plastic package 7 2 Recommended Operating Conditions Item Supply voltage Oscillation frequency Ta 20 to 70 C Symbol VDD fOSC1 fOSC3 Unit V V V kHz kHz kHz kHz Max...

Page 110: ...0 13 VOH2 0 9 VDD BZ VOL1 0 1 VDD R00 03 P00 03 P10 13 VOL2 0 1 VDD BZ VOH3 VC5 0 05V COM0 16 VOL3 VSS 0 05V VOH4 VC5 0 05V SEG0 39 VOL4 VSS 0 05V Item High level input voltage 1 High level input voltage 2 Low level input voltage 1 Low level input voltage 2 High level input current Low level input current 1 Low level input current 2 High level output current 1 High level output current 2 Low level...

Page 111: ...een VSS and VC1 LC0 3 1 without panel load LC0 3 2 LC0 3 3 LC0 3 4 LC0 3 5 LC0 3 6 LC0 3 7 LC0 3 8 LC0 3 9 LC0 3 10 LC0 3 11 LC0 3 12 LC0 3 13 LC0 3 14 LC0 3 15 Connect 1 MΩ load resistor between VSS and VC2 without panel load Connect 1 MΩ load resistor between VSS and VC4 without panel load Connect 1 MΩ load resistor between VSS and VC5 without panel load Connect 1 MΩ load resistor between VSS an...

Page 112: ...HALT 60 kHz CR oscillation LCD power OFF 2 During HALT 60 kHz CR oscillation LCD power ON VC1 standard 2 During HALT 60 kHz CR oscillation LCD power ON VC2 standard 2 During execution 32 kHz crystal oscillation LCD power ON VC1 standard 1 2 During execution 60 kHz CR oscillation LCD power ON VC1 standard 2 During execution 2 MHz ceramic oscillation LCD power ON VC1 standard During execution 4 MHz ...

Page 113: ...1 and VSS Unless otherwise specified VDD 3 0V VSS 0V fOSC1 32 768kHz CG 25pF CD built in Ta 20 to 70 C OSC1 CR oscillation circuit Item Oscillation frequency dispersion Oscillation start voltage Oscillation start time Oscillation stop voltage Symbol fOSC1 Vsta tsta Vstp Unit V ms V Max 30 3 Typ 60kHz Min 30 2 2 2 2 Condition VDD VDD 2 2 to 6 4V VDD Unless otherwise specified VDD 3 0V VSS 0V RCR1 5...

Page 114: ...2 to 6 4 V VSS 0 V Ta 25 C Typ value 20k 30k 40k 50k 60k 70k 80k 90k 100k 110k 120k 300k 400k 500k 600k 700k 800k 900k 1M OSC3 CR oscillation frequency resistance characteristic The oscillation characteristics change depending on the conditions components used board pattern etc Use the following characteristics as reference values and evaluate the characteristics on the actual product 30k 20k 40k ...

Page 115: ... 1 MHz Condition VDD 3 0V VSS 0V Ta 25 C VIH1 0 8VDD VIL1 0 2VDD VOH 0 8VDD VOL 0 2VDD Clock synchronous slave mode During 32 kHz operation Item Transmitting data output delay time Receiving data input set up time Receiving data input hold time Symbol tssd tsss tssh Unit µs µs µs Max 10 Typ Min 10 5 Condition VDD 3 0V VSS 0V Ta 25 C VIH1 0 8VDD VIL1 0 2VDD VOH 0 8VDD VOL 0 2VDD During 1 MHz operat...

Page 116: ... System clock switching VDC OSCC CLKCHG 2 5 msec min 5 msec min 1 instruction execution time or longer Note When the OSC1 oscillation circuit has been selected as the CR oscillation circuit it is not neces sary to set the VDC register Whether the VDC register value is 1 or 0 does not matter ...

Page 117: ...8 PACKAGE CHAPTER 8 PACKAGE 8 1 Plastic Package QFP15 100pin Unit mm The dimensions are subject to change without notice 14 0 1 16 0 4 51 75 14 0 1 16 0 4 26 50 INDEX 0 18 25 1 100 76 1 0 1 0 1 1 2 max 1 0 5 0 2 0 10 0 125 0 05 0 025 0 5 0 1 0 05 ...

Page 118: ...HNICAL MANUAL CHAPTER 8 PACKAGE 8 2 Ceramic Package for Test Samples QFP15 100pin Unit mm 13 97 0 15 12 00Typ 17 00 0 30 0 50 0 20 1 25 26 50 75 51 100 76 GLASS CERAMIC 0 50Typ 0 82 0 30 2 54Max 0 76 0 13 0 95 0 08 0 38 0 08 ...

Page 119: ...CAL MANUAL EPSON 109 CHAPTER 9 PAD LAYOUT CHAPTER 9 PAD LAYOUT 9 1 Diagram of Pad Layout Chip thickness 400 µm Pad opening 85 µm X Y 0 0 4 19 mm 3 94 mm 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 Die No ...

Page 120: ...061 1 176 1 291 1 406 No 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 Pad name SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 X 1 468 1 343 1 228 1 113 998 883 768 653 538 423 308 193 78 37 152 267 382 497 612 727 842 957 1 072 1 187 1 302 1 417 Y 1 845 1 84...

Page 121: ...ral Circuit Board included with the product Please refer to the user s manual provided with your ICE for detailed information on its functions and method of use A 1 Names and Functions of Each Part The following explains the names and functions of each part of the board S5U1C63000P VSVD VC5 PRG CLK RESET IOSEL2 XC4062XLA D E 1 3 VLCD CN3 connector Unused CN2 connector Unused CN1 connector 3 4 10 1...

Page 122: ... 15 2 4 6 8 10 12 14 16 LED 5 CR oscillation frequency adjusting control When OSC1 and OSC3 respectively are set for a CR oscillation circuit and a CR ceramic oscillation circuit by a mask option this control allows you to adjust the oscillation frequency The oscillation frequency can be adjusted in the range of approx 20 kHz to 500 kHz for OSC1 and approx 100 kHz to 8 MHz for OSC3 Note that the a...

Page 123: ...this board will remain incomplete and the debugger may not be able to start when you power on the ICE once again In this case temporarily power off the ICE and set CLK to the 32K position and the PRG switch to the Prog position then switch on power for the ICE once again This should allow the debugger to start up allowing you to download circuit data After downloading the circuit data temporarily ...

Page 124: ...connect the S5U1C63000P to the target system To connect this board S5U1C63000P to the target system use the I O connecting cables supplied with the board 80 pin 40 pin 2 flat type Take care when handling the connectors since they conduct electrical power VDD 3 3 V CN1 1 40 pin I O connection cable To target board CN1 2 40 pin mark Fig A 2 1 Connecting the S5U1C63000P to the target system ...

Page 125: ... connected Cannot be connected Cannot be connected Cannot be connected Cannot be connected BZ VSS VSS No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 40 pin CN1 2 connector Pin name VDD 3 3 V VDD 3 3 V R00 R01 R02 R03 R10 1 R11 1 R12 1 R13 1 VSS VSS R20 1 R21 1 R22 1 R23 1 Cannot be connected Cannot be connected Cannot be connected ...

Page 126: ...fore this board and the target system cannot be interfaced with voltages exceeding VDD by setting the output ports for open drain mode Pull up resistance value The pull up resistance values on this board are set to 220 kΩ which differ from those for the actual IC For the resistance values on the actual IC refer to the technical manual for the S1C63404 454 455 458 466 P466 Note that when using pull...

Page 127: ...n circuit when the voltage regulating circuit for high speed operation remains idle Access to undefined address space If any undefined space in the S1C63404 454 455 458 466 P466 s internal ROM RAM or I O is accessed for data read or write operations the read written value is indeterminate Additionally it is important to remain aware that indeterminate state differs between this board and the actua...

Page 128: ...8 466 P466 when setting the appropriate wait time for the actual IC I O port input circuit 2 When this tool is used for the S1C63454 455 This board does not support Schmitt trigger input for the I O port that is available by mask option in the actual IC If the target system needs Schmitt trigger input ports it should be configured with an external circuit LCD drive circuit 3 When this tool is used...

Page 129: ...llès SPAIN Phone 34 93 544 2490 Fax 34 93 544 2491 ASIA EPSON CHINA CO LTD 23F Beijing Silver Tower 2 North RD DongSanHuan ChaoYang District Beijing CHINA Phone 64106655 Fax 64107319 SHANGHAI BRANCH 4F Bldg 27 No 69 Gui Jing Road Caohejing Shanghai CHINA Phone 21 6485 5552 Fax 21 6485 0775 EPSON HONG KONG LTD 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Phone 852 2585 4600 Fax 852 2827 43...

Page 130: ...ursuit of Saving Technology Epson electronic devices Our lineup of semiconductors liquid crystal displays and quartz devices assists in creating the products of our customers dreams Epson IS energy savings ...

Page 131: ...http www epsondevice com Technical Manual S1C63454 EPSON Electronic Devices Website ELECTRONIC DEVICES MARKETING DIVISION First issue March 1998 Printed October 2001 in Japan A L M ...

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