S1C63454 TECHNICAL MANUAL
EPSON
23
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.3.3 OSC3 oscillation circuit
The S1C63454 has built-in the OSC3 oscillation circuit that generates the CPU's sub-clock (Max. 4 MHz)
for high speed operation and the source clock for peripheral circuits needing a high speed clock (pro-
grammable timer, FOUT output). The mask option enables selection of either the CR or ceramic oscilla-
tion circuit. When CR oscillation is selected, only a resistance is required as an external element. When
ceramic oscillation is selected, a ceramic oscillator and two capacitors (gate and drain capacitance) are
required.
Figure 4.3.3.1 is the block diagram of the OSC3 oscillation circuit.
C
CR
OSC3
OSC4
R
CR2
V
SS
C
GC
C
DC
Ceramic
OSC4
OSC3
R
R
DC
FC
To CPU
(and some peripheral circuits)
Oscillation circuit control signal
To CPU
(and some peripheral circuits)
Oscillation circuit control signal
(a) CR oscillation circuit
(b) Ceramic oscillation circuit
Fig. 4.3.3.1 OSC3 oscillation circuit
As shown in Figure 4.3.3.1, the CR oscillation circuit can be configured simply by connecting the resistor
R
CR2
between the OSC3 and OSC4 terminals when CR oscillation is selected. See Chapter 7, "Electrical
Characteristics" for resistance value of R
CR2
.
When ceramic oscillation is selected, the ceramic oscillation circuit can be configured by connecting the
ceramic oscillator (Max. 4 MHz) between the OSC3 and OSC4 terminals, capacitor C
GC
between the OSC3
and OSC4 terminals, and capacitor C
DC
between the OSC4 and V
SS
terminals. For both C
GC
and C
DC
,
connect capacitors that are about 30 pF. To reduce current consumption of the OSC3 oscillation circuit,
oscillation can be stopped by the software (OSCC register).
