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EPSON
S1C63358 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
ESOUT: SOUT enable/disable control register (FF70H•D2)
Enables output of the SOUT signal.
When "1" is written: Enabled
When "0" is written: Disabled
Reading: Valid
When "1" is written to the ESOUT register, the SOUT terminal can output serial data. When "0" is written,
the SOUT terminal goes high-impedance status.
At initial reset, this register is set to "0".
PUL10: SIN (P10) pull-up control register (FF45H•D0)
PUL12: SCLK (P12) pull-up control register (FF45H•D2)
Sets the pull-up of the SIN terminal and the SCLK terminals (in the slave mode).
When "1" is written: Pull-up ON
When "0" is written: Pull-up OFF
Reading: Valid
Sets the pull-up resistor built into the SIN (P10) and SCLK (P12) terminals to ON or OFF. (Pull-up resistor
is only built in the port selected by mask option.)
SCLK pull-up is effective only in the slave mode. In the master mode, the PUL12 register can be used as a
general purpose register.
At initial reset, these registers are set to "1" and pull-up goes ON.
SCS1, SCS0: Clock mode selection register (FF71H•D0, D1)
Selects the synchronous clock (SCLK) for the serial interface.
Table 4.12.5.2 Synchronous clock selection
SCS1
1
1
0
0
SCS0
1
0
1
0
Mode
Master mode
Slave mode
Synchronous clock
OSC1
OSC1 /2
Programmable timer
External clock
Synchronous clock (SCLK) is selected from among the above 4 types: 3 types of internal clock and
external clock.
When the programmable timer is selected, the signal that is generated by dividing the underflow signal
of the programmable timer (timer 1) in 1/2 is used as the synchronous clock. In this case, the program-
mable timer must be controlled before operating the serial interface. Refer to Section 4.11, "Programmable
Timer" for the control of the programmable timer.
At initial reset, external clock is selected.
SCPS: Clock phase selection register (FF71H•D2)
Selects the timing for reading in the serial data input from the SIN (P10) terminal.
• When negative polarity is selected:
When "1" is written: Falling edge of SCLK
When "0" is written: Rising edge of SCLK
Reading: Valid
• When positive polarity is selected:
When "1" is written: Rising edge of SCLK
When "0" is written: Falling edge of SCLK
Reading: Valid
Select whether the fetching for the serial input data to registers (SD0–SD7) at the rising edge or falling
edge of the synchronous signal.