Epson S1C63358 Technical Manual Download

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EPSON

S1C63358 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

(5) Timing chart

The S1C63358 serial interface timing charts are shown in Figures 4.12.4.2 and 4.12.4.3.

SCTRG (W)

SCTRG (R)

SCLK

SIN

8-bit shift register

SOUT

ISIF

SRDY (Slave mode)

SCTRG (W)

SCTRG (R)

SCLK

SIN

8-bit shift register

SOUT

ISIF

SRDY (Slave mode)

(b) When SCPS = "0"

Fig. 4.12.4.2 Serial interface timing chart (when synchronous clock is negative polarity SCLK)

SCTRG (W)

SCTRG (R)

SCLK

SIN

8-bit shift register

SOUT

ISIF

SRDY (Slave mode)

SCTRG (W)

SCTRG (R)

SCLK

SIN

8-bit shift register

SOUT

ISIF

SRDY (Slave mode)

(b) When SCPS = "0"

Fig. 4.12.4.3 Serial interface timing chart (when synchronous clock is positive polarity SCLK)

(a) When SCPS = "1"

Summary of Contents for S1C63358

Page 1: ...Technical Manual CMOS 4 BIT SINGLE CHIP MICROCOMPUTER S1C63358 Technical Hardware S1C63358 MF1022 04 ...

Page 2: ...uiring high level reliability such as medical products Moreover no license to any intellectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party This material or portions thereof may contain technology or the subject relating to...

Page 3: ...put comparison register Control of LCD display and drive waveform 1 Display ON OFF control Programming notes Summary of Notes by Function Programmable timer Contents The sentence was revised A part of contents was deleted 6 was added 5 was added Chapter 4 5 Revisions and Additions for this manual ...

Page 4: ......

Page 5: ...Specification Package D die form F QFP Model number Model name C microcomputer digital products Product classification S1 semiconductor Development tools S5U1 C 63000 A1 1 Packing specifications 00 standard packing Version 1 Version 1 Tool type Hx ICE Ex EVA board Px Peripheral board Wx Flash ROM writer for the microcomputer Xx ROM writer peripheral board Cx C compiler package Ax Assembler package...

Page 6: ......

Page 7: ..._________________ 14 3 1 CPU 14 3 2 Code ROM 14 3 3 RAM 14 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION__________________________ 16 4 1 Memory Map 16 4 2 Setting of Power Supply and Operating Mode 23 4 2 1 Control of supply voltage 23 4 2 2 Operating mode for the oscillation system voltage regulator and the internal operating voltage 23 4 2 3 Operating mode for LCD system voltage circuit 24 4 2 4 ...

Page 8: ...ng notes 63 4 9 Clock Timer 64 4 9 1 Configuration of clock timer 64 4 9 2 Data reading and hold function 64 4 9 3 Interrupt function 65 4 9 4 I O memory of clock timer 66 4 9 5 Programming notes 68 4 10 A D Converter 69 4 10 1 Characteristics and configuration of A D converter 69 4 10 2 Terminal configuration of A D converter 69 4 10 3 Mask option 70 4 10 4 Control of A D converter 70 4 10 5 Inte...

Page 9: ...and HALT 106 4 15 1 Interrupt factor 108 4 15 2 Interrupt mask 109 4 15 3 Interrupt vector 109 4 15 4 I O memory of interrupt 110 4 15 5 Programming notes 112 CHAPTER 5 SUMMARY OF NOTES ______________________________________ 113 5 1 Notes for Low Current Consumption 113 5 2 Summary of Notes by Function 114 5 3 Precautions on Mounting 119 CHAPTER 6 BASIC EXTERNAL WIRING DIAGRAM ____________________...

Page 10: ...C63000P MANUAL PERIPHERAL CIRCUIT BOARD FOR S1C63158 358 P366 __________ 133 A 1 Names and Functions of Each Part 133 A 2 Connecting to the Target System 136 A 3 Usage Precautions 138 A 3 1 Operational precautions 138 A 3 2 Differences with the actual IC 138 ...

Page 11: ... operation at 4 MHz Min 0 5 µsec ROM capacity Code ROM 8 192 words 13 bits RAM capacity Data memory 512 words 4 bits Display memory 32 words 4 bits Input port 9 bits 8 bits Pull up resistors may be supplemented 1 1 bit Input interrupt for key position sensing by A D Output port 12 bits It is possible to switch the 2 bits to special output 2 I O port 20 bits It is possible to switch the 4 bits to s...

Page 12: ...µA Package QFP15 100pin plastic 1 Can be selected with mask option 2 Can be selected with software 1 2 Block Diagram OSC1 OSC2 OSC3 OSC4 COM0 3 SEG0 31 VDD VC1 3 CA CB VD1 VSS BZ R00 R03 R10 R13 R20 R23 K00 K03 K10 K13 K20 TEST AVDD AVSS AVREF RESET P00 P03 P10 P13 P20 P23 P30 P33 P40 P43 Core CPU S1C63000 ROM 8 192 words 13 bits System Reset Control Interrupt Generator OSC RAM 512 words 4 bits LC...

Page 13: ...No 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Name SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 Name N C N C COM0 COM1 COM2 COM3 CB CA VC3 VC2 VC1 VSS OSC1 OSC2 VD1 OSC3 OSC4 VDD RESET TEST AVREF AVDD AVSS N C N C Name N C P43 P42 P41 P40 P33 P32 P31 P30 P23 P22 P2...

Page 14: ...ted by mask option Ceramic or CR oscillation output pin selected by mask option Input port Input port Input port with control I O port I O port switching to serial I F input output is possible by software I O port I O port I O port can be used as A D input Output port Output port Output port switching to TOUT output is possible by software Output port switching to FOUT output is possible by softwa...

Page 15: ... Section 2 2 2 Simultaneous low input to terminals K00 K03 for details 3 Input port pull up resistor The mask option is used to select whether the pull up resistor is supplemented to the input ports or not It is possible to select for each bit of the input ports Refer to Section 4 5 3 Mask option for details 4 Output specification of the output port Either complementary output or N channel open dr...

Page 16: ...n circuit Either CR oscillation circuit or ceramic oscillation circuit can be selected as the OSC3 oscillation circuit Refer to Section 4 4 3 OSC3 oscillation circuit for details Mask option list The following is the option list for the S1C63358 Multiple selections are available in each option item as indicated in the option list Refer to Chapter 4 Peripheral Circuits and Operation to select the s...

Page 17: ...O PORT PULL UP RESISTOR P1x 1 With Resistor 2 Gate Direct P20 1 With Resistor 2 Gate Direct P21 1 With Resistor 2 Gate Direct P22 1 With Resistor 2 Gate Direct P23 1 With Resistor 2 Gate Direct P30 1 With Resistor 2 Gate Direct P31 1 With Resistor 2 Gate Direct P32 1 With Resistor 2 Gate Direct P33 1 With Resistor 2 Gate Direct P40 1 With Resistor 2 Gate Direct P41 1 With Resistor 2 Gate Direct P4...

Page 18: ...Power supply circuits Circuit Oscillation and internal circuits LCD driver Oscillation system voltage regulator A D converter Power supply circuit Oscillation system voltage regulator LCD system voltage circuit Supply voltage VDD or LCD system voltage circuit VC2 Analog supply voltage AVDD and supply voltage VDD or LCD system voltage circuit VC2 Output voltage VD1 VC1 VC3 VDD or VC2 AVDD and VDD o...

Page 19: ...voltage regulator built in and generates two other voltages by boosting the voltage of VC1 VC2 2 VC1 VC3 3 VC1 When 1 2 bias is selected by mask option VC2 becomes the same level with VC1 VC2 VC1 VC3 2 VC1 1 4 V or more voltage is needed to generate the voltage VC1 Therefore when operating with 0 9 1 4 V the LCD display contrast will become worse Refer to Chapter 7 Electrical Characteristics for v...

Page 20: ...mode 2 1 4 Voltage source for A D converter 1 Booster mode VC2 mode The A D converter operates with 0 9 3 6 V supply voltage However a minimum 1 6 V supply voltage is need for the A D converter maximum error within 5 LSB Therefore when operating with a 1 6 V or less of supply voltage VDD switch the power supply source to drive the A D converter circuit with the VC2 2 Normal mode In this mode the A...

Page 21: ...ET Initial reset can be executed externally by setting the reset terminal to a low level VSS After that the initial reset is released by setting the reset terminal to a high level VDD and the CPU starts operation The reset input signal is maintained by the RS latch and becomes the internal initial reset signal The RS latch is designed to be released by a 2 Hz signal high that is divided by the OSC...

Page 22: ...tial reset if that time is the defined time 1 to 2 sec or more If using this function make sure that the specified ports do not go low at the same time during ordinary operation 2 2 3 Internal register at initial resetting Initial reset initializes the CPU as shown in Table 2 2 3 1 The registers and flags which are not initialized by initial reset should be initial ized in the program if necessary...

Page 23: ...cial output TOUT FOUT TOUT FOUT Serial I F Master Slave SIN I SIN I SOUT O SOUT O SCLK O SCLK I SRDY O Terminal name R00 R01 R02 R03 R10 R13 R20 R23 P00 P03 P10 P11 P12 P13 P20 P23 P30 P33 P40 P41 P42 P43 Terminal status at initial reset R00 High output R01 High output R02 High output R03 High output R10 R13 High output R20 R23 High output P00 P03 Input Pull up P10 Input Pull up P11 Input Pull up ...

Page 24: ... 0000H to 01FFH on the data memory map Addresses 0100H to 01FFH are 4 bit 16 bit data accessible areas and in other areas it is only possible to access 4 bit data When programming keep the following points in mind 1 Part of the RAM area is used as a stack area for subroutine call and register evacuation so pay attention not to overlap the data area and stack area 2 The S1C63000 core CPU handles th...

Page 25: ...tack area for 16 bit data SP1 Interrupts use 4 words for PC evacuation in the stack area for 16 bit data SP1 and 1 word for F register evacua tion in the stack area for 4 bit data 0000H 00FFH 0100H 01FFH 4 bits 4 bit access area SP2 stack area 4 16 bit access area SP1 stack area Fig 3 3 1 Configuration of data RAM ...

Page 26: ... of 512 word RAM 32 word display memory and 76 word peripheral I O memory area Figure 4 1 1 shows the overall memory map of the S1C63358 and Tables 4 1 1 a f the peripheral circuits I O space memory maps 0000H 0200H F000H FF00H FFFFH RAM area Unused area I O memory area Display memory area Unused area Peripheral I O area F000H F020H FF00H FFFFH Fig 4 1 1 Memory map Note Memory is not implemented i...

Page 27: ...used CPU operating voltage switch 1 35 V OSC1 2 25 V OSC3 FF20H SIK03 SIK02 SIK01 SIK00 R W SIK03 SIK02 SIK01 SIK00 0 0 0 0 Enable Enable Enable Enable Disable Disable Disable Disable K00 K03 interrupt selection register FF21H K03 K02 K01 K00 R K03 K02 K01 K00 2 2 2 2 High High High High Low Low Low Low K00 K03 input port data FF22H KCP03 KCP02 KCP01 KCP00 R W KCP03 KCP02 KCP01 KCP00 1 1 1 1 K00 K...

Page 28: ...gister FF41H PUL03 PUL02 PUL01 PUL00 R W PUL03 PUL02 PUL01 PUL00 1 1 1 1 On On On On Off Off Off Off P00 P03 pull up control register FF42H P03 P02 P01 P00 R W P03 P02 P01 P00 2 2 2 2 High High High High Low Low Low Low P00 P03 I O port data Unused Unused Unused K20 input port data Unused Unused Unused K20 input comparison register FF29H 0 0 0 K20 R 0 3 0 3 0 3 K20 2 2 2 2 High Low FF2AH 0 0 0 KCP...

Page 29: ...functions as a general purpose register when SIF is selected P10 pull up control register ESIF 0 SIN pull up control register when SIF is selected FF46H P13 P12 P11 P10 R W P13 P12 P11 P10 2 2 2 2 High High High High Low Low Low Low P13 I O port data functions as a general purpose register when SIF slave is selected P12 I O port data ESIF 0 functions as a general purpose register when SIF is selec...

Page 30: ...k timer data 2 Hz Clock timer data 4 Hz Clock timer data 8 Hz 0 Slave 2 OSC1 2 1 PT 3 OSC1 SCS1 0 Clock SCS1 0 Clock FF71H SDP SCPS SCS1 SCS0 R W SDP SCPS SCS1 SCS0 0 0 0 0 MSB first LSB first Serial I F data input output permutation Serial I F clock phase selection Negative polarity mask option Positive polarity mask option Serial I F clock mode selection FF70H 0 ESOUT SCTRG ESIF R R W 0 3 ESOUT ...

Page 31: ...a high order 4 bits LSB R W FFC7H RLD17 RLD16 RLD15 RLD14 PTD03 PTD02 PTD01 PTD00 0 0 0 0 MSB Programmable timer 0 data low order 4 bits LSB R FFC8H PTD03 PTD02 PTD01 PTD00 PTD07 PTD06 PTD05 PTD04 0 0 0 0 MSB Programmable timer 0 data high order 4 bits LSB R FFC9H PTD07 PTD06 PTD05 PTD04 PTD13 PTD12 PTD11 PTD10 0 0 0 0 MSB Programmable timer 1 data low order 4 bits LSB R FFCAH PTD13 PTD12 PTD11 PT...

Page 32: ...used Unused Interrupt mask register K00 K03 FFE5H 0 0 EIK2 EIK1 R R W 0 3 0 3 EIK2 EIK1 2 2 0 0 Enable Enable Mask Mask Unused Unused Interrupt mask register K20 Interrupt mask register K10 K13 FFF6H IT3 IT2 IT1 IT0 R W IT3 IT2 IT1 IT0 0 0 0 0 R Yes W Reset R No W Invalid Interrupt factor flag Clock timer 1 Hz Interrupt factor flag Clock timer 2 Hz Interrupt factor flag Clock timer 8 Hz Interrupt ...

Page 33: ... 1 Turn the LCD booster ON set LPWR 1 2 Maintain 100 msec or more 3 Set 1 in the VDSEL for the oscillation system voltage regulator or VADSEL for the A D converter voltage circuit VC2 mode Normal mode 1 Set 0 in the VDSEL or VADSEL 2 Turn the LCD booster OFF set LPWR 0 if LCD is unused Note If the power supply voltage is out of the specified voltage range for an operating mode do not switch into t...

Page 34: ... set in the VC2 mode The OSC3 oscillation circuit can be used in this voltage range 4 2 3 Operating mode for LCD system voltage circuit The LCD system voltage circuit generates the voltage VC1 VC2 and VC3 for driving the LCD The LCD system voltage circuit generates VC1 by the regulator and boosts it to generate the other 2 voltages Turning the LCD power supply circuit ON OFF can be controlled usin...

Page 35: ...erate VC2 by LCD booster to drive the internal power supply circuit When 1 is written to the LPWR register the voltage booster generates VC2 When 0 is written boostering is not performed When the power supply voltage is 1 4 V or more do not use the voltage VC2 for oscillation system voltage regulator However this does not apply when the battery voltage falls by heavy load such as driving a buzzer ...

Page 36: ...ltage software control is necessary Set the oscillation system voltage regulator to the VC2 mode When 1 4 V or more power supply voltage is used don t set the oscillation system voltage regulator into the VC2 mode 2 When using the A D converter with a 0 9 1 6 V power supply voltage software control is necessary Set the A D converter voltage circuit to the VC2 mode When 1 6 V or more power supply v...

Page 37: ... bit binary counter and generates the non maskable interrupt when the last stage of the counter 0 25 Hz overflows Watchdog timer reset processing in the program s main routine enables detection of program overrun such as when the main routine s watchdog timer processing is bypassed Ordinarily this routine is incorporated where periodic processing takes place just as for the timer interrupt routine...

Page 38: ...hen 0 is written Disabled Reading Valid When 1 is written to the WDEN register the watchdog timer starts count operation When 0 is written the watchdog timer does not count and does not generate the interrupt NMI At initial reset this register is set to 1 WDRST Watchdog timer reset FF07H D0 Resets the watchdog timer When 1 is written Watchdog timer is reset When 0 is written No operation Reading A...

Page 39: ...ing with the S1C63358 requires high speed operation the CPU operating clock can be switched from OSC1 to OSC3 by the software To stabilize operation of the internal circuits the operating voltage VD1 must be switched according to the oscillation circuit to be used Figure 4 4 1 1 is the block diagram of this oscillation system Oscillation circuit control signal CPU clock selection signal To CPU To ...

Page 40: ...crystal oscillator X tal of 32 768 kHz Typ between the OSC1 and OSC2 terminals and the trimmer capacitor CGX between the OSC1 and VSS terminals when crystal oscillation is selected The CR oscillation circuit can be configured simply by connecting the resistor RCR1 between the OSC1 and OSC2 terminals when CR oscillation is selected See Chapter 7 Electrical Characteristics for resis tance value of R...

Page 41: ...circuit b Ceramic oscillation circuit Fig 4 4 3 1 OSC3 oscillation circuit As shown in Figure 4 4 3 1 the CR oscillation circuit can be configured simply by connecting the resistor RCR2 between the OSC3 and OSC4 terminals when CR oscillation is selected See Chapter 7 Electrical Characteristics for resistance value of RCR2 When ceramic oscillation is selected the ceramic oscillation circuit can be ...

Page 42: ...ing procedure using the software first switch the operating mode if necessary and the operating voltage VD1 turn the OSC3 oscillation ON after waiting 2 5 msec or more for the above operation to stabilize switch the clock after waiting 5 msec or more for oscillation stabilization When switching from OSC3 to OSC1 turn the OSC3 oscillation circuit OFF after switching the clock then set the operating...

Page 43: ...en selected as the OSC1 oscillation circuit by mask option When 1 is written 2 25 V for OSC3 operation When 0 is written 1 35 V for OSC1 operation Reading Valid When switching the CPU system clock the operating voltage VD1 should also be switched according to the clock When switching from OSC1 to OSC3 first set VD1 to 2 25 V After that maintain 2 5 msec or more and then turn the OSC3 oscillation O...

Page 44: ...hen switching from OSC3 to OSC1 set VD1 after switching to OSC1 and turning the OSC3 oscilla tion OFF However when the CR oscillation circuit has been selected as the OSC1 oscillation circuit it is not necessary to set VD1 2 It takes at least 5 msec from the time the OSC3 oscillation circuit goes ON until the oscillation stabi lizes Consequently when switching the CPU operation clock from OSC1 to ...

Page 45: ... 5 1 1 shows the configuration of input port K00 K03 K10 K13 Figure 4 5 1 2 shows the configuration of input port K20 Kxx Mask option Address VDD Interrupt request Data bus VSS Fig 4 5 1 1 Configuration of input port K00 K03 K10 K13 K20 Mask option VDD Interrupt request Data bus VSS Key sense ON OFF control Address Address Fig 4 5 1 2 Configuration of input port K20 Selection of With pull up resis...

Page 46: ...the configuration of K00 K03 K10 K13 interrupt circuit Figure 4 5 2 2 shows the configuration of K20 interrupt circuit Data bus Input comparison register KCP00 10 K00 10 Interrupt request Interrupt selection register SIK00 10 Address Address Address Address Interrupt factor flag IK0 1 K01 11 K02 12 K03 13 Interrupt mask register EIK0 1 Address Fig 4 5 2 1 Input interrupt circuit configuration K00 ...

Page 47: ...3 shows an example of an interrupt for K00 K03 Interrupt selection register SIK03 1 SIK02 1 SIK01 1 SIK00 0 Input port 1 Initial value Interrupt generation K03 1 K02 0 K01 1 K00 0 Input comparison register KCP03 1 KCP02 0 KCP01 1 KCP00 0 With the above setting the interrupt of K00 K03 is generated under the following condition 2 K03 1 K02 0 K01 1 K00 1 3 K03 0 K02 0 K01 1 K00 1 4 K03 0 K02 1 K01 1...

Page 48: ... FF26H KCP13 KCP12 KCP11 KCP10 R W KCP13 KCP12 KCP11 KCP10 1 1 1 1 K10 K13 input comparison register FFE4H 0 0 0 EIK0 R R W 0 3 0 3 0 3 EIK0 2 2 2 0 Enable Mask Unused Unused Unused Interrupt mask register K00 K03 FFF4H 0 0 0 IK0 R R W 0 3 0 3 0 3 IK0 2 2 2 0 R Yes W Reset R No W Invalid Unused Unused Unused Interrupt factor flag K00 K03 FF28H 0 0 0 SIK20 R R W 0 3 0 3 0 3 SIK20 2 2 2 0 Enable Dis...

Page 49: ...t comparison register FF22H KCP10 KCP13 K1 port input comparison register FF26H KCP20 K20 port input comparison register FF2AH D0 Interrupt conditions for terminals K00 K03 K10 K13 and K20 can be set with these registers When 1 is written Falling edge When 0 is written Rising edge Reading Valid The interrupt conditions can be set for the rising or falling edge of input for each of the nine bits K0...

Page 50: ...e I flag 1 is set or the RETI instruction is executed unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state At initial reset these flags are set to 0 SENON K20 port key sense ON OFF control FF2BH D0 Controls the key sense function When 1 is written On When 0 is writte...

Page 51: ...aveform is delayed on account of the time constant of the pull up resistor and input gate capacitance Hence when fetching input ports set an appropriate waiting time Particular care needs to be taken of the key scan during key matrix configuration Make this waiting time the amount of time or more calculated by the following expression 10 C R C terminal capacitance 5 pF parasitic capacitance pF R p...

Page 52: ...tput port Table 4 6 1 1 shows the setting of the output terminals by function selection Table 4 6 1 1 Function setting of output terminals Terminal name R00 R01 R02 R03 R10 R13 R20 R23 Terminal status at initial reset R00 High output R01 High output R02 High output R03 High output R10 R13 High output R20 R23 High output Special output TOUT FOUT R00 R00 R01 R01 TOUT FOUT R10 R13 R10 R13 R20 R23 R20...

Page 53: ...ftware Figure 4 6 4 1 shows the configuration of the R02 and R03 output ports Table 4 6 4 1 Special output Terminal R03 R02 Special output FOUT TOUT Output control register FOUTE PTOUT Data bus Register PTOUT Register R02 TOUT R02 TOUT Register FOUTE Register R03 Register R03HIZ Register R02HIZ FOUT R03 FOUT Fig 4 6 4 1 Configuration of R02 and R03 output ports At initial reset the output port dat...

Page 54: ...put from the oscillation circuit or a clock that the fOSC1 clock has divided in the internal circuit and can be used to provide a clock signal to an external device To output the FOUT signal fix the R03 register at 1 and the R03HIZ register at 0 and turn the signal ON and OFF using the FOUTE register The frequency of the output clock may be selected from among 4 types shown in Table 4 6 4 2 by set...

Page 55: ... Low R03 output port data FOUTE 0 Fix at 1 when FOUT is used R02 output port data PTOUT 0 Fix at 1 when TOUT is used R01 output port data R00 output port data FF32H 0 0 0 R1HIZ R R W 0 3 0 3 0 3 R1HIZ 2 2 2 0 High Z Output Unused Unused Unused R1 output high impedance control FF33H R13 R12 R11 R10 R W R13 R12 R11 R10 1 1 1 1 High High High High Low Low Low Low R10 R13 output port data FF34H 0 0 0 ...

Page 56: ...UT output OFF Reading Valid By writing 1 to the FOUTE register when the R03 register has been set to 1 and the R03HIZ register has been set to 0 an FOUT signal is output from the R03 terminal When 0 is written the R03 terminal goes high VDD When using the R03 output port for DC output fix this register at 0 At initial reset this register is set to 0 FOFQ0 FOFQ1 FOUT frequency selection register FF...

Page 57: ... VSS level the same as the DC output if 0 is written to the R02 and R03 registers when the special output has been selected Be aware that the output terminal shifts into high impedance status when 1 is written to the high impedance control register R02HIZ R03HIZ 2 A hazard may occur when the FOUT signal and the TOUT signal are turned ON and OFF 3 When fOSC3 is selected for the FOUT signal frequenc...

Page 58: ...input output terminals by function selection Table 4 7 1 1 Function setting of input output terminals Terminal name P00 P03 P10 P11 P12 P13 P20 P23 P30 P33 P40 P41 P42 P43 Terminal status at initial reset P00 P03 Input pull up P10 Input pull up P11 Input pull up P12 Input pull up P13 Input pull up P20 P23 Input pull up P30 P33 Input pull up P40 Input Pull up P41 Input Pull up P42 Input Pull up P43...

Page 59: ...ver when the pull up explained in the following section has been set by software the input line is pulled up only during this input mode To set the output mode write 1 is to the I O control register When an I O port is set to output mode it works as an output port it outputs a high level VDD when the port output data is 1 and a low level VSS when the port output data is 0 If perform the read out i...

Page 60: ...ected P10 I O port data ESIF 0 functions as a general purpose register when SIF is selected FF41H PUL03 PUL02 PUL01 PUL00 R W PUL03 PUL02 PUL01 PUL00 1 1 1 1 On On On On Off Off Off Off P00 P03 pull up control register FF42H P03 P02 P01 P00 R W P03 P02 P01 P00 2 2 2 2 High High High High Low Low Low Low P00 P03 I O port data FF45H PUL13 PUL12 PUL11 PUL10 R W PUL13 PUL12 PUL11 PUL10 1 1 1 1 On On O...

Page 61: ...Low Low P43 I O port data PAD3 0 functions as a general purpose register when A D is enabled P42 I O port data PAD2 0 functions as a general purpose register when A D is enabled P41 I O port data PAD1 0 functions as a general purpose register when A D is enabled P40 I O port data PAD0 0 functions as a general purpose register when A D is enabled PAD3 PAD2 PAD1 PAD0 0 0 0 0 Enable Enable Enable Ena...

Page 62: ...de When reading data When 1 is read High level When 0 is read Low level The terminal voltage level of the I O port is read out When the I O port is in the input mode the voltage level being input to the port terminal can be read out in the output mode the register value can be read When the terminal voltage is high VDD the port data that can be read is 1 and when the terminal voltage is low VSS th...

Page 63: ... When 1 is written Pull up ON When 0 is written Pull up OFF Reading Valid The built in pull up resistor which is turned ON during input mode is set to enable in 1 bit units The pull up resistor is included into the ports selected by the mask option By writing 1 to the pull up control register the corresponding I O ports are pulled up during input mode while writing 0 turns the pull up function OFF...

Page 64: ...When LPWR is set to 0 VC1 VC3 becomes VSS level In this case all outputs from the COM terminals and SEG terminals go to VSS level To display the LCD the LCD drive power must be ON by previously setting LPWR to 1 SEG output ports that are set for DC output by the mask option operate same as the output R port regardless of the power ON OFF control 4 8 3 Control of LCD display and drive waveform 1 Di...

Page 65: ...R 4 PERIPHERAL CIRCUITS AND OPERATION LCD Driver LCD lighting status COM0 COM1 COM2 COM3 Not lit Lit COM0 COM1 COM2 COM3 SEG 0 31 SEG0 31 VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS Frame frequency Fig 4 8 3 1 Dynamic drive waveform for 1 4 duty 1 3 bias ...

Page 66: ...it Lit COM0 COM1 COM2 COM3 SEG 0 31 SEG0 31 VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS Frame frequency Fig 4 8 3 2 Dynamic drive waveform for 1 3 duty 1 3 bias LCD lighting status COM0 COM1 Not lit Lit COM0 COM1 COM2 COM3 SEG 0 31 SEG0 31 VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS Frame frequency Fig 4 8 3 3 Dynamic drive waveform for 1 2 duty 1 3 bias ...

Page 67: ...ER 4 PERIPHERAL CIRCUITS AND OPERATION LCD Driver LCD lighting status COM0 COM1 COM2 COM3 Not lit Lit COM0 COM1 COM2 COM3 SEG 0 31 SEG0 31 VC3 VC1 C2 VSS VC3 VC1 C2 VSS Frame frequency Fig 4 8 3 4 Dynamic drive waveform for 1 4 duty 1 2 bias ...

Page 68: ... lit Lit COM0 COM1 COM2 COM3 SEG 0 31 SEG0 31 VC3 VC1 C2 VSS VC3 VC1 C2 VSS Frame frequency Fig 4 8 3 5 Dynamic drive waveform for 1 3 duty 1 2 bias LCD lighting status COM0 COM1 Not lit Lit COM0 COM1 COM2 COM3 SEG 0 31 SEG0 31 VC3 VC1 C2 VSS VC3 VC1 C2 VSS Frame frequency Fig 4 8 3 6 Dynamic drive waveform for 1 2 duty 1 2 bias ...

Page 69: ...uts a static ON waveform When all the COM0 to COM3 bits are set to 0 the SEG terminal outputs a dynamic OFF waveform Figures 4 8 3 7 and 4 8 3 8 show the static drive waveform for 1 3 bias and 1 2 bias COM 0 3 Frame frequency LCD lighting status COM0 COM1 COM2 COM3 SEG0 31 VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS Not lit Lit SEG 0 31 Fig 4 8 3 7 Static drive waveform 1 3 bias SEG 0 31 COM 0...

Page 70: ... F00CH F00DH Address d p d p D3 c g c g D2 b f b f D1 a e a e D0 Data Display memory allocation SEG10 SEG11 SEG12 F00A D0 a F00A D1 b F00D D1 f F00B D1 f F00B D2 g F00A D2 c F00B D0 e F00A D3 d F00B D3 p Pin address allocation Common 0 Common 1 Common 2 Fig 4 8 4 1 Segment allocation At initial reset the contents of the display memory are undefined therefore it is necessary to initialize by softwa...

Page 71: ...mask option external elements can be minimized because one or two external capacitors for VC1 to VC3 are not necessary However when the LCD system voltage regurator is not used the display quality of the LCD panel when the supply voltage fluctuates drops is inferior to when the LCD system voltage regurator is used Figure 4 8 4 2 shows the external elements when the the LCD system voltage regurator...

Page 72: ... F F000 F010 Display memory 32 words 4 bits R W Fig 4 8 5 1 Display memory map LPWR LCD power control ON OFF register FF60H D0 Turns the LCD system voltage circuit ON and OFF When 1 is written ON When 0 is written OFF Reading Valid When 1 is written to the LPWR register the LCD system voltage circuit goes ON and generates the LCD drive voltage When 0 is written all the LCD drive voltages go to VSS...

Page 73: ...g 1 to the ALOFF register all the LCD segments goes OFF and when 0 is written it returns to normal display This function outputs an OFF waveform to the SEG terminals and does not affect the content of the display memory At initial reset this register is set to 1 Display memory F000H F01FH The LCD segments are lit or turned off depending on this data When 1 is written Lit When 0 is written Not lit ...

Page 74: ...t be used for the clock function 4 9 2 Data reading and hold function The 8 bits timer data are allocated to the address FF79H and FF7AH FF79H D0 TM0 128 Hz D1 TM1 64 Hz D2 TM2 32 Hz D3 TM3 16 Hz FF7AH D0 TM4 8 Hz D1 TM5 4 Hz D2 TM6 2 Hz D3 TM7 1 Hz Since the clock timer data has been allocated to two addresses a carry is generated from the low order data within the count TM0 TM3 128 16 Hz to the ...

Page 75: ...nterrupt request Bit D0 D1 D2 D3 D0 D1 D2 D3 frequency Clock timer timing chart 128 Hz 64 Hz 32 Hz 16 Hz 8 Hz 4 Hz 2 Hz 1 Hz Fig 4 9 3 1 Timing chart of clock timer As shown in Figure 4 9 3 1 interrupt is generated at the falling edge of the frequencies 16 Hz 8 Hz 2 Hz 1 Hz At this time the corresponding interrupt factor flag IT0 IT1 IT2 IT3 is set to 1 Selection of whether to mask the separate in...

Page 76: ...nterrupt mask register Clock timer 16 Hz FFF6H IT3 IT2 IT1 IT0 R W IT3 IT2 IT1 IT0 0 0 0 0 R Yes W Reset R No W Invalid Interrupt factor flag Clock timer 1 Hz Interrupt factor flag Clock timer 2 Hz Interrupt factor flag Clock timer 8 Hz Interrupt factor flag Clock timer 16 Hz 1 Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read TM0 TM7 Timer data FF79H FF7AH The...

Page 77: ...ask the interrupt to the separate frequencies 16 Hz 8 Hz 2 Hz 1 Hz At initial reset these registers are set to 0 IT0 16 Hz interrupt factor flag FFF6H D0 IT1 8 Hz interrupt factor flag FFF6H D1 IT2 2 Hz interrupt factor flag FFF6H D2 IT3 1 Hz interrupt factor flag FFF6H D3 These flags indicate the status of the clock timer interrupt When 1 is read Interrupt has occurred When 0 is read Interrupt ha...

Page 78: ... is set or the RETI instruction is executed unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state 3 When the CR oscillation circuit is selected as the OSC1 oscillation circuit by mask option the frequen cies and times differ from the values described in this section b...

Page 79: ...D3 P43 Analog mux AVDD AVREF AVSS 8 bit D A converter SAR Converted data Clock selector Comparator Sample hold Control circuit fOSC1 or fOSC3 2 Data bus Interrupt circuit OSC3 oscillator fOSC3 2 OSC1 oscillator fOSC1 1 2 Fig 4 10 1 1 Configuration of A D converter 4 10 2 Terminal configuration of A D converter The terminals used with the A D converter are as follows AVDD AVSS power supply terminal...

Page 80: ...h terminal goes to a high impedance Table 4 10 4 1 Correspondence between A D input terminal and PAD register Terminal P40 AD0 P41 AD1 P42 AD2 P43 AD3 A D input enable disable PAD0 PAD1 PAD2 PAD3 Comment 2 Setting of input clock The clock selector selects the A D conversion clock from OSC1 or OSC3 according to the value written in the ADCLK register Table 4 10 4 2 shows the input clock selection w...

Page 81: ...art converting of the analog signal input to the AD1 terminal The built in sample hold circuit starts sampling of the analog input specified from tAD after writing When the sampling is completed the held analog input voltage is converted into a 8 bit digital value in successive approximation architecture The conversion result is loaded into the ADDR ADDR0 ADDR7 register ADDR0 is the LSB and ADDR7 ...

Page 82: ...sion has completed Figure 4 10 5 1 shows the configuration of the A D converter interrupt circuit The A D converter sets the interrupt factor flag IAD to 1 immediately after storing the conversion result to the ADDR register At this time if the interrupt mask register EIAD is 1 an interrupt is generated to the CPU By setting the EIAD register to 0 the interrupt to the CPU can be disabled However t...

Page 83: ...tart OSC3 Invalid OSC1 W R W FFD0H ADRUN ADCLK CHS1 CHS0 A D Run Off control A D input clock selection A D input channel selection 0 P40 1 P41 3 P43 2 P42 CHS1 0 Input channel FF01H VADSEL VDSEL 0 0 R W R VADSEL VDSEL 0 3 0 3 0 0 2 2 VC2 VC2 VDD VDD Power source selection for A D converter Power supply selection for oscillation system voltage regulator Unused Unused 1 Initial value at initial rese...

Page 84: ...en 0 is written the A D converter operates with VDD In this case VDD must be 1 6 V or more At initial reset this register is set to 0 VDD ADRUN A D conversion control FFD0H D3 Starts an A D conversion When 1 is written Start When 0 is written No operation Reading Invalid When 1 is written to ADRUN the A D converter starts A D conversion of the channel selected by the CHS register and stores the co...

Page 85: ...r befor starting A D conversion 2 The A D converter can operate by inputting the clock from the clock selector Therefore it is neces sary to select the clock source and to turn the clock output on before starting A D conversion Fur thermore it is also necessary that the OSC3 oscillation circuit is operating when using the OSC3 clock 3 When using the OSC3 clock as the A D conversion clock do not st...

Page 86: ...al Generating an interrupt Generating a TOUT signal output from the R02 output port terminal Generating the synchronous clock source for the serial interface timer 1 underflow is used and it is possible to set the transfer rate Reload data register RLD00 RLD07 Data buffer PTD00 PTD07 Input port K13 PTRUN0 FCSEL PLPOL Programmable timer 0 PTPS00 PTPS01 8 bit down counter Prescaler Selector CKSEL0 T...

Page 87: ... counting This control RUN STOP does not affect the counter data The counter maintains its data while stopped and can restart counting continuing from that data The counter data can be read via the data buffers PTD00 PTD07 timer 0 and PTD10 PTD17 timer 1 in optional timing However the counter has the data hold function the same as the clock timer that holds the high order data when the low order d...

Page 88: ...ter EVCNT The timer 1 operates only in the timer mode and cannot be used as an event counter In the event counter mode the clock is supplied to timer 0 from outside of the IC therefore the settings of the timer 0 prescaler division ratio selection registers PTPS00 and PTPS01 and the settings of the timer 0 source clock selection register CKSEL0 become invalid Count down timing can be selected from...

Page 89: ... and CKSEL1 timer 1 when 0 is written to the register OSC1 is selected and when 1 is written OSC3 is selected When the OSC3 oscillation clock is selected for the clock source it is necessary to turn the OSC3 oscillation ON prior to using the programmable timer However the OSC3 oscillation circuit requires a time interval of several msec to several 10 msec from turning the circuit ON until the osci...

Page 90: ...hen 1 is written timer 1 is selected Figure 4 11 2 5 1 shows the TOUT signal waveform when the channel is changed Timer 0 underflow Timer 1 underflow CHSEL 0 1 TOUT output R02 Fig 4 11 2 5 1 TOUT signal waveform at channel change The TOUT signal can be output from the R02 output port terminal Programmable clocks can be supplied to external devices Figure 4 11 2 5 2 shows the configuration of the o...

Page 91: ...counter By writing 1 to the timer reset bit PTRST0 timer 0 or PTRST1 timer 1 the down counter loads the initial value set in the reload register RLD Therefore down counting is executed from the stored initial value by the input clock The register PTRUN0 timer 0 is used to control the RUN STOP for timers 0 and 1 By writing 1 to the register after presetting the reload data to the down counter the d...

Page 92: ...o the timer 0 counter mode selection register EVCNT In the event counter mode the clock is supplied to timer 0 from outside of the IC therefore the settings of the timer 0 prescaler division ratio selection registers PTPS00 and PTPS01 and the settings of the timer 0 source clock selection register CKSEL0 become invalid Count down timing can be selected from either the falling or rising edge of the...

Page 93: ...ock selection register CKSEL0 timer 0 when 0 is written to the register OSC1 is selected and when 1 is written OSC3 is selected When the OSC3 oscillation clock is selected for the clock source it is necessary to turn the OSC3 oscillation ON prior to using the programmable timer However the OSC3 oscillation circuit requires a time interval of several msec to several 10 msec from turning the circuit...

Page 94: ...n be output from the R02 output port terminal Programmable clocks can be supplied to external devices Figure 4 11 3 5 1 shows the configuration of the output port R02 Data bus Register PTOUT Register R02 TOUT R02 TOUT Register R02HIZ Fig 4 11 3 5 1 Configuration of R02 The output of a TOUT signal is controlled by the PTOUT register When 1 is written to the PTOUT register the TOUT signal is output ...

Page 95: ...tputs the clock to the serial interface by setting this 16 bit programmable timer into RUN state PTRUN0 1 It is not necessary to control with the PTOUT register PTRUN0 16 bit programmable timer underfrow Source clock for serial I F Fig 4 11 3 6 1 Synchronous clock of serial interface A setting value for the RLD1X register according to a transfer rate is calculated by the following expres sion RLD1...

Page 96: ...ble timer 1 reload data low order 4 bits LSB R W FFC6H RLD13 RLD12 RLD11 RLD10 RLD17 RLD16 RLD15 RLD14 0 0 0 0 MSB Programmable timer 1 reload data high order 4 bits LSB R W FFC7H RLD17 RLD16 RLD15 RLD14 PTD03 PTD02 PTD01 PTD00 0 0 0 0 MSB Programmable timer 0 data low order 4 bits LSB R FFC8H PTD03 PTD02 PTD01 PTD00 PTD07 PTD06 PTD05 PTD04 0 0 0 0 MSB Programmable timer 0 data high order 4 bits L...

Page 97: ... be set by these registers are shown in Table 4 11 4 2 Table 4 11 4 2 Selection of prescaler division ratio PTPS11 PTPS01 1 1 0 0 PTPS10 PTPS00 1 0 1 0 Prescaler division ratio Source clock 256 Source clock 32 Source clock 4 Source clock 1 When the event counter mode is selected to timer 0 the setting of the PTPS00 and PTPS01 becomes invalid At initial reset these registers are set to 0 EVCNT Time...

Page 98: ...lected from either the falling edge of the external clock input to the K13 input port terminal or the rising edge When 0 is written to the PLPOL register the falling edge is selected and when 1 is written the rising edge is selected Setting of this register is effective only when timer 0 is used in the event counter mode At initial reset this register is set to 0 RLD00 RLD07 Timer 0 reload data re...

Page 99: ...maintained until the counter is reset or is set in the next RUN status When STOP status changes to RUN status the data that has been maintained can be used for resuming the count Same as above the timer 1 counter is controlled by the PTRUN1 register At initial reset these registers are set to 0 CHSEL TOUT output channel selection register FFC1H D3 Selects the channel used for TOUT signal output Wh...

Page 100: ...nterrupt When 1 is read Interrupt has occurred When 0 is read Interrupt has not occurred When 1 is written Flag is reset When 0 is written Invalid The interrupt factor flags IPT0 and IPT1 correspond to timer 0 and timer 1 interrupts respectively The software can judge from these flags whether there is a programmable timer interrupt However even if the interrupt is masked the flags are set to 1 by ...

Page 101: ... to using the programmable timer However the OSC3 oscillation circuit requires a time interval of several msec to several 10 msec from turning the circuit ON until the oscillation stabilizes Therefore allow an adequate interval from turning the OSC3 oscillation circuit ON to starting the programmable timer Refer to Section 4 4 Oscillation Circuit for the control and notes of the OSC3 oscillation c...

Page 102: ... available to transmit or receive can be output to the SRDY terminal SD0 SD7 SIN P10 SCLK or SCLK P12 SCS0 SCS1 Output latch Serial I F interrupt control circuit Interrupt request SOUT P11 SRDY or SRDY P13 SCTRG Serial I F activating circuit fOSC1 Serial clock counter Serial clock selector Serial clock generator Shift register 8 bits Programmable timer 1 underflow signal SCPS ESOUT Fig 4 12 1 1 Co...

Page 103: ...planation it is assumed that negative polarity SCLK SRDY has been selected 4 12 3 Master mode and slave mode of serial interface The serial interface of the S1C63358 has two types of operation mode master mode and slave mode The master mode uses an internal clock as the synchronous clock for the built in shift register and outputs this internal clock from the SCLK P12 terminal to control the exter...

Page 104: ...and SD4 SD7 FF73H and writing 1 to SCTRG bit FF70H D1 it synchronizes with the synchronous clock and the serial data is output to the SOUT P11 terminal The synchronous clock used here is as follows in the master mode internal clock which is output to the SCLK P12 terminal while in the slave mode external clock which is input from the SCLK P12 terminal Shift timing of serial data is as follows When...

Page 105: ...om data registers SD0 SD7 by software 3 Serial data input output permutation The S1C63358 allows the input output permutation of serial data to be selected by the SDP register FF71H D3 as to either LSB first or MSB first The block diagram showing input output permutation in case of LSB first and MSB first is provided in Figure 4 12 4 1 The SDP register should be set before setting data to SD0 SD7 ...

Page 106: ...ve mode SCTRG W SCTRG R SCLK SIN 8 bit shift register SOUT ISIF SRDY Slave mode b When SCPS 0 Fig 4 12 4 2 Serial interface timing chart when synchronous clock is negative polarity SCLK SCTRG W SCTRG R SCLK SIN 8 bit shift register SOUT ISIF SRDY Slave mode SCTRG W SCTRG R SCLK SIN 8 bit shift register SOUT ISIF SRDY Slave mode b When SCPS 0 Fig 4 12 4 3 Serial interface timing chart when synchron...

Page 107: ...S0 0 0 0 0 MSB first LSB first Serial I F data input output permutation Serial I F clock phase selection Negative polarity mask option Positive polarity mask option Serial I F clock mode selection FFE3H 0 0 0 EISIF R R W 0 3 0 3 0 3 EISIF 2 2 2 0 Enable Mask Unused Unused Unused Interrupt mask register Serial I F FFF3H 0 0 0 ISIF R R W 0 3 0 3 0 3 ISIF 2 2 2 0 R Yes W Reset R No W Invalid Unused U...

Page 108: ... register FF71H D0 D1 Selects the synchronous clock SCLK for the serial interface Table 4 12 5 2 Synchronous clock selection SCS1 1 1 0 0 SCS0 1 0 1 0 Mode Master mode Slave mode Synchronous clock OSC1 OSC1 2 Programmable timer External clock Synchronous clock SCLK is selected from among the above 4 types 3 types of internal clock and external clock When the programmable timer is selected the sign...

Page 109: ...nternal circuit of the serial interface is initiated through data writ ing reading on data registers SD0 SD7 In addition be sure to enable the serial interface with the ESIF register before setting the trigger Supply trigger only once every time the serial interface is placed in the RUN state Refrain from perform ing trigger input multiple times as leads to malfunctioning Moreover when the synchro...

Page 110: ...RETI instruction is executed unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state At initial reset this flag is set to 0 4 12 6 Programming notes 1 Perform data writing reading to the data registers SD0 SD7 only while the serial interface is not running i e the synch...

Page 111: ...4 13 2 Mask option Polarity of the buzzer signal output from the BZ terminal can be selected as either positive polarity or negative polarity Figure 4 13 2 1 shows each output circuit configuration and the output waveform When positive polarity is selected the BZ terminal goes to a low VSS level when the buzzer signal is not output Select positive polarity when driving a piezo buzzer by externally...

Page 112: ...er BZON When negative polarity is selected the BZ terminal goes to a high VDD level by writing 0 to the BZON register When positive polarity is selected the BZ terminal goes to a low VSS level by writing 0 BZON register Buzzer output BZ Negative polarity Buzzer output BZ Positive polarity 1 0 0 Fig 4 13 3 1 Timing chart of buzzer signal output 2 Hz intervals can be added to the buzzer signal when ...

Page 113: ... been written a 2 Hz ON OFF interval is not added At initial reset this register is set to 0 BZFQ Buzzer frequency selection register FF64H D1 Selects the buzzer signal frequency When 1 is written 2 kHz When 0 is written 4 kHz Reading Valid When 1 is written to BZFQ the frequency is set to 2 kHz When 0 is written it is set to 4 kHz At initial reset this register is set to 0 BZON Buzzer output cont...

Page 114: ...re whether the supply voltage is normal or has dropped The criteria voltage can be set for the 16 types shown in Table 4 14 2 1 by the SVDS3 SVDS0 registers Table 4 14 2 1 Criteria voltage setting SVDS3 0 0 0 0 0 0 0 0 SVDS2 1 1 1 1 0 0 0 0 SVDS1 1 1 0 0 1 1 0 0 SVDS0 1 0 1 0 1 0 1 0 Criteria voltage V 1 60 1 40 1 30 1 25 1 20 1 15 1 10 1 05 SVDS3 1 1 1 1 1 1 1 1 SVDS2 1 1 1 1 0 0 0 0 SVDS1 1 1 0 ...

Page 115: ... control ON OFF register FF05H D0 Turns the SVD circuit ON and OFF When 1 is written SVD circuit ON When 0 is written SVD circuit OFF Reading Valid When the SVDON register is set to 1 a source voltage detection is executed by the SVD circuit As soon as SVDON is reset to 0 the result is loaded to the SVDDT latch To obtain a stable detection result the SVD circuit must be ON for at least l00 µsec At...

Page 116: ...ting Also the interrupt mask register is not provided However it is possible to not generate NMI since software can stop the watchdog timer operation Figure 4 15 1 shows the configuration of the interrupt circuit Note After an initial reset all the interrupts including NMI are masked until both the stack pointers SP1 and SP2 are set with the software Be sure to set the SP1 and SP2 in the initializ...

Page 117: ...IT1 IT0 EIT0 IAD EIAD IPT0 EIPT0 IPT1 EIPT1 Interrupt vector generation circuit Program counter low order 4 bits INT interrupt request NMI interrupt request Watchdog timer Interrupt factor flag Interrupt mask register Input comparison register Interrupt selection register Interrupt flag ISIF EISIF K00 KCP00 SIK00 K01 KCP01 SIK01 K02 KCP02 SIK02 K03 KCP03 SIK03 IK0 EIK0 Fig 4 15 1 Configuration of ...

Page 118: ... Table 4 15 1 1 Interrupt factors Interrupt factor Programmable timer 1 counter 0 Programmable timer 0 counter 0 Serial interface 8 bit data input output completion K00 K03 input falling edge or rising edge K10 K13 input falling edge or rising edge K20 input falling edge or rising edge Clock timer 1 Hz falling edge Clock timer 2 Hz falling edge Clock timer 8 Hz falling edge Clock timer 16 Hz falli...

Page 119: ...E6H D1 FFE6H D0 FFE7H D0 Interrupt mask register 4 15 3 Interrupt vector When an interrupt request is input to the CPU the CPU begins interrupt processing After the program being executed is terminated the interrupt processing is executed in the following order 1 The content of the flag register is evacuated then the I flag is reset 2 The address data value of program counter of the program to be ...

Page 120: ...ion register Unused Unused Unused K20 input comparison register FF2AH 0 0 0 KCP20 R R W 0 3 0 3 0 3 KCP20 2 2 2 1 FFE6H EIT3 EIT2 EIT1 EIT0 R W EIT3 EIT2 EIT1 EIT0 0 0 0 0 Enable Enable Enable Enable Mask Mask Mask Mask Interrupt mask register Clock timer 1 Hz Interrupt mask register Clock timer 2 Hz Interrupt mask register Clock timer 8 Hz Interrupt mask register Clock timer 16 Hz FFE2H 0 0 EIPT1...

Page 121: ...0 2 2 2 0 R Yes W Reset R No W Invalid Unused Unused Unused Interrupt factor flag K00 K03 FFF5H 0 0 IK2 IK1 R R W 0 3 0 3 IK2 IK1 2 2 0 0 R Yes W Reset R No W Invalid Unused Unused Interrupt factor flag K20 Interrupt factor flag K10 K13 1 Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read EIPT1 EIPT0 Interrupt mask registers FFE2H D1 D0 IPT1 IPT0 Interrupt facto...

Page 122: ...xecuted unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state 3 After an initial reset all the interrupts including NMI are masked until both the stack pointers SP1 and SP2 are set with the software Be sure to set the SP1 and SP2 in the initialize routine Further when...

Page 123: ... voltage regulator LCD system voltage circuit Supply voltage booster SVD circuit Control register HALT instruction CLKCHG OSCC VDC LPWR LPWR VDSEL VADSEL SVDON Refer to Chapter 7 Electrical Characteristics for current consumption Below are the circuit statuses at initial reset CPU Operating status CPU operating frequency Low speed side CLKCHG 0 OSC3 oscillation circuit is in OFF status OSCC 0 Osci...

Page 124: ...mode 1 When operating the S1C63358 with a 0 9 1 4 V power supply voltage software control is necessary Set the oscillation system voltage regulator to the VC2 mode When 1 4 V or more power supply voltage is used don t set the oscillation system voltage regulator into the VC2 mode 2 When using the A D converter with a 0 9 1 6 V power supply voltage software control is necessary Set the A D converte...

Page 125: ...and the programmable timer Therefore when the K13 terminal is set to the clock input terminal for the programmable timer take care of the interrupt setting Output port 1 When using the output port R02 R03 as the special output port fix the data register R02 R03 at 1 and the high impedance control register R02HIZ R03HIZ at 0 data output Be aware that the output terminal is fixed at a low VSS level ...

Page 126: ...which is not included in the analog input terminals set by the PAD register the PAD register can select several terminals simultaneously the A D conversion does not result in a correct converted value 7 During A D conversion do not operate the P4n terminals which are not used for analog inputs of the A D converter for input output of digital signals It affects the A D conversion precision Programm...

Page 127: ...k source of the programmable timer and the CPU is operating with the OSC3 high speed clock Serial interface 1 Perform data writing reading to the data registers SD0 SD7 only while the serial interface is not running i e the synchronous clock is neither being input or output 2 As a trigger condition it is required that data writing or reading on data registers SD0 SD7 be performed prior to writing ...

Page 128: ...pt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state 3 After an initial reset all the interrupts including NMI are masked until both the stack pointers SP1 and SP2 are set with the software Be sure to set the SP1 and SP2 in the initialize routine Further when re setting the stack poin...

Page 129: ...depending on conditions power rise time components used board pattern etc Decide the time constant of the capacitor and resistor after enough tests have been completed with the application product When the built in pull up resistor is added to the RESET terminal by mask option take into consider ation dispersion of the resistance for setting the constant In order to prevent any occurrences of unne...

Page 130: ...ion Do not arrange a high speed signal line especially near circuits that are sensitive to noise such as the oscillation unit and analog input unit P40 AD0 Large current signal line High speed signal line OSC4 OSC3 VSS Large current signal line High speed signal line Prohibited pattern Precautions for Visible Radiation when bare chip is mounted Visible radiation causes semiconductor devices to cha...

Page 131: ... COM0 COM3 LCD panel 32 4 1 Crystal oscillation 2 CR oscillation 3 Ceramic oscillation CGC BZ Input I O Output X tal CGX RCR1 CR CGC CDC RCR2 C1 C5 CP CRES Crystal oscillator Trimmer capacitor Resistor for OSC1 CR oscillation Ceramic oscillator Gate capacitor Drain capacitor Resistor for OSC3 CR oscillation Capacitor Capacitor RESET terminal capacitor 32 768 kHz CI Max 34 kΩ 5 25 pF 600 kΩ 60 kHz ...

Page 132: ...c lead section 250 Unit V V V mA C C mW The permissible total output current is the sum total of the current average current that simultaneously flows from the output pin or is drawn in In case of plastic package QFP15 100pin 7 2 Recommended Operating Conditions Item Supply voltage Oscillation frequency Ta 20 to 70 C Symbol VDD AVDD AVREF fOSC1 fOSC3 Unit V V V V V V kHz kHz kHz kHz Max 1 4 3 6 3 ...

Page 133: ...10 13 P20 23 P30 33 P40 43 VOL2 0 1 VDD BZ VOH3 VC5 0 05V COM0 3 VOL3 VSS 0 05V VOH4 VC5 0 05V SEG0 31 VOL4 VSS 0 05V VOH5 0 9 VDD SEG0 31 VOL5 0 1 VDD Item High level input voltage 1 High level input voltage 2 Low level input voltage 1 Low level input voltage 2 High level input current Low level input current 1 Low level input current 2 High level output current 1 High level output current 2 Low ...

Page 134: ...kHz Crystal oscillation Normal mode 1 60kHz CR oscillation LCD power ON 1 8MHz CR oscillation 4MHz Ceramic oscillation During execution 32 768kHz Crystal oscillation Booster mode VDD 1 2V 1 LCD power ON Item LCD drive voltage Symbol VC1 VC2 VC3 Unit V V V Max 1 15 2 VC1 0 1 3 VC1 0 1 Typ 1 05 Min 0 95 2 VC1 0 9 3 VC1 0 9 Condition Connect 1 MΩ load resistor between VSS and VC1 without panel load C...

Page 135: ...VSS Unless otherwise specified VDD 3 0V VSS 0V fOSC1 32 768kHz CG 25pF CD built in Ta 25 C OSC1 CR oscillation circuit Item Oscillation frequency dispersion Oscillation start voltage Oscillation start time Oscillation stop voltage Symbol fOSC1 Vsta tsta Vstp Unit V ms V Max 30 3 Typ 60kHz Min 30 2 3 2 3 Condition Normal mode VDD VDD 2 3 to 3 6V Normal mode VDD Unless otherwise specified VDD 3 0V V...

Page 136: ... VDD 2 3 to 3 6 V VSS 0 V Ta 25 C Typ value 20k 30k 40k 50k 60k 70k 80k 90k 100k 110k 120k 300k 400k 500k 600k 700k 800k 900k 1M OSC3 CR oscillation frequency resistance characteristic The oscillation characteristics change depending on the conditions components used board pattern etc Use the following characteristics as reference values and evaluate the characteristics on the actual product Resis...

Page 137: ...00 200 Condition VDD 3 0V VSS 0V Ta 25 C VIH1 0 8VDD VIL1 0 2VDD VOH 0 8VDD VOL 0 2VDD Clock synchronous slave mode During 32 kHz operation Item Transmitting data output delay time Receiving data input set up time Receiving data input hold time Symbol tssd tsss tssh Unit µs µs µs Max 10 Typ Min 10 5 Condition VDD 3 0V VSS 0V Ta 25 C VIH1 0 8VDD VIL1 0 2VDD VOH 0 8VDD VOL 0 2VDD During 1 MHz operat...

Page 138: ...ion circuit it is not necessary to set the VDC register Whether the VDC register value is 1 or 0 does not matter 2 5 msec min 5 msec min 1 instruction execution time or longer Supply voltage VC2 mode control during heavy load driving LPWR VDSEL VADSEL Note Heavy load ON OFF Note VADSEL is used only when it is required 100 msec min 100 msec min 1 msec min 2 sec min 1 instruction execution time or l...

Page 139: ...8 PACKAGE CHAPTER 8 PACKAGE 8 1 Plastic Package QFP15 100pin Unit mm 14 0 1 16 0 4 51 75 14 0 1 16 0 4 26 50 INDEX 0 18 25 1 100 76 1 0 1 0 1 1 2 max 1 0 5 0 2 0 10 0 125 0 05 0 025 0 5 0 1 0 05 The dimensions are subject to change without notice ...

Page 140: ...HNICAL MANUAL CHAPTER 8 PACKAGE 8 2 Ceramic Package for Test Samples QFP15 100pin Unit mm 13 97 0 15 12 00Typ 17 00 0 30 0 50 0 20 1 25 26 50 75 51 100 76 GLASS CERAMIC 0 50Typ 0 82 0 30 2 54Max 0 76 0 13 0 95 0 08 0 38 0 08 ...

Page 141: ...L MANUAL EPSON 131 CHAPTER 9 PAD LAYOUT CHAPTER 9 PAD LAYOUT 9 1 Diagram of Pad Layout X Y 0 0 4 36 mm 4 59 mm 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 Die No Chip thickness 400 µm Pad opening 98 µm ...

Page 142: ...2 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 X 2 052 2 052 2 052 2 052 2 052 2 052 2 052 2 052 2 052 2 052 2 052 2 052 2 052 2 052 2 052 2 052 2 052 2 052 1 557 1 427 1 297 1 167 1 037 0 907 0 777 0 647 0 517 0 387 0 257 0 127 0 003 0 133 0 263 0 393 Y 0 769 0 625 0 492 0 362 0 232 0 102 0 029 0 159 0 289 0 419 0 549 0 726 0 856 0 986 1 116 1 246 1 376 1 506 2 169 2 169 2 169 2 16...

Page 143: ... provided with your ICE for detailed information on its functions and method of use A 1 Names and Functions of Each Part The following explains the names and functions of each part of the board S5U1C63000P VSVD VC5 PRG CLK RESET IOSEL2 XC4062XLA D E 1 3 VLCD CN3 connector Unused CN2 connector CN1 connector 3 4 9 1 2 11 10 9 8 7 6 5 1 VLCD You can turn this control to adjust the LCD drive power sup...

Page 144: ... 11 13 15 2 4 6 8 10 12 14 16 LED 5 CR oscillation frequency adjusting control When OSC1 and OSC3 respectively are set for a CR oscillation circuit and a CR ceramic oscillation circuit by a mask option this control allows you to adjust the oscillation frequency The oscillation frequency can be adjusted in the range of approx 20 kHz to 500 kHz for OSC1 and approx 100 kHz to 8 MHz for OSC3 Note that...

Page 145: ...this board will remain incomplete and the debugger may not be able to start when you power on the ICE once again In this case temporarily power off the ICE and set CLK to the 32K position and the PRG switch to the Prog position then switch on power for the ICE once again This should allow the debugger to start up allowing you to download circuit data After downloading the circuit data temporarily ...

Page 146: ...d S5U1C63000P to the target system use the I O connecting cables supplied with the board 80 pin 40 pin 2 100 pin 50 pin 2 flat type Take care when handling the connectors since they conduct electrical power VDD 3 3 V CN1 1 40 pin CN1 2 40 pin I O connection cable To target board mark CN2 2 50 pin CN2 1 50 pin Fig A 2 1 Connecting the S5U1C63000P to the target system ...

Page 147: ...C SEG10 DC SEG11 DC SEG12 DC SEG13 DC SEG14 DC SEG15 DC VDD 3 3 V VDD 3 3 V SEG16 DC SEG17 DC SEG18 DC SEG19 DC SEG20 DC SEG21 DC SEG22 DC SEG23 DC VSS VSS SEG24 DC SEG25 DC SEG26 DC SEG27 DC SEG28 DC SEG29 DC SEG30 DC SEG31 DC VDD 3 3 V VDD 3 3 V Cannot be connected Cannot be connected Cannot be connected Cannot be connected Cannot be connected Cannot be connected Cannot be connected Cannot be co...

Page 148: ... exceeding VDD by setting the output ports for open drain mode Pull up resistance value The pull up resistance values on this board are set to 220 kΩ which differ from those for the actual IC For the resistance values on the actual IC refer to the technical manual for the S1C63158 358 P366 Note that when using pull up resistors to pull the input pins high the input pins may require a certain perio...

Page 149: ... SVD circuit turns on until actual detection of the voltage On this board this delay is set to 61 92 µsec which differs from that of the actual IC Refer to the technical manual for the S1C63158 358 P366 when setting the appropriate wait time for the actual IC Oscillation circuit A wait time is required before oscillation stabilizes after the OSC3 oscillation control circuit OSCC is turned on On th...

Page 150: ...stem reset can be per formed by pressing the reset switch on this board by a reset pin input or by holding the input ports low simultaneously Internal power supply circuit Although this board contains VDC DBON HLON VDSEL and VADSEL registers it does not actually exercise power supply control by these registers Be sure to refer to the technical manual for the S1C63158 358 P366 when setting the corr...

Page 151: ...491 Scotland Design Center Integration House The Alba Campus Livingston West Lothian EH54 7EG SCOTLAND Phone 44 1506 605040 Fax 44 1506 605041 ASIA EPSON CHINA CO LTD 23F Beijing Silver Tower 2 North RD DongSanHuan ChaoYang District Beijing CHINA Phone 64106655 Fax 64107319 SHANGHAI BRANCH 7F High Tech Bldg 900 Yishan Road Shanghai 200233 CHINA Phone 86 21 5423 5577 Fax 86 21 5423 4677 EPSON HONG ...

Page 152: ...EPSON Electronic Devices Website ELECTRONIC DEVICES MARKETING DIVISION http www epsondevice com Technical Manual S1C63358 First issue November 1997 Printed October 2002 in Japan A L M ...

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