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11 PROGRaMMaBle TiMeR

11-4

Seiko epson Corporation

S1C63003/004/008/016 TeChniCal Manual

(Rev. 1.1)

Basic Counter Operation

11.3

This section explains the basic count operation when each timer is used as an individual 8-bit timer.
Each timer has an 8-bit down counter and an 8-bit reload data register.
The reload data register RLDx[7:0] is used to set the initial value to the down counter.
By writing "1" to the timer reset bit PTRSTx, the down counter loads the initial value set in the reload register. There-
fore, down-counting is executed from the stored initial value by the count clock.
The PTRUNx register is provided to control the RUN/STOP for each timer. By writing "1" to this register after pre-
setting the reload data to the down counter, the down counter starts counting down. Writing "0" stops the input count
clock and the down counter stops counting. This control (RUN/STOP) does not affect the counter data. The counter
maintains its data while stopped, and can restart counting continuing from that data.
The counter data can be read via the data buffer PTDx[7:0] in optional timing. However, the counter has the data hold
function the same as the clock timer, that holds the high-order data (PTDx[7:4]) when the low-order data (PTDx[3:0])
is read in order to prevent the borrowing operation between low- and high-order reading, therefore be sure to read
the low-order data first.
The counter reloads the initial value set in the reload data register when an underflow occurs through the count down.
It continues counting down from the initial value after reloading.
In addition to reloading the counter, this underflow signal controls the interrupt generation and pulse (TOUT_A/
TOUT_B signal) output. The underflow signal of Timer 1 (S1C63004/008/016) is also used to generate the clock to
be supplied to the serial interface and R/F converter.

PTRUNx

PTRSTx

RLDx[7:0]

Count clock

PTDx7

PTDx6

PTDx5

PTDx4

PTDx3

PTDx2

PTDx1

PTDx0

A6H

F3H

Preset

Reload &
underflow interrupt

3.1 Basic operation timing of down counter

Figure 11.

event Counter Mode (Timers 0 and 2)

11.4

Timer 0/Timer 2 has an event counter function that counts an external clock input to an I/O port. Table 11.4.1 lists
the timers and their clock input ports.

4.1 Event counter clock input port

Table 11.

Timer

External clock input terminal

Control register

Timer 0 (Ch.A)

EVIN_A (P10)

EVCNT_A

Timer 2 (Ch.B)

*

EVIN_B (P22)

*

EVCNT_B

*

*

S1C63004/008/016

This function is selected by writing "1" to the counter mode select register EVCNT_A/EVCNT_B. This sets the
corresponding I/O port to input mode and enables the port to send the input signal to Timer 0/Timer 2 as the count
clock. At initial reset, EVCNT_A/EVCNT_B is set to "0" and Timer 0/Timer 2 is configured as a normal timer that
counts the internal clock.

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Summary of Contents for S1C63003

Page 1: ...Rev 1 1 CMOS 4 BiT SinGle ChiP MiCROCOnTROlleR S1C63003 004 008 016 Technical Manual ...

Page 2: ... procedures required by such laws and regulations You are requested not to use to resell to export and or to otherwise dispose of the products and any technical information furnished if any for the development and or manufacture of weapon of mass destruction or for other military purposes All brands or product names mentioned herein are trademarks and or registered trademarks of their respective c...

Page 3: ...gital products Product classification S1 semiconductor Development tools S5U1 C 63000 A1 1 Packing specifications 00 standard packing Version 1 Version 1 Tool type Hx ICE Ex EVA board Px Peripheral board Wx Flash ROM writer for the microcomputer Xx ROM writer peripheral board Cx C compiler package Ax Assembler package Dx Utility tool by the model Qx Soft simulator Yx Writer software Corresponding ...

Page 4: ... Plastic Package 2 20 2 5 2 Ceramic Package for Test Samples 2 22 3 CPu and Memory 3 1 3 1 CPU 3 1 3 2 Code Memory Area 3 1 3 2 1 Code ROM 3 1 3 3 Data Memory Area 3 2 3 3 1 RAM 3 2 3 3 2 Data ROM 3 3 3 3 3 Display Memory 3 3 3 3 4 I O Memory 3 4 4 initial Reset 4 1 4 1 Initial Reset Circuit 4 1 4 2 Reset Terminal RESET 4 1 4 3 Simultaneous High Input to P0x Ports P00 P03 4 2 4 4 Internal Register...

Page 5: ...ock Timer 9 1 9 1 Configuration of Clock Timer 9 1 9 2 Controlling Operating Clock 9 1 9 3 Data Read and Hold Function 9 1 9 4 Interrupt Function 9 2 9 5 I O Memory of Clock Timer 9 2 9 6 Precautions 9 4 10 Stopwatch Timer 10 1 10 1 Configuration of Stopwatch Timer 10 1 10 2 Controlling Operating Clock 10 1 10 3 Counter and Prescaler 10 2 10 4 Capture Buffer and Hold Function 10 2 10 5 Stopwatch T...

Page 6: ...ronous Clock Format 13 4 13 6 Data Input Output and Interrupt Function 13 5 13 6 1 Serial Data Output Procedure and Interrupt 13 5 13 6 2 Serial Data Input Procedure and Interrupt 13 5 13 6 3 Serial Data Input Output Permutation 13 6 13 6 4 SRDY Signal 13 6 13 6 5 Timing Chart 13 6 13 7 Data Transfer in SPI Mode 13 8 13 8 I O Memory of Serial Interface 13 9 13 9 Precautions 13 12 14 lCD Driver 14 ...

Page 7: ... 4 Precautions 17 2 18 integer Multiplier S1C63008 016 18 1 18 1 Configuration of Integer Multiplier 18 1 18 2 Controlling Clock Manager 18 1 18 3 Multiplication Mode 18 1 18 4 Division Mode 18 2 18 5 Execution Cycle 18 2 18 6 I O Memory of Integer Multiplier 18 3 18 7 Precautions 18 5 19 electrical Characteristics 19 1 19 1 Absolute Maximum Rating 19 1 19 2 Recommended Operating Conditions 19 1 1...

Page 8: ...1 2 S5U1C6F016P2 AP B 3 B 2 Connecting to the Target System AP B 5 B 3 Downloading to S5U1C63000P6 AP B 8 B 4 Usage Precautions AP B 9 B 4 1 Operational precautions AP B 9 B 4 2 Differences with the actual IC AP B 9 B 5 Product Specifications AP B 12 B 5 1 Specifications of S5U1C63000P6 AP B 12 B 5 2 Specifications of S5U1C6F016P2 AP B 12 appendix C Power Saving aP C 1 C 1 Power Saving by Clock Co...

Page 9: ... ROM capacity Code ROM 16 384 words 13 bits 8 192 words 13 bits 4 096 words 13 bits Data ROM 4 096 words 4 bits 2 048 words 4 bits 1 024 words 4 bits Not available RAM capacity Data memory 2 048 words 4 bits 1 024 words 4 bits 512 words 4 bits 256 words 4 bits Display memory 448 bits 400 bits 288 bits 110 bits I O ports 24 bits 24 bits 20 bits 16 bits Pull down resistors can be included 1 The pins...

Page 10: ...EY10 13 FOUT KRST00 03 RUN_STP LAP EVIN_A B TOUT_A B BZ SCLK SOUT SIN SRDY_SS RFOUT RFIN0 SEN0 REF0 RFIN1 SEN1 REF1 HUD P00 KEY00 RUN_STP KRST00 P01 KEY01 LAP KRST01 P02 KEY02 KRST02 P03 KEY03 KRST03 P10 KEY10 EVIN_A P11 KEY11 TOUT_A P12 KEY12 BZ P13 KEY13 FOUT P20 P21 P22 EVIN_B P23 TOUT_B P30 SCLK P31 SOUT P32 SIN P33 SRDY_SS P40 P41 P42 P43 P50 RFOUT P51 SEN0 P52 REF0 P53 RFIN0 HUD SEN1 REF1 RF...

Page 11: ...EY02 KRST02 P03 KEY03 KRST03 P10 KEY10 EVIN_A P11 KEY11 TOUT_A P12 KEY12 BZ P13 KEY13 FOUT P20 P21 P22 EVIN_B P23 TOUT_B P30 SCLK P31 SOUT P32 SIN P33 SRDY_SS P40 P41 P42 P43 P50 RFOUT P51 SEN0 P52 REF0 P53 RFIN0 HUD SEN1 REF1 RFIN1 VDD VD1 VOSC VC1 3 CA CB VSS Core CPu S1C63000 Code ROM 8 192 words 13 bits System Reset Control Interrupt Controller OSC RAM 1 024 words 4 bits Data ROM 2 048 words 4...

Page 12: ...5 SEG46 SEG47 SEG40 SEG41 SEG42 SEG43 SEG48 SEG49 SEG50 SEG51 SEG55 SEG54 SEG53 SEG52 SEG0 19 COM0 7 KEY00 03 KEY10 13 FOUT SEG40 55 KRST00 03 RUN_STP LAP EVIN_A B TOUT_A B BZ SCLK SOUT SIN SRDY_SS RFOUT RFIN0 SEN0 REF0 RFIN1 SEN1 REF1 HUD Mask option Core CPu S1C63000 Code ROM 4 096 words 13 bits System Reset Control Interrupt Controller OSC RAM 512 words 4 bits Data ROM 1 024 words 4 bits LCD Co...

Page 13: ...1 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG55 SEG54 SEG53 SEG52 SEG0 9 COM0 4 KEY00 03 FOUT SEG44 55 KRST00 03 EVIN_A TOUT_A BZ RFOUT RFIN0 SEN0 REF0 RFIN1 SEN1 REF1 HUD Mask option Core CPu S1C63000 Code ROM 4 096 words 13 bits System Reset Control Interrupt Controller OSC RAM 256 words 4 bits LCD Controller Driver Power Controller Watchdog Timer Clock Management Unit Clock Timer Stopwa...

Page 14: ... port Either complementary output or P channel open drain output can be selected as the output cell type of each I O port P00 P53 Refer to Mask Option in the I O Ports chapter for details Do not configure the P50 P53 ports to P channel open drain output if the R F converter channel 0 is used 7 Multiple key entry reset function by simultaneous high input to the P0x ports This option allows selectio...

Page 15: ... Use 2 Not Use P21 1 Use 2 Not Use P22 1 Use 2 Not Use P23 1 Use 2 Not Use P30 1 Use 2 Not Use P31 1 Use 2 Not Use P32 1 Use 2 Not Use P33 1 Use 2 Not Use P40 1 Use 2 Not Use P41 1 Use 2 Not Use P42 1 Use 2 Not Use P43 1 Use 2 Not Use P50 1 Use 2 Not Use P51 1 Use 2 Not Use P52 1 Use 2 Not Use P53 1 Use 2 Not Use I O port output specification P00 1 Complementary 2 Pch Open Drain P01 1 Complementar...

Page 16: ...lt in R 2 CR external R 3 Ceramic 4 0 MHz RESET terminal pull down resistor 1 Use 2 Not Use SEG GPIO RFC selector P20 1 I O 2 SEG P21 1 I O 2 SEG P22 1 I O 2 SEG P23 1 I O 2 SEG P30 1 I O 2 SEG P31 1 I O 2 SEG P32 1 I O 2 SEG P33 1 I O 2 SEG P50 1 I O 2 SEG P51 1 I O 2 SEG P52 1 I O 2 SEG P53 1 I O 2 SEG RFIN1 1 RFC 2 SEG REF1 1 RFC 2 SEG SEN1 1 RFC 2 SEG HUD 1 RFC 2 SEG I O port pull down resisto...

Page 17: ...t specification if the R F converter channel 0 is used 3 3 Option list S1C63003 Table 1 Optional item Option Operating power voltage 1 Normal Type 1 8 5 5 V 2 Low Voltage Type 1 1 1 7 V OSC3 oscillation circuit n 1 CR built in R 2 CR external R 3 Ceramic 4 0 MHz RESET terminal pull down resistor 1 Use 2 Not Use SEG GPIO RFC selector P20 1 I O 2 SEG P21 1 I O 2 SEG P22 1 I O 2 SEG P23 1 I O 2 SEG P...

Page 18: ...rain P53 1 Complementary 2 Pch Open Drain P0x port multiple key entry reset combination 1 Not Use 2 Use P00 P01 3 Use P00 P01 P02 4 Use P00 P01 P02 P03 P0x port multiple key entry reset time authorization 1 Not Use 2 Use LCD drive power supply 1 Internal VC2 reference 1 3 bias 3 0 V panel 2 Internal VC1 reference 1 3 bias 3 0 V panel 3 External 1 3 bias VDD VC2 4 5 V panel 4 External 1 3 bias VDD ...

Page 19: ...G41 n S C N SEG42 n S C N SEG43 n S C N SEG44 n S C N SEG45 n S C N SEG46 n S C N SEG47 n S C N SEG48 n S C N SEG49 n S C N SEG50 n S C N SEG51 n S C N SEG52 n S C N SEG53 n S C N SEG54 n S C N SEG55 n S C N address H RAM data high order address 0 7 Output specification S Segment output L RAM data low order address 0 F C Complementary output D Data bit 0 3 N Nch open drain output Notes for using t...

Page 20: ... C N SEG49 n S C N SEG50 n S C N SEG51 n S C N SEG52 n S C N SEG53 n S C N SEG54 n S C N SEG55 n S C N address H RAM data high order address 0 7 Output specification S Segment output L RAM data low order address 0 F C Complementary output D Data bit 0 3 N Nch open drain output Notes for using the segment option generator winsog S1C63008 1 The output specification of SEG0 to SEG29 can be selected f...

Page 21: ... SEG48 n S C N SEG49 n S C N SEG50 n S C N SEG51 n S C N SEG52 n S C N SEG53 n S C N SEG54 n S C N SEG55 n S C N address H RAM data high order address 0 7 Output specification S Segment output L RAM data low order address 0 F C Complementary output D Data bit 0 3 N Nch open drain output Notes for using the segment option generator winsog S1C63004 1 The output specification of SEG0 to SEG19 can be ...

Page 22: ...EG52 n S C N SEG53 n S C N SEG54 n S C N SEG55 n S C N address H RAM data high order address 0 3 Output specification S Segment output L RAM data low order address 0 F C Complementary output D Data bit 0 3 N Nch open drain output Notes for using the segment option generator winsog S1C63003 1 The output specification of SEG0 to SEG9 can be selected from LCD segment output S DC complementary output ...

Page 23: ...01 KRST01 KEY01 LAP P02 KRST02 KEY02 P03 KRST03 KEY03 N C N C N C N C V SS ReSeT TeST N C N C V DD V D1 OSC4 OSC3 V SS OSC2 OSC1 V OSC 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VC1 VC2 VC3 Ca CB N C N C N C COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SeG0 SeG1 SeG2 SeG3 SeG4 SeG5 SeG6 SeG7 SeG8...

Page 24: ... 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 91 Die No 1 1 2 S1C63016 pad layout diagram Figure 2 Chip thickness 400 µm Pad opening X Y 77 85 µm No 1 to No 25 No 51 to No 72 85 77 µm No 26 to No 50 No 73 to No 91 Note A chip thickness that exceeds 400 µm cannot be specified even if a chip other than the standard thickness type is required ...

Page 25: ...G39 523 0 1247 5 69 CA 801 0 1247 5 20 P42 SEG38 630 0 1247 5 70 VC3 891 0 1247 5 21 P41 SEG37 737 0 1247 5 71 VC2 981 0 1247 5 22 P40 SEG36 844 0 1247 5 72 VC1 1071 0 1247 5 23 VSS 951 0 1247 5 73 VOSC 1236 5 1023 0 24 SEG35 1041 0 1247 5 74 OSC1 1236 5 933 0 25 SEG34 1197 0 1247 5 75 OSC2 1236 5 843 0 26 SEG33 1236 5 971 0 76 VSS 1236 5 753 0 27 SEG32 1236 5 881 0 77 OSC3 1236 5 663 0 28 SEG31 1...

Page 26: ...input P02 P02 85 69 I o D I O port pin KRST02 I OP Key reset input pin KEY02 I SFT Port interrupt input pin P03 P03 84 68 I o D I O port pin KRST03 I OP Key reset input pin KEY03 I SFT Port interrupt input pin P10 P10 91 75 I o D I O port pin KEY10 I SFT Port interrupt input pin EVIN_A I SFT Event counter programmable timer 0 input pin P11 P11 90 74 I o D I O port pin KEY11 I SFT Port interrupt in...

Page 27: ...I SFT R F converter Ch 0 CR oscillation input pin SEG51 O OP LCD segment output pin RFin1 RFIN1 4 79 I OP R F converter Ch 1 CR oscillation input pin SEG52 O OP LCD segment output pin ReF1 REF1 3 78 O OP R F converter Ch 1 CR oscillation output pin for reference resistor SEG53 O OP LCD segment output pin Sen1 SEN1 2 77 O OP R F converter Ch 1 CR oscillation output pin for DC bias sensor SEG54 O OP...

Page 28: ...Y01 LAP P02 KRST02 KEY02 P03 KRST03 KEY03 N C N C N C N C V SS ReSeT TeST N C N C V DD V D1 OSC4 OSC3 V SS OSC2 OSC1 V OSC 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VC1 VC2 VC3 Ca CB N C N C N C COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SeG0 SeG1 SeG2 SeG3 SeG4 SeG5 SeG6 SeG7 SeG8 huD Sen1 Re...

Page 29: ...5 10 15 45 50 55 60 65 70 75 85 80 1 20 25 30 35 40 Die No 2 1 2 S1C63008 pad layout diagram Figure 2 Chip thickness 400 µm Pad opening X Y 77 85 µm No 1 to No 19 No 43 to No 61 85 77 µm No 20 to No 42 No 62 to No 85 Note A chip thickness that exceeds 400 µm cannot be specified even if a chip other than the standard thickness type is required ...

Page 30: ...EY11 TOUT_A 558 0 1159 5 19 SEG10 808 0 1159 5 61 P10 KEY10 EVIN_A 648 0 1159 5 20 SEG9 1138 5 1089 0 62 HUD SEG55 1138 5 1088 0 21 SEG8 1138 5 999 0 63 SEN1 SEG54 1138 5 998 0 22 SEG7 1138 5 909 0 64 REF1 SEG53 1138 5 908 0 23 SEG6 1138 5 819 0 65 RFIN1 SEG52 1138 5 818 0 24 SEG5 1138 5 729 0 66 VSS 1138 5 728 0 25 SEG4 1138 5 639 0 67 P53 RFIN0 SEG51 1138 5 638 0 26 SEG3 1138 5 549 0 68 P52 REF0...

Page 31: ...input P02 P02 55 69 I o D I O port pin KRST02 I OP Key reset input pin KEY02 I SFT Port interrupt input pin P03 P03 54 68 I o D I O port pin KRST03 I OP Key reset input pin KEY03 I SFT Port interrupt input pin P10 P10 61 75 I o D I O port pin KEY10 I SFT Port interrupt input pin EVIN_A I SFT Event counter programmable timer 0 input pin P11 P11 60 74 I o D I O port pin KEY11 I SFT Port interrupt in...

Page 32: ...N0 I SFT R F converter Ch 0 CR oscillation input pin SEG51 O OP LCD segment output pin RFin1 RFIN1 65 79 I OP R F converter Ch 1 CR oscillation input pin SEG52 O OP LCD segment output pin ReF1 REF1 64 78 O OP R F converter Ch 1 CR oscillation output pin for reference resistor SEG53 O OP LCD segment output pin Sen1 SEN1 63 77 O OP R F converter Ch 1 CR oscillation output pin for DC bias sensor SEG5...

Page 33: ...T P51 SEN0 P52 REF0 P53 RFIN0 V SS RFin1 ReF1 Sen1 huD 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 N C P10 KEY10 EVIN_A P11 KEY11 TOUT_A P12 KEY12 BZ P13 KEY13 FOUT P00 KRST00 KEY00 RUN_STP P01 KRST01 KEY01 LAP P02 KRST02 KEY02 P03 KRST03 KEY03 VSS ReSeT TeST VDD VD1 OSC4 OSC3 VSS OSC2 OSC1 VOSC SeG19 SeG18 SeG17 SeG16 SeG...

Page 34: ...in1 ReF1 Sen1 huD N C N C 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 N C N C N C N C N C P10 KEY10 EVIN_A P11 KEY11 TOUT_A P12 KEY12 BZ P13 KEY13 FOUT P00 KRST00 KEY00 RUN_STP P01 KRST01 KEY01 LAP P02 KRST02 KEY02 P03 KRST03 KEY03 VSS N C ReSeT TeST VDD VD1 OSC4 OSC3 VSS OSC2 OSC1 VOSC SeG19...

Page 35: ...oration 2 13 Rev 1 1 Diagram of pad layout 2 500 mm Y X 0 0 2 195 mm 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 Die No 3 1 3 S1C63004 pad layout diagram Figure 2 Chip thickness 400 µm Pad opening X Y 77 85 µm No 1 to No 18 No 39 to No 51 85 77 µm No 19 to No 38 No 52 to No 70 ...

Page 36: ...P33 SRDY_SS SEG43 280 5 1149 0 49 VC3 7 5 1149 0 15 P32 SIN SEG42 370 5 1149 0 50 VC2 82 5 1149 0 16 P31 SOUT SEG41 460 5 1149 0 51 VC1 172 5 1149 0 17 P30 SCLK SEG40 550 5 1149 0 52 VOSC 996 5 1074 0 18 VDD 640 5 1149 0 53 OSC1 996 5 984 0 19 SEG19 996 5 1040 5 54 OSC2 996 5 894 0 20 SEG18 996 5 950 5 55 VSS 996 5 804 0 21 SEG17 996 5 860 5 56 OSC3 996 5 714 0 22 SEG16 996 5 770 5 57 OSC4 996 5 6...

Page 37: ...STOP input P02 P02 64 33 39 I o D I O port pin KRST02 I OP Key reset input pin KEY02 I SFT Port interrupt input pin P03 P03 63 32 38 I o D I O port pin KRST03 I OP Key reset input pin KEY03 I SFT Port interrupt input pin P10 P10 70 39 45 I o D I O port pin KEY10 I SFT Port interrupt input pin EVIN_A I SFT Event counter programmable timer 0 input pin P11 P11 69 38 44 I o D I O port pin KEY11 I SFT ...

Page 38: ... input pin SEG52 O OP LCD segment output pin ReF1 REF1 3 43 55 O OP R F converter Ch 1 CR oscillation output pin for reference resistor SEG53 O OP LCD segment output pin Sen1 SEN1 2 42 54 O OP R F converter Ch 1 CR oscillation output pin for DC bias sensor SEG54 O OP LCD segment output pin huD HUD 1 41 53 O OP R F converter CR oscillation output pin for AC bias sensor SEG55 O OP LCD segment output...

Page 39: ...M4 COM3 P10 EVIN_A P11 TOUT_A P12 BZ P13 FOUT P00 KRST00 KEY00 P01 KRST01 KEY01 P02 KRST02 KEY02 P03 KRST03 KEY03 ReSeT TeST V DD V D1 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 VSS OSC2 OSC1 VOSC VC1 VC2 VC3 Ca CB COM0 COM1 COM2 huD Sen1 ReF1 RFin1 RFIN0 P53 REF0 P52 SEN0 P51 RFOUT P50 P23 P22 P21 P20 SeG55 SeG54 SeG53 SeG52 SeG51 SeG50 SeG49 SeG48 SeG47 SeG46 SeG45 S...

Page 40: ... 214 0 859 0 5 VSS 87 6 859 0 30 CA 124 0 859 0 6 P53 RFIN0 SEG51 2 4 859 0 31 VC3 34 0 859 0 7 P52 REF0 SEG50 92 4 859 0 32 VC2 56 0 859 0 8 P51 SEN0 SEG49 182 4 859 0 33 VC1 146 0 859 0 9 P50 RFOUT SEG48 272 4 859 0 34 VOSC 236 0 859 0 10 P23 SEG47 362 4 859 0 35 OSC1 326 0 859 0 11 P22 SEG46 452 4 859 0 36 OSC2 416 0 859 0 12 P21 SEG45 542 4 859 0 37 VSS 506 0 859 0 13 P20 SEG44 632 4 859 0 38 ...

Page 41: ... 11 46 I o OP I O port pin SEG46 O OP LCD segment output pin P23 P23 10 45 I o OP I O port pin SEG47 O OP LCD segment output pin P50 P50 9 44 I o OP D I O port pin RFOUT O SFT R F converter CR oscillation clock output pin SEG48 O OP LCD segment output pin P51 P51 8 43 I o OP D I O port pin SEN0 O SFT R F converter Ch 0 CR oscillation output pin for DC bias sensor SEG49 O OP LCD segment output pin ...

Page 42: ...ackage 2 5 Plastic Package 2 5 1 QFP15 100pin S1C63008 016 Unit mm 14 16 51 75 14 16 26 50 INDEX 0 17 0 27 25 1 100 76 1 4 0 1 1 7 max 1 0 3 0 75 0 10 0 09 0 2 0 5 TQFP14 100pin S1C63004 008 016 Unit mm 51 75 26 50 INDEX 25 1 100 76 12 14 12 14 0 13 0 23 0 4 1 0 1 1 2 max 1 0 3 0 75 0 10 0 09 0 2 ...

Page 43: ... Corporation 2 21 Rev 1 1 QFP14 80pin S1C63004 Unit mm 12 14 41 60 12 14 21 40 INDEX 0 13 0 27 20 1 80 61 1 4 0 1 1 7 max 1 0 3 0 75 0 10 0 09 0 2 0 5 QFP12 48pin S1C63003 Unit mm 7 9 25 36 7 9 13 24 INDEX 0 13 0 27 12 1 48 37 1 4 0 1 1 7 max 1 0 3 0 7 0 10 0 09 0 2 0 5 ...

Page 44: ... Unit mm 13 97 0 15 12 00Typ 17 00 0 30 0 50 0 20 1 25 26 50 75 51 100 76 GLASS CERAMIC 0 50Typ 0 82 0 30 2 54max 0 76 0 13 0 95 0 08 0 38 0 08 Pin configuration S1C63016 Same as that of the QFP15 100pin TQFP14 100pin plastic package S1C63008 Same as that of the QFP15 100pin TQFP14 100pin plastic package S1C63004 Same as that of the TQFP14 100pin plastic package ...

Page 45: ...35 N C 51 HUD SEG55 4 SEG9 20 COM1 36 VD1 52 SEN1 SEG54 5 SEG8 21 COM0 37 VDD 53 REF1 SEG53 6 SEG7 22 CB 38 TEST 54 RFIN1 SEG52 7 SEG6 23 CA 39 RESET 55 VSS 8 SEG5 24 VC3 40 P03 KRST03 KEY03 56 P53 RFIN0 SEG51 9 SEG4 25 VC2 41 P02 KRST02 KEY02 57 P52 REF0 SEG50 10 SEG3 26 VC1 42 P01 KRST01 KEY01 58 P51 SEN0 SEG49 11 SEG2 27 VOSC 43 P00 KRST00 KEY00 59 P50 RFOUT SEG48 12 SEG1 28 OSC1 44 P13 FOUT 60...

Page 46: ... hardware interrupt vectors are allocated to step 0100H and steps 0101H 010FH respectively 0000H 0FFFH 1000H FFFFH 0000H 0100H 0101H 0110H 0100H 0101H 0102H 0103H 0104H 0105H 0106H 0107H 0108H 0109H 010AH 010BH 010CH 010DH 010EH 010FH Program area NMI vector Hardware interrupt vectors Program start address Program area Code ROM S1C63003 Unused area 13 bits S1C63000 core CPU program space Code ROM ...

Page 47: ... If the pro gram that accesses these areas is generated its operation cannot be guaranteed Refer to the I O memory maps in the Appendix for the peripheral I O area RaM 3 3 1 The RAM is a data memory for storing various kinds of data 3 1 1 RAM capacity Table 3 Model Capacity Address S1C63016 2 048 words 4 bits 0000H to 07FFH S1C63008 1 024 words 4 bits 0000H to 03FFH S1C63004 512 words 4 bits 0000H...

Page 48: ... 0200H 03FFH S1C63008 0000H 00FFH 0100H 01FFH S1C63004 0000H 007FH 0100H 017FH S1C63003 3 1 1 RAM configuration Figure 3 Data ROM 3 3 2 The data ROM is used for loading various static data such as a character generator and data can be read using the same data memory access instructions as the RAM 3 2 1 Data ROM capacity Table 3 Model Capacity Address S1C63016 4 096 words 4 bits 8000H to 8FFFH S1C6...

Page 49: ...as shown in the figure below Refer to the Appendix for the register list and descriptions of each peripheral circuit for details of the registers S1C63xxx Address Peripheral circuit 016 008 004 003 FF00H Oscillation circuit FF01H Watchdog timer FF03H Power supply circuit FF04H FF05H SVD circuit FF10H FF1BH Clock manager FF20H FF3FH I O ports and input interrupt control FF40H FF42H Clock timer FF44...

Page 50: ...el VDD After that the initial reset is released by setting the reset terminal to a low level VSS and the CPU starts operating The reset input signal is maintained by the RS latch and becomes the internal initial reset signal The RS latch is designed to be released by a 16 Hz signal high that is divided by the OSC1 clock Therefore in normal operation a maximum of 1 024 fOSC1 seconds 32 msec when fO...

Page 51: ...imultaneous high input and performs initial reset if that time is the defined time 1 to 2 sec or more If using this function make sure that the specified ports do not go high at the same time during ordinary operation internal Register at initial Resetting 4 4 Initial reset initializes the CPU as shown in Table 4 4 1 The registers and flags which are not initialized by initial reset should be init...

Page 52: ...verter Stopwatch direct input 2 Event counter TOUT FOUT BZ Master Slave P00 P00 IN PD 1 RUN STOP P01 P01 IN PD 1 LAP P02 P02 IN PD 1 P03 P03 IN PD 1 P10 P10 IN PD 1 EVIN_A P11 P11 IN PD 1 TOUT_A P12 P12 IN PD 1 BZ P13 P13 IN PD 1 FOUT P20 P21 P20 P21 IN PD 1 P22 P22 IN PD 1 EVIN_B 2 P23 P23 IN PD 1 TOUT_B 2 P30 2 P30 IN PD 1 SCLK O SCLK I P31 2 P31 IN PD 1 SOUT O SOUT O P32 2 P32 IN PD 1 SIN I SIN...

Page 53: ...SC4 OSC1 OSC2 COMx SEGxx Pxx External power supply 1 5 V low voltage type 3 V normal type Mask option LCD driver VDD VD1 VOSC VC1 VC2 VC3 CA CB VSS VC1 VC2 VC3 VD1 VOSC Internal operating voltage regulator LCD system voltage regulator LPWR VCREF VCHLMOD VDHLMOD CPU Internal circuits OSC3 oscillation circuit OSC1 oscillation circuit OSC1 oscillation circuit voltage regulator I O interface a S1C6300...

Page 54: ...for the voltage values In the S1C63003 004 008 016 the LCD drive voltage is supplied to the built in LCD driver that drives the LCD panel connected to the SEG and COM terminals The LCD system voltage regulator can be disabled by mask option to supply external voltages In this case ex ternal elements can be minimized because the external capacitors for the LCD system voltage regulator are not neces...

Page 55: ...power consumption Notes The LCD system voltage regulator takes about 100 msec for stabilizing the LCD drive voltages after writing 1 to LPWR Do not select the reference voltage VC2 for the S1C63003 1 5 V low voltage type Furthermore the LCD system voltage regulator uses the boost clock supplied from the clock manager for boosting reducing the voltage The clock supply is controlled by the VCCKS 1 0...

Page 56: ...ulator reference voltage select register FF03h D1 S1C63004 008 016 Selects the reference voltage generated in the LCD system voltage regulator When 1 is written VC2 When 0 is written VC1 Reading Valid When 1 is written to VCREF the LCD system voltage regulator generates the reference voltage VC2 and gener ates two other voltages VC1 VC2 1 2 VC3 VC2 3 2 by boosting and reducingVC2 WhenVCREF is 0 th...

Page 57: ...ystem voltage regulator 5 2 Controlling boost clock Table 5 VCCKS 1 0 Boost clock control 3 or 2 Prohibited 1 On 2 kHz 0 Off The LCD system voltage regulator uses the boost clock supplied from the clock manager for boosting reducing the voltage Use this register to control the clock supply Set VCCKS 1 0 to 1 before writing 1 to LPWR When LCD display is not necessary stop the clock supply by settin...

Page 58: ...ng interrupt mask register must be set to 1 enable When an interrupt occurs the interrupt flag is automatically reset to 0 DI and interrupts after that are disabled The watchdog timer interrupt is an NMI non maskable interrupt therefore the interrupt is generated regardless of the interrupt flag setting Also the interrupt mask register is not provided However it is possible to disable NMI since so...

Page 59: ...0 IPT0 EIPT0 ICTC0 EICTC0 IPT1 EIPT1 ICTC1 EICTC1 IPT2 EIPT2 ICTC2 EICTC2 IPT3 EIPT3 ICTC3 EICTC3 ISIF EISIF PCP03 SIP03 IK03 EIK03 IRFS EIRFS P03 PCP02 SIP02 IK02 EIK02 P02 PCP01 SIP01 IK01 EIK01 P01 PCP00 SIP00 IK00 EIK00 P00 SLEEP cancellation PCP13 SIP13 IK13 EIK13 P13 PCP12 SIP12 IK12 EIK12 P12 PCP11 SIP11 IK11 EIK11 P11 PCP10 SIP10 IK10 EIK10 P10 IT3 EIT3 IT2 EIT2 IT1 EIT1 IT0 EIT0 IT7 EIT7 ...

Page 60: ...FFBH D3 EIK03 FFEBH D3 Key input interrupt P02 IK02 FFFBH D2 EIK02 FFEBH D2 Key input interrupt P01 IK01 FFFBH D1 EIK01 FFEBH D1 Key input interrupt P00 IK00 FFFBH D0 EIK00 FFEBH D0 Key input interrupt P13 IK13 FFFCH D3 EIK13 FFECH D3 Key input interrupt P12 IK12 FFFCH D2 EIK12 FFECH D2 Key input interrupt P11 IK11 FFFCH D1 EIK11 FFECH D1 Key input interrupt P10 IK10 FFFCH D0 EIK10 FFECH D0 Stopwa...

Page 61: ...ial interface 010BH Key input interrupt P0 010CH Key input interrupt P1 010DH Stopwatch timer 010EH Clock timer 128 Hz 64 Hz 32 Hz 16 Hz 010FH Clock timer 8 Hz 4 Hz 2 Hz 1 Hz Low The S1C63003 supports 32 Hz 8 Hz 2 Hz and 1 Hz interrupts only The four low order bits of the program counter are indirectly addressed through the interrupt request Note The interrupt handler routine must be located withi...

Page 62: ...ble 0 Mask Interrupt mask register PT3 compare match FFEAH 6 D3 0 3 R 2 Unused D2 0 3 R 2 Unused D1 0 3 R 2 Unused D0 eiSiF R W 0 1 Enable 0 Mask Interrupt mask register Serial I F FFEBH D3 eiK03 R W 0 1 Enable 0 Mask Interrupt mask register KEY03 P03 D2 eiK02 R W 0 1 Enable 0 Mask Interrupt mask register KEY02 P02 D1 eiK01 R W 0 1 Enable 0 Mask Interrupt mask register KEY01 P01 D0 eiK00 R W 0 1 E...

Page 63: ...R W 0 Interrupt factor flag KEY00 P00 FFFCH 6 D3 iK13 R W 0 1 Occurred R Reset W 0 Not occurred R Invalid W Interrupt factor flag KEY13 P13 D2 iK12 R W 0 Interrupt factor flag KEY12 P12 D1 iK11 R W 0 Interrupt factor flag KEY11 P11 D0 iK10 R W 0 Interrupt factor flag KEY10 P10 FFFDH D3 iRun 6 R W 0 1 Occurred R Reset W 0 Not occurred R Invalid W Interrupt factor flag SW direct RUN D2 ilaP 6 R W 0 ...

Page 64: ... Programmable timer 0 underflow IPT0 FFF2H D1 EIPT0 FFE2H D1 Programmable timer 0 compare match ICTC0 FFF2H D0 EICTC0 FFE2H D0 Programmable timer 1 underflow IPT1 FFF3H D1 EIPT1 FFE3H D1 Programmable timer 1 compare match ICTC1 FFF3H D0 EICTC1 FFE3H D0 Programmable timer 2 underflow IPT2 FFF4H D1 EIPT2 FFE4H D1 Programmable timer 2 compare match ICTC2 FFF4H D0 EICTC2 FFE4H D0 Programmable timer 3 ...

Page 65: ... until both the stack pointers SP1 and SP2 are set with the software Be sure to set the SP1 and SP2 in the initialize routine Further when re setting the stack pointer the SP1 and SP2 must be set as a pair When one of them is set all the interrupts including NMI are masked and interrupts cannot be accepted until the other one is set The interrupt handler routine must be located within the range fr...

Page 66: ...it on and off and to switch the system clock between OSC3 and OSC1 The OSC3 oscillation circuit is used when the CPU and some peripheral circuits need high speed operation Otherwise use the OSC1 oscillation circuit to generate the operating clock and stop the OSC3 oscillation circuit to reduce current consumption Mask Option 7 1 2 In the S1C63004 008 016 the OSC3 oscillator type can be selected fr...

Page 67: ... When ceramic oscillation circuit is selected connect a ceramic resonator Ceramic between the OSC3 and OSC4 terminals and connecting two capacitors CG3 CD3 between the OSC3 terminal and VSS and between the OSC4 terminal and VSS respectively When CR external R is selected connect a resistor RCR between the OSC3 and OSC4 terminals The CR built in R oscillator does not need any external elements Leav...

Page 68: ...003 004 008 016 supports both HALT and SLEEP modes for power saving during standby halT mode The CPU enters HALT mode and stops operating when it executes the HALT instruction However timer coun ters and peripheral circuits continue operating since the oscillation circuit operates in HALT mode Reactivating the CPU from HALT status is done by generating a hardware interrupt request including NMI Sl...

Page 69: ... signal oscillation clock fOSC1 fOSC3 or a dividing clock can be output from the FOUT P13 terminal The FOUT output is controlled using the FOUT 3 0 register When the output clock frequency is selected using FOUT 3 0 the FOUT signal is output from the FOUT terminal The P13 I O port functions are disabled while the FOUT signal is being output Set ting FOUT 3 0 to 0H disables FOUT output and the P13 ...

Page 70: ... written OSC3 oscillation Off Reading Valid When it is necessary to operate the CPU at high speed set OSCC to 1 At other times set it to 0 to reduce current consumption At initial reset this register is set to 0 ClKChG CPu system clock switching register FF00h D3 The CPU s operation clock is selected with this register When 1 is written OSC3 clock is selected When 0 is written OSC1 clock is select...

Page 71: ...on Consequently you should switch the CPU operating clock OSC1 OSC3 after allowing for a sufficient waiting time once the OSC3 oscillation goes on The oscillation start time will vary somewhat de pending on the resonator and externally attached parts Refer to the oscillation start time example indicated in the Electrical Characteristics chapter When switching the clock from OSC3 to OSC1 be sure to...

Page 72: ...ode If a HALT status continues for 3 4 seconds the non maskable interrupt releases the HALT status interrupt Function 8 2 If the watchdog timer is not reset periodically the non maskable interrupt NMI is generated to the core CPU Since this interrupt cannot be masked it is accepted even in the interrupt disable status I flag 0 However it is not accepted when the CPU is in the interrupt mask state ...

Page 73: ...written to the WDEN register the watchdog timer starts count operation When 0 is written the watchdog timer does not count and does not generate the interrupt NMI At initial reset this register is set to 1 Precautions 8 4 When the watchdog timer is being used the software must reset it within 3 second cycles Because the watchdog timer is set in operation state by initial reset set the watchdog tim...

Page 74: ...ly the operating clock to the clock timer 2 1 Controlling clock timer operating clock Table 9 RTCKE Clock timer operating clock 1 fOSC1 128 256 Hz 0 Off If it is not necessary to run the clock timer stop the clock supply by setting RTCKE to 0 to reduce current con sumption Data Read and hold Function 9 3 The 8 bits timer data are allocated to the address FF41H and FF42H FF41H D0 TM0 128 Hz D1 TM1 ...

Page 75: ...Hz 16 Hz 8 Hz 4 Hz 2 Hz 1 Hz At this time the corresponding interrupt factor flag IT0 IT1 IT2 IT3 IT4 IT5 IT6 IT7 is set to 1 The interrupt mask registers EIT0 EIT1 EIT2 EIT3 EIT4 EIT5 EIT6 EIT7 are used to enable or mask each interrupt factor However regardless of the interrupt mask register setting the interrupt factor flag is set to 1 at the falling edge of the corresponding signal Not supporte...

Page 76: ... Stop control register FF40h D0 Controls run stop of the clock timer When 1 is written Run When 0 is written Stop Reading Valid The clock timer starts running when 1 is written to the TMRUN register and stops when 0 is written In stop status the timer data is maintained until the next run status or the timer is reset Also when stop status changes to run status the data that is maintained can be us...

Page 77: ...t be obtained depending on the count data read and count up timings To avoid this problem the clock timer count data should be read by one of the procedures shown below Read the count data twice and verify if there is any difference between them Temporarily stop the clock timer when the counter data is read to obtain proper data When resetting the clock timer TMRST 1 do not start the clock timer T...

Page 78: ... 2 0 LCURF Direct RUN interrupt request Direct LAP interrupt request 1 000 Hz Direct input control SWDIR P01 P00 P02 P03 P10 P13 a S1C63004 008 016 Clock manager SWCKE fOSC1 32 OSC1 oscillation circuit fOSC1 Data bus 1 Hz interrupt request 1 000 1 024 prescaler 1 1 000 sec counter 1 100 sec counter 1 10 sec counter Capture buffer SWD 3 0 reading SWD 7 4 reading SWD 11 8 reading SWRST 10 Hz interru...

Page 79: ... frequency of the prescaler output clock 1 000 Hz 100 Hz generated by SWD 3 0 and 10 Hz generated by SWD 7 4 are approximate values Capture Buffer and hold Function 10 4 The stopwatch timer data 1 1 000 sec 1 100 sec and 1 10 sec can be read from SWD 3 0 FF4BH SWD 7 4 FF4CH and SWD 11 8 FF4DH respectively The counter data are latched in the capture buffer when reading and are held until reading of...

Page 80: ...Count clock 5 1 Operating timing when controlling SWRUN Figure 10 When the direct input function explained in next section is set RUN STOP control is done by an external key input In this case SWRUN becomes read only register that indicates the operating status of the stopwatch timer S1C63004 008 016 Stopwatch timer reset The stopwatch timer is reset when 1 is written to SWRST With this the counte...

Page 81: ...ture buffer and is held The counter continues counting operation Furthermore an interrupt occurs by direct LAP input As stated above the capture buffer data is held until SWD 11 8 is read If the LAP key is input when data has been already held it renews the content of the capture buffer When SWD 11 8 is read after renewing the capture renewal flag is set to 1 In this case the hold status is not re...

Page 82: ...nation 0H None at initial reset 1H P02 2H P02 P03 3H P02 P03 P10 4H P10 5H P10 P11 6H P10 P11 P12 7H P10 P11 P12 P13 RUN or LAP inputs become invalid in the following status 1 The RUN or LAP key is pressed when one or more keys that are included in the selected combination here in after referred to as mask are held down 2 The RUN or LAP key has been pressed when the mask is released fOSC1 32 1 024...

Page 83: ...0 D1 D2 D3 Address Register Stopwatch timer SWD 3 0 timing chart FF4BH 1 1 000 sec BCD D0 D1 D2 D3 Address Register Stopwatch timer SWD 7 4 timing chart Address Register Stopwatch timer SWD 11 8 timing chart 7 1 Timing chart for counters Figure 10 As shown in Figure 10 7 1 the interrupts are generated by the overflow of their respective counters 9 chang ing to 0 Also at this time the corresponding...

Page 84: ... inputs fOSC1 32 1 024 Hz SWRST writing EDIR writing EDIR register Direct RUN input SWRUN writing SWRUN register Direct LAP input Counter data Capture buffer SWD 3 0 reading SWD 7 4 reading SWD 11 8 reading CRNWF 1 Hz interrupt factor flag ISW1 LCURF Direct RUN interrupt Direct LAP interrupt 10 Hz interrupt 1 Hz interrupt 001 002 003 004 005 006 098 099 100 101 102 000 001 002 003 004 005 006 007 ...

Page 85: ...pply by setting SWCKE to 0 to reduce current consumption At initial reset this register is set to 0 eDiR Direct input function enable register FF48h D0 S1C63004 008 016 Enables the direct input RUN LAP function When 1 is written Enabled When 0 is written Disabled Reading Valid The direct input function is enabled by writing 1 to EDIR and then RUN STOP and LAP control can be done by external key in...

Page 86: ...enters the RUN status when 1 is written to SWRUN and the STOP status when 0 is written In the STOP status the timer data is maintained until the next RUN status or resets timer Also when the STOP status changes to the RUN status the data that was maintained can be used for resuming the count RUN STOP control with this register is valid only when the direct input function is set to disable always e...

Page 87: ...f the capture buffer works by reading this data These 4 bits are read only and cannot be used for writing operations At initial reset the timer data is set to 0 SWD 7 4 Stopwatch timer data 1 100 sec FF4Ch Data BCD of the 1 100 sec column of the capture buffer can be read out These 4 bits are read only and cannot be used for writing operations At initial reset the timer data is set to 0 SWD 11 8 S...

Page 88: ...d interrupt signals and resets the counter to its initial value The reload data register is used to set the initial value The underflow signal of Timer 1 S1C63004 008 016 is used as the source clock of the R F converter and serial interface this makes it possible to program a flexible R F converter count clock and the transfer rate of the serial interface Each timer of the S1C63004 008 016 has an ...

Page 89: ... PTRUN2 PTPS2 3 0 Timer function setting fOSC1 16 2 048 Hz fOSC1 FCSEL_B fOSC3 Pulse polarity setting PLPUL_B Output control PTOUT_B Event counter mode setting EVCNT_B Reload data register RLD2 7 0 Compare data register CD2 7 0 8 bit down counter Timer control circuit PWM waveform generator P22 port TOUT_B P23 P23 port Clock manager Interrupt control circuit Output control circuit Data buffer PTD2...

Page 90: ...l component does not affect the IC power supply Refer to Precautions on Mounting in the Appendix for more information Controlling Operating Clock 11 2 The clock manager generates the down count clock for each timer by dividing the OSC1 or OSC3 clock Table 11 2 1 lists the 15 count clocks that can be generated by the clock manager and the clock to be used for each timer can be selected using the co...

Page 91: ...rowing operation between low and high order reading therefore be sure to read the low order data first The counter reloads the initial value set in the reload data register when an underflow occurs through the count down It continues counting down from the initial value after reloading In addition to reloading the counter this underflow signal controls the interrupt generation and pulse TOUT_A TOU...

Page 92: ...jected is 0 48 msec or less when fOSC1 32 768 kHz Figure 11 4 2 shows the count down timing with noise rejector Counter input clock 2 Count data n n 1 n 2 n 3 EVIN_A EVIN_B input 2 048 Hz 1 1 When fOSC1 32 768 kHz 2 When PLPUL_A PLPUL_B register is set to 0 4 2 Count down timing with noise rejector Figure 11 The operation of the event counter mode is the same as the normal timer except it uses the...

Page 93: ...r 0 clock PWM output selection PTSEL1 PTRST0 Data bus Timer 1 reset PTRST1 Timer 0 Run Stop PTRUN0 PTPS0 3 0 Timer function setting fOSC1 16 2 048 Hz fOSC1 FCSEL_A fOSC3 Pulse polarity setting PLPUL_A Output control PTOUT_A Event counter mode setting EVCNT_A Reload data register RLD0 7 0 Compare data register CD0 7 0 Compare data register CD1 7 0 8 bit down counter Reload data register RLD1 7 0 8 ...

Page 94: ...derflow of Timer 1 In this case IPT0 is not set to 1 by a Timer 0 underflow The compare match interrupt uses ICTC1 of Timer 1 The same applies when Ch B is used as a 16 bit timer TOuT Output Control 11 8 The programmable timer Ch A Ch B can generate the TOUT_A TOUT_B signal from the timer underflow and compare match signals The TOUT_A TOUT_B signal is generated by dividing the underflow signal by ...

Page 95: ...erface is calculated by the follow ing expression fCNT1 RLD1x 1 2 bps fCNT1 Timer 1 count clock frequency set by the PTPS1 register See Table 11 2 1 bps Transfer rate 00H can be set to RLD1x Be aware that the maximum clock frequency for the serial interface is limited to 1 MHz when OSC3 is used as the clock source i O Memory of Programmable Timer 11 10 Table 11 10 1 shows the I O addresses and the...

Page 96: ...reload data low order 4 bits RLD10 LSB D2 RlD12 R W 0 D1 RlD11 R W 0 D0 RlD10 R W 0 FF87H 6 D3 RlD17 R W 0 0H FH Programmable timer 1 reload data high order 4 bits RLD17 MSB D2 RlD16 R W 0 D1 RlD15 R W 0 D0 RlD14 R W 0 FF88H D3 PTD03 R 0 0H FH Programmable timer 0 data low order 4 bits PTD00 LSB D2 PTD02 R 0 D1 PTD01 R 0 D0 PTD00 R 0 FF89H D3 PTD07 R 0 0H FH Programmable timer 0 data high order 4 ...

Page 97: ...ble timer 2 data low order 4 bits PTD20 LSB D2 PTD22 R 0 D1 PTD21 R 0 D0 PTD20 R 0 FF99H 6 D3 PTD27 R 0 0H FH Programmable timer 2 data high order 4 bits PTD27 MSB D2 PTD26 R 0 D1 PTD25 R 0 D0 PTD24 R 0 FF9AH 4 D3 PTD33 R 0 0H FH Programmable timer 3 data low order 4 bits PTD30 LSB D2 PTD32 R 0 D1 PTD31 R 0 D0 PTD30 R 0 FF9BH 4 D3 PTD37 R 0 0H FH Programmable timer 3 data high order 4 bits PTD37 M...

Page 98: ... does not include registers at FF19H FF1BH PlPul_a Timer 0 pulse polarity select register FF80h D0 PlPul_B Timer 2 pulse polarity select register FF90h D0 S1C63004 008 016 Selects the count pulse polarity in the event counter mode When 1 is written Rising edge When 0 is written Falling edge Reading Valid The count timing in the event counter mode is selected from either the falling edge of the ext...

Page 99: ... used to select whether Timers 0 and 1 in Ch A or Timers 2 and 3 in Ch B are used as two chan nels of independent 8 bit timers or one channel of combined 16 bit timer When 0 is written to the register the timers are set to 8 bit timer mode When 1 is written the timers are set to 16 bit timer mode When Ch A Ch B is used in 16 bit timer mode Timer 1 Timer 3 operates with the Timer 0 Timer 2 underflo...

Page 100: ... 0 is written the timer outputs the normal clock generated from the underflow signal When Ch A Ch B is set to 16 bit timer mode the PTSEL0 PTSEL2 register for Timer 0 Timer 2 is ineffective At initial reset these registers are set to 0 FF91H D3 in the S1C63004 008 and FF81H D2 D3 in the S1C63003 are read only bits and always 0 will be read The S1C63003 does not include a register at FF91H PTRun0 T...

Page 101: ...high order 4 bits are held by reading the low order 4 bits be sure to read the low order 4 bits first In 16 bit timer mode the high order 12 bits are held by reading the low order 4 bits be sure to read the low order 4 bits first Since these latches are exclusively for reading the writing operation is invalid At initial reset these counter data are set to 00H The S1C63004 008 does not include regi...

Page 102: ... set in off state For the reason below pay attention to the reload data write timing when changing the interval of the programmable timer interrupts while the programmable timer is running The programmable timer counts down at the falling edge of the input clock and at the same time it generates an interrupt if the counter underflows Then it starts loading the reload data to the counter and the co...

Page 103: ...the printed circuit board so that the operation of the external component does not affect the IC power supply Refer to Precautions on Mounting in the Appendix for more information Each I O port terminal provides an internal pull down resistor and it can be connected or disconnected in 1 bit units by mask option When Use is selected by mask option the port suits input from the push switch key matri...

Page 104: ...nction is used the input output direction of the port is automatically config ured by switching the terminal function and the I O control registers becomes ineffective For switching the terminal function and input output control refer to respective peripheral circuit chapter Note Before the port function is configured the circuit that uses the port e g input interrupt multiple key entry reset seri...

Page 105: ...el input interface At initial reset all the ports are configured with a CMOS Schmitt level interface The input interface level select register of the port that is set for a peripheral input functions the same as the I O port The input interface level of the P2 to P5 ports are fixed at a CMOS Schmitt level Pull down During input Mode 12 5 A pull down resistor that activates during the input mode ca...

Page 106: ...0 3 0 PCP1 3 0 are individually provided for the I O ports P00 P03 and P10 P13 The interrupt select registers SIPxx select the ports to be used for generating interrupts or canceling SLEEP mode Writing 1 to an interrupt select register incorporates that port into the key input interrupt generation conditions Changing the port where the interrupt select register has been set to 0 does not affect th...

Page 107: ...nd the control bits for the I O ports 7 1 Control bits of I O ports Table 12 Address Register name R W Default Setting data Function FF11H D3 nRSP11 6 R W 0 3 f1 256 1 f1 16 P1 key input interrupt noise reject frequency selection f1 fOSC1 D2 nRSP10 6 R W 0 2 f1 64 0 Off D1 nRSP01 R W 0 3 f1 256 1 f1 16 P0 key input interrupt noise reject frequency selection f1 fOSC1 D0 nRSP00 R W 0 2 f1 64 0 Off F...

Page 108: ...R W 1 1 Enable 0 Disable P31 pull down control register D0 Pul30 R W 1 1 Enable 0 Disable P30 pull down control register FF30H 5 D3 P43 R W 1 1 High 0 Low P43 I O port data D2 P42 R W 1 1 High 0 Low P42 I O port data D1 P41 R W 1 1 High 0 Low P41 I O port data D0 P40 R W 1 1 High 0 Low P40 I O port data FF31H 5 D3 iOC43 R W 0 1 Output 0 Input P43 I O control register D2 iOC42 R W 0 1 Output 0 Inpu...

Page 109: ...ort terminal When 1 is written as port data the port terminal goes high VDD and when 0 is written the terminal goes low VSS Port data can be written also in the input mode When reading data When 1 is read High level When 0 is read Low level When the I O port is placed into input mode the voltage level being input to the port terminal can be read out When the terminal voltage is high VDD the port d...

Page 110: ...ing Valid These registers enable the built in pull down resistor to be effective during input mode in 1 bit units The pull down resistor is included into the ports selected by mask option By writing 1 to the pull down control register the corresponding I O ports are pulled down during input mode while writing 0 or output mode disables the pull down function At initial reset these registers are all...

Page 111: ...pt at the falling edge of the input signal When 0 is written the I O port generates an interrupt at the rising edge of the input signal At initial reset these registers are set to 1 nRSP0 1 0 Key input interrupt 0 3 noise reject frequency select register FF11h D 1 0 nRSP1 1 0 Key input interrupt 4 7 noise reject frequency select register FF11h D 3 2 S1C63004 008 016 Selects the noise reject freque...

Page 112: ... be used for releasing SLEEP status before executing the SLP instruction Furthermore enable the key input interrupt using the corresponding interrupt mask register EIKxx 1 before executing the SLP instruction to run key input interrupt handler routine after SLEEP status is released Before the port function is configured the circuit that uses the port e g input interrupt multiple key entry reset se...

Page 113: ... selection SIFCKS 2 0 fOSC1 fOSC3 Programmable timer 1 Data bus 1 1 Configuration of serial interface Figure 13 Serial interface Terminals 13 2 The following shows the terminals used in the serial interface and their functions SCLK P30 Inputs or outputs the serial clock By writing 1 to the ESIF register to enable the serial interface the P30 terminal is switched to the SCLK terminal In master mode...

Page 114: ... by the mask options for P32 P30 and P33 When the pull down resistor is not used take care that a floating status does not occur Pull down control when pull down resistor is incorporated When a pull down resistor is incorporated at the serial input terminal the pull down resistor should be en abled disabled using the pull down control register of the I O port SIN terminal PUL32 register SCLK termi...

Page 115: ...SPI slave mode SCLK SOUT SIN SS SCLK SDO SDI SS 4 1 Sample basic connection of serial input output terminals Figure 13 The SMOD ENCS and ESREADY registers are used for setting the mode Master mode SMOD 1 ENCS 0 ESREADY 0 Slave mode SMOD 0 ENCS 1 ESREADY 1 SPI slave mode SMOD 0 ENCS 1 ESREADY 0 Table 13 4 1 lists the combination of mode settings and used terminal configurations 4 1 Mode settings an...

Page 116: ...ates the frequency when fOSC1 32 kHz fOSC3 OSC3 oscillation frequency The maximum clock frequency is limited to 1 MHz When programmable timer 1 is selected the programmable timer 1 underflow signal is divided by 2 before it is used as the synchronous clock In this case the programmable timer must be controlled before operating the serial inter face Refer to the Programmable Timer chapter for contr...

Page 117: ...ng edge of the clock input or output from to the SCLK P30 terminal The data in the shift register is shifted at the falling edge of the SCLK signal when the SCPS0 register is 0 or at the rising edge of the SCLK signal when the SCPS0 register is 1 When the output of the 8 bit data from SD0 to SD7 is completed the interrupt factor flag ISIF is set to 1 and an interrupt occurs Moreover the interrupt ...

Page 118: ...e 1 to the ENCS and ESREADY registers this signal cannot be used in SPI slave mode Output timing of SRDY signal is as follows When positive polarity SCPS1 0 is selected for the synchronous clock The SRDY signal goes 1 high when the S1C63004 008 016 serial interface is ready to transmit or receive data normally it is at 0 low The SRDY signal changes from 0 to 1 immediately after 1 is written to SCT...

Page 119: ...a When SCPS1 0 and SCPS0 0 b When SCPS1 0 and SCPS0 1 c When SCPS1 1 and SCPS0 0 d When SCPS1 1 and SCPS0 1 SCTRG W SCTRG R SCLK SIN 8 bit shift register SOUT ISIF SRDY Slave mode SCTRG W SCTRG R SCLK SIN 8 bit shift register SOUT ISIF SRDY Slave mode SCTRG W SCTRG R SCLK SIN 8 bit shift register SOUT ISIF SRDY Slave mode 6 5 1 Serial interface timing chart Figure 13 ...

Page 120: ... inactive the serial interface does not start data transfer even if the synchronous clock is input to the SCLK terminal SPi master device When using the S1C63004 008 016 as an SPI master device set the serial interface to master mode ESIF 1 SMOD 1 ENCS 0 ESREADY 0 ESOUT 1 when SOUT is used The SS signal output terminal is not available in master mode set an I O port to output mode and use it as th...

Page 121: ...D0 enCS R W 0 1 SRDY_SS 0 P33 SRDY_SS enable P33 port function selection FF5BH 6 D3 SD3 R W 0H FH Serial I F transmit receive data low order 4 bits SD0 LSB D2 SD2 R W D1 SD1 R W D0 SD0 R W FF5CH 6 D3 SD7 R W 0H FH Serial I F transmit receive data high order 4 bits SD7 MSB D2 SD6 R W D1 SD5 R W D0 SD4 R W 1 Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read 4 Unu...

Page 122: ...o input the external clock after the trigger When reading When 1 is read RUN during input output the synchronous clock When 0 is read STOP the synchronous clock stops When this bit is read it indicates the status of serial interface clock After 1 is written to SCTRG this value is latched till serial interface clock stops 8 clock counts Therefore if 1 is read it indicates that the synchronous clock...

Page 123: ...when the SCPS0 register is 0 or at the falling edge of the SCLK signal when the SCPS0 register is 1 When negative polarity SCPS1 1 is selected for the synchronous clock During receiving the serial data is read into the built in shift register at the falling edge of the SCLK signal when the SCPS0 register is 0 or at the rising edge of the SCLK signal when the SCPS0 register is 1 The shift reg ister...

Page 124: ...he serial interface is not running i e the synchronous clock is neither being input or output At initial reset these registers are undefined Precautions 13 9 Perform data writing reading to the data registers SD 7 0 only while the serial interface is not running i e the synchronous clock is neither being input or output As a trigger condition it is required that data writing or reading on data reg...

Page 125: ...led turned on and off by software Mask Option 14 2 SeG GPiO RFC Terminal Configuration 14 2 1 The SEG0 to SEG35 terminals of the S1C63016 the SEG0 to SEG29 terminals of the S1C63008 the SEG0 to SEG19 terminals of the S1C63004 and the SEG0 to SEG9 terminals of the S1C63003 are fixed at segment DC outputs The SEG36 to SEG55 terminals of the S1C63008 016 the SEG40 to SEG55 terminals of the S1C63004 a...

Page 126: ...the external connection diagram when an external supply is used refer to the Power Supply chapter Note that the power control using the LPWR register is necessary even if an external power supply is used Segment Option 14 2 3 Segment allocation Note Refer to Appendix D Mask Data Creation Procedure for mask data creation including segment allocation and precautions The display memory addresses and ...

Page 127: ...N SEG41 n S C N SEG42 n S C N SEG43 n S C N SEG44 n S C N SEG45 n S C N SEG46 n S C N SEG47 n S C N SEG48 n S C N SEG49 n S C N SEG50 n S C N SEG51 n S C N SEG52 n S C N SEG53 n S C N SEG54 n S C N SEG55 n S C N address H RAM data high order address 0 7 Output specification S Segment output L RAM data low order address 0 F C Complementary output D Data bit 0 3 N Nch open drain output Notes for usi...

Page 128: ... n S C N SEG49 n S C N SEG50 n S C N SEG51 n S C N SEG52 n S C N SEG53 n S C N SEG54 n S C N SEG55 n S C N address H RAM data high order address 0 7 Output specification S Segment output L RAM data low order address 0 F C Complementary output D Data bit 0 3 N Nch open drain output Notes for using the segment option generator winsog S1C63008 1 The output specification of SEG0 to SEG29 can be select...

Page 129: ... C N SEG48 n S C N SEG49 n S C N SEG50 n S C N SEG51 n S C N SEG52 n S C N SEG53 n S C N SEG54 n S C N SEG55 n S C N address H RAM data high order address 0 7 Output specification S Segment output L RAM data low order address 0 F C Complementary output D Data bit 0 3 N Nch open drain output Notes for using the segment option generator winsog S1C63004 1 The output specification of SEG0 to SEG19 can...

Page 130: ... N SEG52 n S C N SEG53 n S C N SEG54 n S C N SEG55 n S C N address H RAM data high order address 0 3 Output specification S Segment output L RAM data low order address 0 F C Complementary output D Data bit 0 3 N Nch open drain output Notes for using the segment option generator winsog S1C63003 1 The output specification of SEG0 to SEG9 can be selected from LCD segment output S DC complementary out...

Page 131: ...8 56 8 400 50 8 288 36 8 6 1 7 COM0 COM6 392 56 7 350 50 7 252 36 7 5 1 8 COM0 COM7 448 56 8 400 50 8 288 36 8 4 1 7 COM0 COM6 392 56 7 350 50 7 252 36 7 3 1 6 COM0 COM5 336 56 6 300 50 6 216 36 6 2 1 5 COM0 COM4 280 56 5 250 50 5 180 36 5 110 22 5 1 1 4 COM0 COM3 224 56 4 200 50 4 144 36 4 88 22 4 0 1 3 COM0 COM2 168 56 3 150 50 3 108 36 3 66 22 3 Switching Frame Frequency 14 3 3 The frame freque...

Page 132: ... 1 Drive Waveform 14 3 4 The drive waveforms by duty selection are shown in Figures 14 3 4 1 to 14 3 4 6 COM0 COM1 COM2 COM3 7 LCD lighting status SEGxx VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC2 VC1 VC2 VC1 Not lit Lit COM0 COM1 COM2 SEGxx Frame 3 4 1 LCD drive waveform for 1 3 duty Figure 14 ...

Page 133: ...ical Manual Seiko Epson Corporation 14 9 Rev 1 1 COM0 COM1 COM2 COM3 COM4 7 LCD lighting status SEGxx VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC2 VC1 VC2 VC1 Not lit Lit COM0 COM1 COM2 COM3 SEGxx Frame 3 4 2 LCD drive waveform for 1 4 duty Figure 14 ...

Page 134: ...1C63003 004 008 016 TECHNICAL MANUAL Rev 1 1 COM0 COM1 COM2 COM3 COM4 COM5 7 SEGxx VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC2 VC1 VC2 VC1 Not lit Lit COM0 COM1 COM2 COM3 COM4 SEGxx Frame LCD lighting status 3 4 3 LCD drive waveform for 1 5 duty Figure 14 ...

Page 135: ...pson Corporation 14 11 Rev 1 1 COM0 COM1 COM2 COM3 COM4 COM5 COM6 7 SEGxx VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC2 VC1 Not lit Lit COM0 COM1 COM2 COM3 COM4 COM5 SEGxx Frame VC2 VC1 LCD lighting status 3 4 4 LCD drive waveform for 1 6 duty S1C63004 008 016 Figure 14 ...

Page 136: ...6 TECHNICAL MANUAL Rev 1 1 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEGxx VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC2 VC1 Not lit Lit LCD lighting status SEGxx Frame COM0 COM1 COM2 COM3 COM4 COM5 COM6 VC2 VC1 3 4 5 LCD drive waveform for 1 7 duty S1C63004 008 016 Figure 14 ...

Page 137: ...on Corporation 14 13 Rev 1 1 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEGxx VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC2 VC1 Not lit Lit SEGxx Frame LCD lighting status COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 3 4 6 LCD drive waveform for 1 8 duty S1C63004 008 016 Figure 14 ...

Page 138: ...C1 VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS SEGxx LCD lighting status SEGxx Not lit Lit COM0 COM1 COM7 3 5 1 Static drive waveform Figure 14 COM0 to COM4 in the S1C63003 lCD Contrast adjustment 14 3 6 S1C63004 008 016 The S1C63004 008 016 allows software to adjust the LCD contrast This function is realized by controlling the volt ages VC1 VC2 and VC3 output from the LCD system voltage regulator The con...

Page 139: ...5 6 7 8 9 A B C D E F F000H F010H F020H F030H S1C63003 110 bits R W b S1C63003 4 1 Display memory map Figure 14 The S1C63004 008 016 includes a 128 word memory addresses F000H F07FH and the S1C63003 includes a 64 word memory addresses F000H F03FH Any address can be allocated for a segment output Note however that the number of bits usable as display memory are limited to the size shown above The m...

Page 140: ...ncy affects the display quality We recommend that the frame frequency should be determined after the display quality is evaluated using the actual LCD panel DSPC 1 0 lCD display mode select register FF50h D 1 0 Sets the display mode 5 3 Display mode Table 14 DSPC 1 0 Display mode 3 All on mode 2 All off mode 1 All on mode 0 Normal mode Normal mode The display memory contents are output without bei...

Page 141: ...d from outside by mask option selection this adjustment becomes invalid At initial reset this register is set to 0 Precautions 14 6 Make sure the LCD display is off LPWR 0 before setting the frame frequency If the frame frequency is switched when the LCD display is on LPWR 1 the LCD may not display normally for one frame period after switching The frame frequency affects the display quality We rec...

Page 142: ...o that the operation of the external component does not affect the IC power supply Refer to Precautions on Mounting in the Appendix for more information Controlling Operating Clock 15 2 To generate the buzzer signal the clock for the sound generator must be supplied from the clock manager by writing 1 to the SGCKE register in advance 2 1 Controlling sound generator clock Table 15 SGCKE Sound gener...

Page 143: ... 3276 8 2730 7 2340 6 2048 0 1638 4 1365 3 1170 3 Level 1 Max 0 8 16 8 20 12 24 12 28 Level 2 1 7 16 7 20 11 24 11 28 Level 3 2 6 16 6 20 10 24 10 28 Level 4 3 5 16 5 20 9 24 9 28 Level 5 4 4 16 4 20 8 24 8 28 Level 6 5 3 16 3 20 7 24 7 28 Level 7 6 2 16 2 20 6 24 6 28 Level 8 Min 7 1 16 1 20 5 24 5 28 When the high level output time has been made TH and when the low level output time has been mad...

Page 144: ... 125 msec 125 msec 0 4 5 1 Timing chart for digital envelope Figure 15 One shot output 15 6 The sound generator has a one shot output function for outputting a short duration buzzer signal for key operation sounds and similar effects Either 125 msec or 31 25 msec can be selected by SHTPW register for one shot buzzer signal output time The output of the one shot buzzer is controlled by writing 1 in...

Page 145: ...1170 3 4 2048 0 1 3276 8 Buzzer frequency Hz selection D1 BZFQ1 R W 0 6 1365 3 3 2340 6 0 4096 0 D0 BZFQ0 R W 0 5 1638 4 2 2730 7 FF47H D3 0 3 R 2 Unused D2 BDTY2 R W 0 7 Level 8 4 Level 5 1 Level 2 Buzzer signal duty ratio selection D1 BDTY1 R W 0 6 Level 7 3 Level 4 0 Level 1 max D0 BDTY0 R W 0 5 Level 6 2 Level 3 1 Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when bein...

Page 146: ...M it becomes 125 msec 8 Hz units and when 0 is written it becomes 62 5 msec 16 Hz units At initial reset this register is set to 0 ShTPW One shot buzzer pulse width setting register FF45h D0 Selects the output time of the one shot buzzer When 1 is written 125 msec When 0 is written 31 25 msec Reading Valid Writing 1 to SHTPW causes the one short output time to be set at 125 msec and writing 0 caus...

Page 147: ... is set to 0 BDTY 2 0 Duty level select register FF47h D 2 0 Selects the duty ratio of the buzzer signal as shown in Table 15 7 3 7 3 Duty ratio setting Table 15 Level BDTY 2 0 Duty ratio by buzzer frequency Hz 4096 0 3276 8 2730 7 2340 6 2048 0 1638 4 1365 3 1170 3 Level 1 Max 0 8 16 8 20 12 24 12 28 Level 2 1 7 16 7 20 11 24 11 28 Level 3 2 6 16 6 20 10 24 10 28 Level 4 3 5 16 5 20 9 24 9 28 Lev...

Page 148: ...configuration of the R F converter is shown in Figure 16 1 1 VDD VSS OSC3 oscillation circuit fOSC3 OSC1 oscillation circuit fOSC1 R F converter clock fTCCLK Measurement counter clock fMCCLK REF0 P52 SEN0 P51 RFIN0 P53 Interrupt request Ch 0 oscillation control circuit REF1 VDD VSS SEN1 HUD RFIN1 Ch 1 oscillation control circuit Measurement counter Time base counter Data bus Interrupt control OVTC...

Page 149: ...n 0 P53 P52 and P51 are configured as the RFIN0 REF0 and SEN0 terminals respectively The RFOUT output through the P50 port is effective when 1 is written to the RFOUT register When the RFOUT register is 0 P50 is used as an I O port The table below lists the correspondence between the P50 to P53 terminals and the R F converter input output 3 1 Setting input output terminal functions Table 16 Termin...

Page 150: ...r is oscillating As a result the oscillation frequency can be measured by an oscilloscope or other equipment Since this monitor has no effect on oscillation frequency it can be used to adjust R F conversion accuracy Oscillation waveforms and waveforms output from the RFOUT terminal are shown in Figure 16 3 2 RFIN0 1 terminal RFOUT output Measurement counter clock VDD VSS VDD VSS 3 2 Oscillation wa...

Page 151: ... words the difference between the reference resistance and sensor oscillation frequencies can be found easily For instance if resistance values of the reference resistance and the sensor are equivalent the same value as the initial value before converting into a complement will be obtained as the result The time base counter allows reading of the counter value and presetting of data By saving the ...

Page 152: ...rs and the RFRUNS register is set to 0 and the R F converter circuit stops operation completely Figure 16 4 2 shows a timing chart for the sensor oscillation Interrupt is generated Time up R F converter clock RFRUNS register RFIN0 1 Time base counter clock Time base counter Measurement counter clock RFOUT output Measurement counter 00000H 00001H 00002H n 1 n Number of counts during sensor oscillat...

Page 153: ...unction which allows interrupt to occur when an R F conversion has completed or an error has occurred When the measurement counter reaches 00000H during counting of the reference oscillation both counters stop counting and RFRUNR is set to 0 At the same time the interrupt factor flag IRFR is set to 1 When the time base counter reaches 00000H during counting of the sensor oscillation both counters ...

Page 154: ... oscillate completion interrupt Figure 16 0 x x 4 x 5 1 2 3 FFFFDH FFFFEH FFFFFH 0 y 2 y 1 y x 1 x 2 Oscillation by sensor resistance R F converter clock RFRUNS register Time base counter Measurement counter clock Measurement counter IRFE OVMC Interrupt request Count up x 3 Overflow 5 3 Error interrupt due to measurement counter overflow Figure 16 n 0 FFFFCH FFFFBH n 1 n 2 n 3 m 2 m 1 m 0 Undefine...

Page 155: ...flow error 0 No error Measurement counter overflow flag D1 RFRunR R W 0 1 Run 0 Stop Reference oscillation Run control status D0 RFRunS R W 0 1 Run 0 Stop Sensor oscillation Run control status FF62H D3 MC3 R W 0H FH Measurement counter MC0 MC3 MC0 LSB D2 MC2 R W D1 MC1 R W D0 MC0 R W FF63H D3 MC7 R W 0H FH Measurement counter MC4 MC7 D2 MC6 R W D1 MC5 R W D0 MC4 R W FF64H D3 MC11 R W 0H FH Measure...

Page 156: ...nel and sensor type to perform R F conversion 7 3 Selecting channel and sensor type Table 16 ERF 1 0 Channel and sensor type 3 Ch 1 DC 2 Ch 1 AC 1 Ch 0 DC 0 I O DC R F conversion using a DC bias resistive sensor such as a thermistor AC R F conversion using an AC bias resistive sensor such as a humidity sensor The R F converter channel 0 input output terminals are shared with the I O port P51 P53 B...

Page 157: ...while the R F conversion is being processed and is set to 0 when the R F conversion has completed Writing 0 during an R F conversion stops the CR oscillation When the channel 1 sensor type AC bias and DC bias is changed by ERF 1 0 during reference oscillation RFRUNR is not reset In this case reset RFRUNR by writing 0 RFRUNR is reset when the channel for R F conversion is changed If RFRUNS and RFRU...

Page 158: ...unts down during oscillation of the reference resistance and counts up to 00000H during oscillation of the sensor 00000H needs to be entered in the counter prior to a reference oscillation in order to adjust the CR oscillating time number of clocks of both counts The counter value after a reference oscillation has completed should be read from this register and save it in the memory The saved valu...

Page 159: ...an be determined by means of software whether the supply voltage is normal or has dropped The criteria voltage can be selected from 29 types shown in Table 17 2 1 using the SVDS 4 0 register 2 1 Criteria voltage Table 17 SVDS 4 0 Criteria voltage V SVDS 4 0 Criteria voltage V 1FH 3 20 0FH 1 65 1EH 3 10 0EH 1 60 1DH 3 00 0DH 1 55 1CH 2 90 0CH 1 50 1BH 2 80 0BH 1 45 1AH 2 70 0AH 1 40 19H 2 60 09H 1 ...

Page 160: ...ng register FF05h D2 FF04h Criteria voltage for SVD is set as shown in Table 17 2 1 At initial reset this register is set to 0 SVDOn SVD circuit On Off register FF05h D0 Turns the SVD circuit on and off When 1 is written SVD circuit On When 0 is written SVD circuit Off Reading Valid When SVDON is set to 1 a source voltage detection is executed by the SVD circuit As soon as SVDON is reset to 0 the ...

Page 161: ...e integer multiplier 2 1 Controlling integer multiplier clock Table 18 MDCKE Integer multiplier clock 1 When CLKCHG 0 fOSC1 32 kHz When OSCC 1 CLKCHG 1 fOSC3 0 Off If it is not necessary to run the integer multiplier stop the clock supply by setting MDCKE to 0 to reduce current consumption Multiplication Mode 18 3 To perform a multiplication set the multiplier to the source register SR and the mul...

Page 162: ...intains the dividend because the quotient overflows the 8 bit To get the correct results when an overflow has occurred perform the division with two steps as shown below 1 Divide the high order 8 bits of the dividend 24H by the divisor 13H and then store the quotient 01H to memory DRH DRL dividend SR divisor DRL quotient DRH remainder NF VF ZF 0024H 13H 01H 11H 0 0 0 2 Keep the remainder 11H in DR...

Page 163: ... FH Source register low order 4 bits SR0 LSB D2 SR2 R W D1 SR1 R W D0 SR0 R W FF71H 5 D3 SR7 R W 0H FH Source register high order 4 bits SR7 MSB D2 SR6 R W D1 SR5 R W D0 SR4 R W FF72H 5 D3 DRl3 R W 0H FH Low order 8 bit destination register low order 4 bits DRL0 LSB D2 DRl2 R W D1 DRl1 R W D0 DRl0 R W FF73H 5 D3 DRl7 R W 0H FH Low order 8 bit destination register high order 4 bits DRL7 MSB D2 DRl6...

Page 164: ... pro cess the quotient is not loaded and the low order 8 bits of the dividend remains At initial reset this register is undefined DRh 7 0 Destination register high order 8 bits FF75h FF74h Used to set high order 8 bits of dividends Set the low order 4 bits of data to DRH 3 0 and the high order 4 bits to DRH 7 4 At the start of a multiplication by writing 0 to FF76H D0 the contents in this register...

Page 165: ...ve flag FF76h D3 Indicates whether the operation result is a positive value or a negative value When 1 is read Negative value MSB of the results is 1 When 0 is read Positive value MSB of the results is 0 Writing Invalid NF is a read only bit so writing operation is invalid At initial reset this flag is set to 0 Precautions 18 7 An operation process takes 10 CPU clock cycles 5 bus cycles after writ...

Page 166: ...ut voltage VI 0 3 to VDD 0 3 V Output voltage VO 0 3 to VDD 0 3 V High level output current IOH 1 pin 5 mA Total of all pins 20 mA Low level output current IOL 1 pin 5 mA Total of all pins 20 mA Permissible loss 1 PD 200 mW Operating temperature Ta 40 to 85 C Storage temperature Tstg 65 to 150 C Soldering temperature time Tsol 260 C 10 seconds lead section 1 In case of plastic package QFP12 48pin ...

Page 167: ... capacitance CIN VIN 0V Ta 25 C RESET RFIN1 Pxx 15 pF Common output current IOH2 VOH2 VC3 0 05V COM0 to COM7 10 µA IOL2 VOL2 VSS 0 05V 10 µA Segment output current during LCD output IOH3 VOH3 VC3 0 05V SEG0 to SEG55 10 µA IOL3 VOL3 VSS 0 05V 10 µA Segment output current during DC output IOH4 VOH4 0 8VDD SEG0 to SEG35 330 µA IOL4 VOL4 0 2VDD 330 µA 1 When CMOS level is selected as the input interfa...

Page 168: ...3 0 BH 3 67 V LC 3 0 CH 3 75 V LC 3 0 DH 3 83 V LC 3 0 EH 3 91 V LC 3 0 FH 4 00 V Notes Depending on the panel load when VDD is 1 2 V or lower the LCD drive voltage does not measure up to the specifications above Contrast settings to set VC1 Max VDD are impossible as the VC1 voltage is always lower than VDD See LCD drive voltage supply voltage characteristic 1 3 bias VC1 reference 1 5 V low voltag...

Page 169: ...he 1 5 V low voltage type as the maximum operating voltage is 1 7 V Depending on the panel load when VDD is 2 0 V or lower the LCD drive voltage does not measure up to the specifications above SVD circuit 19 4 2 S1C63004 008 016 Unless otherwise specified VDD 1 1 to 1 7V 1 5V type or VDD 1 8 to 5 5V 3V type VSS 0V Ta 25 C Item Symbol Condition Min Typ Max Unit SVD voltage VSVD SVDS 4 0 00H Typ 0 9...

Page 170: ...aracteristic value may increase due to variations in oscillation frequency caused by leak age current if the oscillation frequency is 1 kHz or lower 2 In these characteristics unevenness between production lots and variations in board resistances and capacitances used in the measurement environment are taken into account variations in temperature are not included 3 The CR oscillation can be perfor...

Page 171: ...1 ON OSC3 OFF 0 1 0 5 µA Current consumption in HALT IHALT1 OSC1 32kHz Crystal OSC3 OFF 0 5 1 5 µA IHALT2 5 OSC1 32kHz Crystal OSC3 1MHz Ceramic 15 30 µA IHALT3 5 OSC1 32kHz Crystal OSC3 500kHz CR external R 22 50 µA IHALT4 5 OSC1 32kHz Crystal OSC3 500kHz CR built in R 10 22 µA Current consumption during execution IEXE1 OSC1 32kHz Crystal OSC3 OFF CPUclk OSC1 2 0 4 5 µA IEXE2 5 OSC1 32kHz Crystal...

Page 172: ...ol Condition Min Typ Max Unit Oscillation start time tsta 1 ms 1 5 V low voltage type Unless otherwise specified VDD 1 1 to 1 7V VSS 0V Ta 25 C CG3 CD3 30pF Item Symbol Condition Min Typ Max Unit Oscillation start time tsta 3 ms OSC3 CR oscillation circuit external R type S1C63004 008 016 3 V normal type Unless otherwise specified VDD 1 8 to 5 5V VSS 0V Ta 25 C Item Symbol Condition Min Typ Max Un...

Page 173: ... ns Note that the maximum clock frequency is limited to 1 MHz Slave mode Unless otherwise specified VDD 1 5V 1 5V type or 3 0V 3V type VSS 0V Ta 40 to 85 C VIH 0 8VDD VIL 0 2VDD VOH 0 8VDD VOL 0 2VDD Item Symbol Min Typ Max Unit Transmit data output delay time tSSD 200 ns Receive data input set up time tSSS 400 ns Receive data input hold time tSSH 200 ns Note that the maximum clock frequency is li...

Page 174: ...ence value 19 8 high level output current voltage characteristic 3 V normal type Ta 85 C Max value 0 0 0 2 4 6 8 10 12 14 16 18 20 0 2 0 4 0 6 0 8 1 0 VDD VOH V VDD 1 8 V VDD 3 6 V I OH mA VDD 2 4 V VDD 5 5 V 1 5 V low voltage type Ta 85 C Max value 0 0 0 1 2 3 4 5 6 0 2 0 4 0 6 0 8 1 0 VDD VOH V VDD 1 1 V VDD 1 5 V I OH mA VDD 1 7 V ...

Page 175: ...0 2 0 3 0 4 0 5 0 6 VOL V VDD 1 8 V I OL mA VDD 3 6 V VDD 2 4 V VDD 5 5 V 1 5 V low voltage type Ta 85 C Min value 0 0 6 5 4 3 2 1 0 0 1 0 2 0 3 0 4 0 5 0 6 VOL V VDD 1 1 V I OL mA VDD 1 5 V VDD 1 7 V lCD drive voltage supply voltage characteristic 1 3 bias VC2 reference S1C63004 008 016 3 V normal type Ta 25 C Typ value 5 0 4 0 3 0 2 0 VDD V V C3 V 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 LCx FH L...

Page 176: ...25 C Typ value 5 0 4 0 3 0 2 0 VDD V V C3 V 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 lCD drive voltage supply voltage characteristic 1 3 bias VC1 reference S1C63004 008 016 3 V normal type Ta 25 C Typ value 5 0 4 0 3 0 2 0 VDD V V C3 V 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 LCx FH LCx 8H LCx 0H 1 5 V low voltage type Ta 25 C Typ value 5 0 4 0 3 0 2 0 VDD V V C3 V 1 0 1 2 1 4 1 6 1 8 LCx FH LCx 8H ...

Page 177: ...yp value 5 0 4 0 3 0 2 0 VDD V V C3 V 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 1 5 V low voltage type Ta 25 C Typ value 5 0 4 0 3 0 2 0 VDD V V C3 V 1 0 1 2 1 4 1 6 1 8 lCD drive voltage ambient temperature characteristic 1 3 bias VC2 VC1 reference S1C63004 008 016 VDD 3 0 V Typ value 50 1 05VC3 1 04VC3 1 03VC3 1 02VC3 1 01VC3 1 00VC3 0 99VC3 0 98VC3 0 97VC3 0 96VC3 0 95VC3 0 94VC3 25 0 25 50 75 10...

Page 178: ...97VC3 0 96VC3 0 95VC3 0 94VC3 25 0 25 50 75 100 Ta C V C3 V lCD drive voltage load characteristic 1 3 bias S1C63004 008 016 When a load is connected to VC3 terminal only LCx FH Ta 25 C Typ value 0 4 40 4 20 4 00 3 80 3 60 3 40 5 10 15 20 IVC3 µA V C3 V VC2 reference VC1 reference lCD drive voltage load characteristic 1 3 bias S1C63003 When a load is connected to VC3 terminal only Ta 25 C Typ value...

Page 179: ...VSVD 25 0 25 50 75 100 Ta C V SVD V halT state current consumption temperature characteristic during operation with OSC1 Crystal oscillation fOSC1 32 768 khz VDD 5 5 V OSC3 OFF Clock manager OFF Typ value 50 1 4 1 2 1 0 0 8 0 6 0 4 0 2 0 25 0 25 50 75 100 Ta C I HALT1 µA Run state current consumption temperature characteristic during operation with OSC1 Crystal oscillation fOSC1 32 768 khz VDD 5 5...

Page 180: ...cy MHz 0 5 0 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 250 200 150 100 50 0 I EXE2 µA Run state current consumption resistor characteristic during operation with OSC3 CR oscillation external R S1C63004 008 016 VDD 5 5 V Ta 25 C Typ value 10 500 400 300 200 100 0 100 1000 RCR3 kΩ I EXE3 µA Oscillation frequency resistor characteristic OSC3 CR oscillation external R S1C63004 008 016 3 V normal type VDD 5 5 V ...

Page 181: ...RCR3 kΩ f OSC3 kHz Oscillation frequency temperature characteristic OSC3 CR oscillation external R S1C63004 008 016 RCR3 40 kW Typ value 50 25 25 50 0 75 100 Ta C f OSC3 kHz 10000 1000 100 10 Run state current consumption temperature characteristic during operation with OSC3 CR oscillation built in R S1C63004 008 016 VDD 5 5 V Typ value 50 100 75 50 25 0 25 0 25 50 75 100 Ta C I EXE4 µA ...

Page 182: ...VDD 5 5 V Typ value 50 100 75 50 25 0 25 0 25 50 75 100 Ta C I EXE5 µA Oscillation frequency temperature characteristic OSC3 CR oscillation built in R S1C63004 008 016 VDD 5 5 V Typ value 50 650 600 550 500 450 400 350 25 0 25 50 75 100 Ta C f OSC3 kHz Oscillation frequency temperature characteristic OSC3 CR oscillation built in R S1C63003 VDD 5 5 V Typ value 50 650 600 550 500 450 400 350 25 0 25...

Page 183: ...SEN 1000 pF Ta 25 C Typ value 0 1 10 100 1 000 10 000 10 000 1 000 100 10 1 0 RREF RSEN kΩ f RFCLK kHz VDD 1 8 V VDD 3 6 V VDD 5 5 V IC deviation 1 10 100 10 000 1 000 100 10 1 RREF RSEN kΩ f RFCLK kHz VDD 1 8 V VDD 3 6 V VDD 5 5 V IC deviation 1 5 V low voltage type CSEN 1000 pF Ta 25 C Typ value 0 1 10 100 1 000 10 000 10 000 1 000 100 10 1 0 RREF RSEN kΩ f RFCLK kHz VDD 1 1 V VDD 1 5 V VDD 1 7 ...

Page 184: ... 5 V VDD 1 7 V IC deviation RFC reference sensor oscillation frequency resistance characteristic aC oscillation mode 3 V normal type CSEN 1000 pF Ta 25 C Typ value 0 1 10 100 1 000 10 000 10 000 1 000 100 10 1 0 RREF RSEN kΩ f RFCLK kHz VDD 1 8 V VDD 3 6 V VDD 5 5 V IC deviation 1 10 100 10 000 1 000 100 10 1 RREF RSEN kΩ f RFCLK kHz VDD 1 8 V VDD 3 6 V VDD 5 5 V IC deviation ...

Page 185: ...0 RREF RSEN kΩ f RFCLK kHz VDD 1 1 V VDD 1 5 V VDD 1 7 V IC deviation 1 10 100 10 000 1 000 100 10 1 RREF RSEN kΩ f RFCLK kHz VDD 1 1 V VDD 1 5 V VDD 1 7 V IC deviation RFC reference sensor oscillation frequency capacitance characteristic DC aC oscillation mode 3 V normal type RSEN 100 kW Ta 25 C Typ value 10 100 1 000 10 000 1 000 100 10 1 0 CRFC pF f RFCLK kHz IC deviation VDD 1 8 V VDD 3 6 V VD...

Page 186: ...25 C Typ value 10 100 1 000 10 000 1 000 100 10 1 0 CRFC pF f RFCLK kHz IC deviation VDD 1 1 V VDD 1 5 V VDD 1 7 V RFC reference sensor oscillation frequency current consumption characteristic DC aC oscillation mode CRFC 1000 pF Ta 25 C Typ value 0 001 0 01 0 1 1 10 100 1 000 fRFC kHz I RFC µA 10 000 1 000 100 10 1 VDD 1 7 V VDD 3 6 V VDD 5 5 V ...

Page 187: ...ommended value 32 768 kHz 0 to 25 pF 4 MHz 3 V model 1 MHz 1 5 V model 30 pF Ceramic oscillation 30 pF Ceramic oscillation 0 1 µF 0 1 µF 0 1 µF 0 1 µF 0 1 µF 0 1 µF 3 3 µF 0 47 µF 5 5 V 1 8 V or 1 7 V 1 1 V X tal Ceramic LCD panel S1C630xx The potential of the substrate back of the chip is VSS RTMP RREF1 RHUD RREF2 RFOUT P50 SEN0 P51 REF0 P52 RFIN0 P53 HUD SEN1 REF1 RFIN1 CG1 C1 C2 C3 C4 C5 C6 Cre...

Page 188: ...C2 0 VC1 VC regulator reference voltage selection D0 lPWR R W 0 1 On 0 Off VC regulator On Off FF04H FF05H SVD Circuit Address Register name R W Default Setting data Function FF04H 6 D3 SVDS3 R W 0 1F 1E 1D 1C 1B 3 20 3 10 3 00 2 90 2 80 1A 19 18 17 16 2 70 2 60 2 50 2 40 2 30 15 14 13 12 11 2 20 2 10 2 00 1 90 1 80 10 F E D C 1 70 1 65 1 60 1 55 1 50 B A 9 8 7 1 45 1 40 1 35 1 30 1 25 6 5 4 3 2 1...

Page 189: ...3 256 4 f1 16 0 Off FF20H FF3FH I O Ports Address Register name R W Default Setting data Function FF20H D3 P03 R W 1 1 High 0 Low P03 I O port data D2 P02 R W 1 1 High 0 Low P02 I O port data D1 P01 R W 1 1 High 0 Low P01 I O port data D0 P00 R W 1 1 High 0 Low P00 I O port data FF21H D3 iOC03 R W 0 1 Output 0 Input P03 I O control register D2 iOC02 R W 0 1 Output 0 Input P02 I O control register ...

Page 190: ...pull down control register D2 Pul42 R W 1 1 Enable 0 Disable P42 pull down control register D1 Pul41 R W 1 1 Enable 0 Disable P41 pull down control register D0 Pul40 R W 1 1 Enable 0 Disable P40 pull down control register FF34H D3 P53 R W 1 1 High 0 Low P53 I O port data D2 P52 R W 1 1 High 0 Low P52 I O port data D1 P51 R W 1 1 High 0 Low P51 I O port data D0 P50 R W 1 1 High 0 Low P50 I O port d...

Page 191: ...125 msec 0 31 25 msec 1 shot buzzer pulse width setting FF46H D3 0 3 R 2 Unused D2 BZFQ2 R W 0 7 1170 3 4 2048 0 1 3276 8 Buzzer frequency Hz selection D1 BZFQ1 R W 0 6 1365 3 3 2340 6 0 4096 0 D0 BZFQ0 R W 0 5 1638 4 2 2730 7 FF47H D3 0 3 R 2 Unused D2 BDTY2 R W 0 7 Level 8 4 Level 5 1 Level 2 Buzzer signal duty ratio selection D1 BDTY1 R W 0 6 Level 7 3 Level 4 0 Level 1 max D0 BDTY0 R W 0 5 Lev...

Page 192: ...ata input output permutation D0 SMOD R W 0 1 Master 0 Slave Serial I F mode selection FF5AH 6 D3 0 3 R 2 Unused D2 0 3 R 2 Unused D1 eSReaDY R W 0 1 SRDY 0 SS SRDY_SS function selection ENCS 1 D0 enCS R W 0 1 SRDY_SS 0 P33 SRDY_SS enable P33 port function selection FF5BH 6 D3 SD3 R W 0H FH Serial I F transmit receive data low order 4 bits SD0 LSB D2 SD2 R W D1 SD1 R W D0 SD0 R W FF5CH 6 D3 SD7 R W...

Page 193: ...r Multiplier Address Register name R W Default Setting data Function FF70H 5 D3 SR3 R W 0H FH Source register low order 4 bits SR0 LSB D2 SR2 R W D1 SR1 R W D0 SR0 R W FF71H 5 D3 SR7 R W 0H FH Source register high order 4 bits SR7 MSB D2 SR6 R W D1 SR5 R W D0 SR4 R W FF72H 5 D3 DRl3 R W 0H FH Low order 8 bit destination register low order 4 bits DRL0 LSB D2 DRl2 R W D1 DRl1 R W D0 DRl0 R W FF73H 5...

Page 194: ...R W 0 FF85H D3 RlD07 R W 0 0H FH Programmable timer 0 reload data high order 4 bits RLD07 MSB D2 RlD06 R W 0 D1 RlD05 R W 0 D0 RlD04 R W 0 FF86H 6 D3 RlD13 R W 0 0H FH Programmable timer 1 reload data low order 4 bits RLD10 LSB D2 RlD12 R W 0 D1 RlD11 R W 0 D0 RlD10 R W 0 FF87H 6 D3 RlD17 R W 0 0H FH Programmable timer 1 reload data high order 4 bits RLD17 MSB D2 RlD16 R W 0 D1 RlD15 R W 0 D0 RlD1...

Page 195: ...3 RlD27 R W 0 0H FH Programmable timer 2 reload data high order 4 bits RLD27 MSB D2 RlD26 R W 0 D1 RlD25 R W 0 D0 RlD24 R W 0 FF96H 4 D3 RlD33 R W 0 0H FH Programmable timer 3 reload data low order 4 bits RLD30 LSB D2 RlD32 R W 0 D1 RlD31 R W 0 D0 RlD30 R W 0 FF97H 4 D3 RlD37 R W 0 0H FH Programmable timer 3 reload data high order 4 bits RLD37 MSB D2 RlD36 R W 0 D1 RlD35 R W 0 D0 RlD34 R W 0 FF98H...

Page 196: ...e 0 Mask Interrupt mask register KEY12 P12 D1 eiK11 R W 0 1 Enable 0 Mask Interrupt mask register KEY11 P11 D0 eiK10 R W 0 1 Enable 0 Mask Interrupt mask register KEY10 P10 FFEDH D3 eiRun 6 R W 0 1 Enable 0 Mask Interrupt mask register SW direct RUN D2 eilaP 6 R W 0 1 Enable 0 Mask Interrupt mask register SW direct LAP D1 eiSW1 R W 0 1 Enable 0 Mask Interrupt mask register Stopwatch 1 Hz D0 eiSW10...

Page 197: ...t W 0 Not occurred R Invalid W Interrupt factor flag KEY13 P13 D2 iK12 R W 0 Interrupt factor flag KEY12 P12 D1 iK11 R W 0 Interrupt factor flag KEY11 P11 D0 iK10 R W 0 Interrupt factor flag KEY10 P10 FFFDH D3 iRun 6 R W 0 1 Occurred R Reset W 0 Not occurred R Invalid W Interrupt factor flag SW direct RUN D2 ilaP 6 R W 0 Interrupt factor flag SW direct LAP D1 iSW1 R W 0 Interrupt factor flag Stopw...

Page 198: ...t data please see Section B 3 Please refer to the S5U1C63000H manual for detailed information on the ICE functions and method of use Note The S5U1C63000P1 cannot be used for developing the S1C63003 004 008 016 applications names and Functions of each Part B 1 S5u1C63000P6 B 1 1 The S5U1C63000P6 board provides peripheral circuit functions of S1C63 Family microcomputers other than the core CPU The f...

Page 199: ...e VC1 9 LPWR VC regulator On VC regulator Off 10 SVDON SVD circuit On SVD circuit Off 11 SVDS0 SVD criteria voltage level 12 SVDS1 13 SVDS2 14 SVDS3 15 SVDS4 16 4 CR oscillation frequency adjusting control This control is used to adjust the OSC3 oscillation frequency This function is effective only when CR oscillation is selected for the OSC3 oscillation circuit by mask option The oscillation freq...

Page 200: ...sk option Note however that the LCD drive voltage of the actual IC must be controlled using the LCD contrast adjustment register S5u1C6F016P2 B 1 2 The S5U1C6F016P2 board provides the R F converter function that supports resistive sensors such as a thermistor and resistive humidity sensors the SVD function and the P50 P53 port inputs outputs The following explains the names and functions of each p...

Page 201: ...t these switches do not change the actual power supply voltage These switches are intended to be used only for changing the detection results to debug whether the SVD routine works normally or not 1 2 1 Relationship between SW1 SW2 settings and SVDS register Table B Switch settings Supply voltage emulation level SW1 SW2 0 DETECTION Voltage level SVDS 3 0 0 1 DETECTION SVDS 3 0 0 Voltage level SVDS...

Page 202: ...P2 board Set the jig included with the ICE into position as shown in Figure B 2 2 Using this jig as a lever push it toward the inside of the board evenly on the left and right sides After confirming that the board has been firmly fitted into the internal slot of the ICE remove the jig 2 2 Installing the board Figure B Dismounting the S5u1C63000P6 6F016P2 board Set the jig included with the ICE int...

Page 203: ...onnected 23 Cannot be connected 4 Cannot be connected 24 P21 4 Cannot be connected 24 Cannot be connected 5 Cannot be connected 25 P22 5 Cannot be connected 25 Cannot be connected 6 Cannot be connected 26 P23 6 Cannot be connected 26 Cannot be connected 7 Cannot be connected 27 P30 7 Cannot be connected 27 Cannot be connected 8 Cannot be connected 28 P31 8 Cannot be connected 28 Cannot be connecte...

Page 204: ...connected 48 Cannot be connected 24 SEG17 DC 49 Cannot be connected 24 Cannot be connected 49 Cannot be connected 25 SEG18 DC 50 Cannot be connected 25 Cannot be connected 50 Cannot be connected The CN2 1 connector outputs the signals from the SEG pins that have been configured as DC outputs by mask option Do not connect anything to the SEG pins that have been configured as LCD drive outputs 2 3 S...

Page 205: ... 46 SEG32 SEG35 50 pin LC1 1 No 39 44 SEG30 SEG35 Downloading to S5u1C63000P6 B 3 Note The S1C630 Series circuit data is available only for the S5U1C63000P6 and it cannot be down loaded to the previous S5U1C63000P1 board Downloading Circuit Data when new iCe S5u1C63000h2 S5u1C63000h6 is used The S5U1C63000P6 board comes with the FPGA that contains factory inspection data therefore the circuit data...

Page 206: ...lity Port protective diode All I O ports incorporate a protective diode for VDD and VSS and the interface signals between this tool and the target system are set to 3 3 V Therefore this tool and the target system cannot be interfaced with voltages ex ceeding VDD by setting the output ports for open drain mode Pull down resistance value The pull down resistance values on this tool are set to 220 kW...

Page 207: ...ired before oscillation stabilizes after the OSC3 oscillation control circuit OSCC is turned on In this tool even when OSC3 oscillation is changed CLKCHG without a wait time OSC3 will function normally Refer to Electrical Characteristics when setting the appropriate wait time for the actual IC Use separate instructions to switch the clock from OSC3 to OSC1 and to turn off the OSC3 oscillation circ...

Page 208: ...running mode supported by S5U1C63000H1 2 only i O ports Do not set the P0x ports used for multiple key entry reset to output mode as this tool may be reset R F converter The R F converter function is implemented using the S1C6F016 chip included in the S5U1C6F016P2 board If the debugger makes program execution to break while the R F converter is counting the oscillation the R F converter does not s...

Page 209: ...00 171 F Cable connector 50 pin 3M7950 6500SC 1 pair Cable 50 conductor flat cable 1 pair Interface CMOS interface 3 3 V Length Approx 40 cm accessories 40 pin connector for connecting to target system 3M3432 6002LCPL 2 50 pin connector for connecting to target system 3M3433 6002LCPL 2 Specifications of S5u1C6F016P2 B 5 2 S5u1C6F016P2 Dimension 254 mm width 144 8 mm depth 13 mm height including sc...

Page 210: ... 128 Watchdog timer Gate fOSC1 or fOSC3 Integer multiplier 2 Gate fOSC1 1 128 Stopwatch timer Gate fOSC1 fOSC1 1 128 Sound generator Gate fOSC1 1 16 LCD system voltage regulator booster Gate Gate fOSC1 1 16 1 256 P0 key input interrupt noise rejector Gate fOSC1 1 16 1 256 P1 key input interrupt noise rejector 3 Gate fOSC1 1 1 1 256 fOSC3 1 1 1 256 Programmable timer 0 Gate fOSC1 1 1 1 256 fOSC3 1 ...

Page 211: ...he status in place at the time of the HALT instruction enabling use of peripheral circuits for timers and interrupts You can reduce power consumption even further by suspending unnecessary oscillation circuit and peripheral circuits before executing the HALT instruction The CPU is started from HALT mode by an interrupt from a port or the peripheral circuit operating in HALT mode Peripheral circuit...

Page 212: ... with the OSC1 clock Started up by an interrupt from the clock timer stopwatch timer watchdog timer or a peripheral circuit being operated with an OSC1 dividing clock 3 Startup by a peripheral circuit Started up by a peripheral circuit interrupt Power Saving by Power Supply Control C 2 The available power supply controls are listed below internal operating voltage regulator Note that turning on in...

Page 213: ... D Function Option File Creation Procedure D 2 The following shows a procedure to create a function option file 1 Launch the function option generator winfog exe 2 Load the device information definition file INI Select Device INI select from the Tool T menu or click the Device INI select button When the dialog box appears select the folder and file INI for the target model Folder 630xx 2 File 630x...

Page 214: ... 3 1 Assignment must be performed within the assignable area only Area that cannot be assigned unavailable SEG terminals Fixed specification area 3 1 Sample segment assignment area Figure D 5 Segment assignment Assign addresses data bits to the assignable area according to the system design 6 Generate the segment option files SDC SSA Select Generate G from the Tool T menu or click the Generate but...

Page 215: ...n the dialog box that appears in Step 3 The mask data file will be generated For details of the function option generator segment option generator and mask data checker refer to the S5U1C63000A Manual 1 When mask data has already been created using an earlier version of device information definition file Refer to the segment option for each model described in this manual and check that there is no...

Page 216: ...r VDD and VC3 VC2 and supply a voltage within 1 1 V to 1 7 V to the VDD terminal Do not use the VD1 VOSC and VC1 to VC3 terminal output voltages to drive external circuits The LCD system voltage regulator takes about 100 msec for stabilizing the LCD drive voltages after writing 1 to LPWR Do not select the reference voltage VC2 for the S1C63003 1 5 V low voltage type Current consumption increases i...

Page 217: ...PU clock Therefore the correct value may not be ob tained depending on the count data read and count up timings To avoid this problem the clock timer count data should be read by one of the procedures shown below Read the count data twice and verify if there is any difference between them Temporarily stop the clock timer when the counter data is read to obtain proper data When resetting the clock ...

Page 218: ...own at the falling edge of the input clock and at the same time it generates an interrupt if the counter underflows Then it starts loading the reload data to the counter and the counter data is determined at the next rising edge of the input clock period shown in as in the figure Count clock Counter data continuous mode Reload data 25H 03H 02H 01H 00H 25H 24H Counter data is determined by reloadin...

Page 219: ... multiple times as leads to malfunctioning Moreover when the synchronous clock SCLK is ex ternal clock start to input the external clock after the trigger Setting of the input output permutation MSB first LSB first with the SDP register should be done before set ting data to SD 7 0 Be aware that the maximum clock frequency for the serial interface is limited to 1 MHz when the program mable timer i...

Page 220: ...peration is in process do not read write from to the destination register DRH DRL and do not read NF VF ZF Precautions on Mounting e 2 Oscillation circuit Oscillation characteristics change depending on conditions board pattern components used etc In particular when a ceramic oscillator or crystal oscillator is used use the oscillator manufacturer s recom mended values for constants such as capaci...

Page 221: ...e an external component that con sumes a large amount of current the operation of the external component affects the built in power supply circuit of this IC and the output voltage may vary When driving a bipolar transistor by a periodic signal such as the BZ or timer output in particular it may cause variations in the voltage output from the LCD system voltage circuit that affects the contrast of...

Page 222: ...on Old Note Refer to Generating S1C63003 Mask Data in the Appendix when generating an application using the S1C63003 New Note Refer to Appendix D Mask Data Creation Procedure for mask data creation including seg ment allocation and precautions AP D 1 to 3 Appendix D Mask Data Creation Procedure Replaced all the contents ...

Page 223: ...57 CHINA Phone 86 755 2699 3828 Fax 86 755 2699 3838 EPSON HONG KONG LTD Unit 715 723 7 F Trade Square 681 Cheung Sha Wan Road Kowloon Hong Kong Phone 852 2585 4600 Fax 852 2827 4346 EPSON TAIWAN TECHNOLOGY TRADING LTD 14F No 7 Song Ren Road Taipei 110 TAIWAN Phone 886 2 8786 6688 Fax 886 2 8786 6660 EPSON SINGAPORE PTE LTD 1 HarbourFront Place 03 02 HarbourFront Tower One Singapore 098633 Phone 6...

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