7 OSCillaTiOn CiRCuiT anD ClOCK COnTROl
7-4
Seiko epson Corporation
S1C63003/004/008/016 TeChniCal Manual
(Rev. 1.1)
7a. Make sure the P0x (P1x) port input level is high when P0x (P1x) port interrupt polarity select register = "1"
(generates an interrupt request at the falling edge).
7b. Make sure the P0x (P1x) port input level is low when P0x (P1x) port interrupt polarity select register = "0"
(generates an interrupt request at the rising edge).
8. Execute the SLP instruction.
When SLEEP status is canceled by an I/O port interrupt, the CPU restarts operating (input port interrupt process-
ing) after waiting for oscillation to stabilize. Refer to the "S1C63000 Core CPU Manual" for transition to HALT/
SLEEP mode and timing of its cancellation.
Control of Peripheral Circuit Clocks
7.4
The S1C63003/004/008/016 incorporates a clock manager that generates operating clocks by dividing the OSC1/
OSC3 clock output from the oscillation circuit and supplies the clocks to the peripheral circuits. Some peripheral cir-
cuits can select the operating clock to be used from several dividing clocks in the clock manager. If the current process-
ing does not use peripheral circuits, the clock supply to those circuits can be stopped in the clock manager. Disabling
unnecessary clocks to be supplied or operating the peripheral circuits with a clock as low frequency as possible can
reduce current consumption. For controlling the clock manager, see the descriptions in each peripheral circuit.
Clock Output (FOuT)
7.5
In order for the S1C63003/004/008/016 to provide a clock signal to an external device, the FOUT signal (oscillation
clock f
OSC1
, f
OSC3,
or a dividing clock) can be output from the FOUT (P13) terminal. The FOUT output is controlled
using the FOUT[3:0] register. When the output clock frequency is selected using FOUT[3:0], the FOUT signal is
output from the FOUT terminal. The P13 I/O port functions are disabled while the FOUT signal is being output. Set-
ting FOUT[3:0] to 0H disables FOUT output and the P13 port is configured as a general-purpose input/output port.
The FOUT signal frequency can be selected from among 15 settings as shown in Table 7.5.1.
5.1 FOUT frequency selection
Table 7.
FOUT[3:0]
FOUT frequency
FH
f
OSC3
EH
f
OSC3
/ 2
DH
f
OSC3
/ 4
CH
f
OSC3
/ 8
BH
f
OSC3
/ 16
AH
f
OSC3
/ 32
9H
f
OSC3
/ 64
8H
f
OSC3
/ 256
7H
f
OSC1
(32 kHz)
6H
f
OSC1
/ 2 (16 kHz)
5H
f
OSC1
/ 4 (8 kHz)
4H
f
OSC1
/ 16 (2 kHz)
3H
f
OSC1
/ 32 (1 kHz)
2H
f
OSC1
/ 64 (512 Hz)
1H
f
OSC1
/ 256 (128 Hz)
0H
Off
f
OSC1
: OSC1 oscillation frequency. ( ) indicates the clock frequency when f
OSC1
= 32 kHz.
f
OSC3
: OSC3 oscillation frequency
When the FOUT frequency is set to "f
OSC3
/n," the OSC3 oscillation circuit must be turned on before outputting the
FOUT signal. A time interval of several tens of µsec to several tens of msec, from turning the OSC3 oscillation circuit
on until the oscillation stabilizes, is necessary. Consequently, if an abnormality occurs as the result of an unstable
FOUT signal being output externally, you should allow an adequate waiting time after turning the OSC3 oscillation
on, before starting FOUT output. Since the FOUT signal is generated asynchronously from the FOUT[3:0] register,
a hazard of a 1/2 cycle or less is generated when the signal is turned on or off by setting the registers. Figure 7.5.1
shows the output waveform of the FOUT signal.
FOUT[3:0]
FOUT output (P13)
0H
0H
Other than 0H
5.1 Output waveform of FOUT signal
Figure 7.
