3 CPu anD MeMORY
S1C63003/004/008/016 TeChniCal Manual
Seiko epson Corporation
3-1
(Rev. 1.1)
CPU and Memory
3
CPu
3.1
The S1C63003/004/008/016 has a 4-bit core CPU S1C63000 built-in as its CPU part.
Refer to the "S1C63000 Core CPU Manual" for the S1C63000.
Code Memory area
3.2
Code ROM
3.2.1
The built-in code ROM is a mask ROM for loading programs.
2.1.1 Code ROM capacity
Table 3.
Model
Capacity
Address
S1C63016
16,384 words
×
13 bits
0000H to 3FFFH
S1C63008
8,192 words
×
13 bits
0000H to 1FFFH
S1C63004
4,096 words
×
13 bits
0000H to 0FFFH
S1C63003
4,096 words
×
13 bits
0000H to 0FFFH
The program start address after initial reset is assigned to step 0110H. The non-maskable interrupt (NMI) vector and
hardware interrupt vectors are allocated to step 0100H and steps 0101H–010FH, respectively.
0000H
0FFFH
1000H
FFFFH
0000H
0100H
0101H
0110H
0100H
0101H
0102H
0103H
0104H
0105H
0106H
0107H
0108H
0109H
010AH
010BH
010CH
010DH
010EH
010FH
Program area
NMI vector
Hardware
interrupt vectors
Program start address
Program area
Code ROM
S1C63003
Unused area
13 bits
S1C63000 core CPU
program space
Code ROM
S1C63004
Unused area
13 bits
Code ROM
S1C63008
Unused area
13 bits
0000H
3FFFH
4000H
FFFFH
Code ROM
S1C63016
Unused area
13 bits
Watchdog timer (NMI)
R/F converter
Programmable timer 0
Programmable timer 1
Programmable timer 2
Programmable timer 3
–
–
–
–
Serial interface
Key input interrupt (P0)
Key input interrupt (P1)
Stopwatch timer
Clock timer (1)
Clock timer (2)
S1C63016
–
–
–
–
S1C63008
–
–
–
–
–
S1C63004
–
–
–
–
–
S1C63003
–
–
–
–
–
–
–
–
–
Program area
0000H
0FFFH
1000H
FFFFH
0000H
1FFFH
2000H
FFFFH
2.1.1 Configuration of code ROM
Figure 3.