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Page-3

D

0

-D

3

11-14

14,15,16,19

Bi-

(Data bus)

direction

A

0

-A

3

4-7

5,7,9,10

Input

(Address bus)

ALE

3

4

Input

(Address Latch Enable)

WR

10

13

Input

(WRite)

RD

8

11

Input

(ReaD)

CS

1

, CS

0

15,2

20,2

Input

(Chip Select)

STD.P

1

1

Output

(STanDard Pulse)

V

DD

18

24

GND

9

12

(V

DD

)

16,17

22,23

N.C.

-

3,6,8,17,18,21

Connect these pins to a bidirectional data bus or CPU data bus. Use
this bus to read to and write from the internal counter and registers.

Address input pins used for connection to CPU addresses, etc. Used
to select the RTC's internal counter and registers (address selection).
When the RTC is connected to a multiplexed-bus type of CPU, these
pins can also be used in combination with the ALE described below.
Reads in address data and 

CS

0

state for internal latching.

When the ALE is high, the address data and 

CS

0

state is read into

the RTC. When the (through-mode) ALE falls, the address data and

CS

0

state at that point are held. The held address data and 

CS

0

status

are maintained while the ALE is low.

If the RTC is connected to a CPU that does not have an ALE pin and
thus there is no need to use this ALE pin, fix it to V

DD

.

Writes the data on D

0

to D

3

into the register of the address specified

by A

0

to A

3

, at the leading edge of 

WR

.

Make sure that 

RD

and 

WR

are never low at the same time.

Outputs data to D

0

to D

3

from the register at the address specified by

A

0

to A

3

, while 

RD

is low.

Make sure that 

RD

and 

WR

are never low at the same time.

When CS

1

is high and 

CS

0

is low, the RTC's chip-select function is

valid and read and write are enabled.
When the RTC is connected to a multiplexed-bus type of CPU, 

CS

0

requires the operation of the ALE (see the description of the ALE).
Use CS

1

connected to a power voltage detection circuit. When CS

1

is

high, the RTC is enabled; when it is low, the RTC is on standby.
When CS

1

goes low, the HOLD and RESET bits in the RTC registers

are cleared to 0.
This is an N-channel open drain output pin.
Depending on the setting of the C

E

register, a fixed-period interrupt

signal and a pulse signal are output.
The output from this pin cannot be inhibited by the CS

1

and 

CS

0

signals.

Use a load voltage that is less than or equal to V

DD

. If not using this

pin, keep it open-circuit.
An example of STD.P connection is shown below.

If the STD.P output is not be used during standby operation,
connecting the pull-up resistor to +5 V provides a reduction in current
consumption. If the STD.P output is to be used even during standby,
connect the pull-up resistor to the RTC's V

DD

. In this case, the current

consumption will be increased by the amount of current flowing
through the pull-up resistor.
Connect this pin to power source. Supply to 5 V ±10% to this pin
during normal operation; at least 2 V during battery back-up
operation.
Connect this pin to ground.
These pins are connected internally to V

DD

. Leave them open circuit.

These pins are not connected internally. Ground them.

Pin functions

Signal

Pin No.

Input/

Function

RTC-72421 RTC-72423 Output

CS-1

CS

0

RD

WR

Mode of D

0

to D

3

H

L

L

H

Output mode (read mode)

H

L

H

L

Input mode (write mode)

H

L

L

L

Do not use

L

H or L

High impedance (back-up mode)

H

H

H or L

High impedance (RTC not selected)

ALE

Address data and CS

0

status

H

Read into the RTC to set address data

L

Held in the RTC (latched at the trailing edge of the ALE)

Summary of Contents for RTC-72421 A

Page 1: ...Real Time Clock Module Application Manual MQ162 01 RTC 72421 72423 ...

Page 2: ...llectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party This material of portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Contro...

Page 3: ...tting the fixed period pulse output mode and fixed period interrupt mode 10 5 Resetting the fixed period pulse output mode and fixed period interrupt mode 10 Register description 11 1 Timing registers 11 1 S1 to Y10 registers 11 2 W register 11 3 H10 register PM AM h20 h10 11 4 Y1 and Y10 registers 11 5 Out of range data 11 2 CD register control register D 12 1 HOLD bit D0 12 2 BUSY bit D1 12 3 IR...

Page 4: ... Connection to 68 series MPU 20 Reference data 21 1 Frequency temperature characteristics typical 21 2 Frequency voltage characteristics typical 21 3 Current consumption voltage characteristics typical 21 External dimensions 22 1 RTC 72421 22 2 RTC 72423 22 Marking layout 22 Application notes 23 1 Notes on handling 23 1 Static electricity 22 2 Noise 22 3 Voltage levels of input pins 22 4 Treatment...

Page 5: ...ited for applications requiring timing management such as personal computers dedicated wordprocessors fax machines multi function telephones and sequencers Built in crystal unit removes need for adjustment and reduces installation costs Use of C MOS IC enables low current consumption 5µA max at VDD 2 0V Compatibility with Intel CPU bus Address latch enable ALE pin compatible with multiplex bus CPU...

Page 6: ...23 Block diagram Pin connections RTC 72421 RTC 72423 The VDD pins are at the same electrical level as VDD Do not connect these pins externally The N C pins are not connected internally Ground them in order to prevent noise ...

Page 7: ...en the RTC is connected to a multiplexed bus type of CPU CS0 requires the operation of the ALE see the description of the ALE Use CS1 connected to a power voltage detection circuit When CS1 is high the RTC is enabled when it is low the RTC is on standby When CS1 goes low the HOLD and RESET bits in the RTC registers are cleared to 0 This is an N channel open drain output pin Depending on the settin...

Page 8: ... 5 p y t 0 1 x a m 0 1 µA I D D 2 V D D V 0 2 p y t 9 0 x a m 5 m e t I l o b m y S n o i t i d n o C s n o i t a c i f i c e p S t i n U e g a t l o v y l p p u S V D D 5 5 o t 5 4 V e r u t a r e p m e t g n i t a r e p O T R P O 1 2 4 2 7 C T R 0 7 o t 0 1 C 3 2 4 2 7 C T R 5 8 o t 0 4 e g a t l o v d l o h a t a D V H D 5 5 o t 0 2 V S C 1 e m i t d l o h a t a d t R D C a t a d n o n o i t c ...

Page 9: ...a k a e l t u p n I I 1 K L VI V D D 0 V D r o f t p e c x e s n i p t u p n I 0 D o t 3 1 1 µA 2 t n e r r u c e g a k a e l t u p n I I 2 K L D0 D o t 3 0 1 0 1 1 e g a t l o v t u p t u o w o L V 1 L O I L O A m 5 2 4 0 V e g a t l o v t u p t u o h g i H V H O I H O 0 0 4 µA 4 2 2 e g a t l o v t u p t u o w o L V 2 L O I L O A m 5 2 P D T S 4 0 t n e r r u c e g a k a e l e t a t s f f O I K ...

Page 10: ... t a D t V Z P Q R F p 0 5 1 L C 0 2 1 d a e r r e t f a e m i t r e f s n a r t g n i t a o l f t u p t u o a t a D t Z V P Q R 0 0 7 S C 1 e m i t d l o h tH S C 1 0 0 2 e m i t y r e v o c e r d a e R t C E R W 0 0 0 1 m e t I l o b m y S n o i t i d n o C N I M X A M t i n U S C 1 e m i t p u t e s t U S S C 1 0 0 0 1 s n E L A e r o f e b e m i t p u t e s s s e r d d A t U S E L A A 0 5 E L ...

Page 11: ...Page 7 1 Write mode 2 Read mode ...

Page 12: ...t i r w e r o f e b e m i t p u t e s t u p n i a t a D t U S W D 0 8 e t i r w r e t f a e m i t d l o h a t a D tH D W 0 1 e m i t y r e v o c e r e t i r W t C E R W 0 0 2 m e t I l o b m y S n o i t i d n o C N I M X A M t i n U S C 1 e m i t p u t e s t U S S C 1 0 0 0 1 s n S C 1 e m i t d l o h tH S C 1 0 0 0 1 e t i r w e r o f e b e m i t p u t e s s s e r d d A t U S W A 0 5 e t i r w r ...

Page 13: ...0 4 s 0 2 s 0 1 s 5 0 r e t s i g e r t i g i d s d n o c e s 0 1 2 0 0 1 0 1 I M 8 i m 4 i m 2 i m 1 i m 9 0 r e t s i g e r t i g i d e t u n i m 1 3 0 0 1 1 0 1 I M 0 4 i m 0 2 i m 0 1 i m 5 0 r e t s i g e r t i g i d s e t u n i m 0 1 4 0 1 0 0 1 H 8 h 4 h 2 h 1 h 9 0 r e t s i g e r t i g i d r u o h 1 5 0 1 0 1 0 1 H M A M P 0 2 h 0 1 h 2 r o 1 0 r e t s i g e r t i g i d s r u o h 0 1 6 0 ...

Page 14: ...l b i c r o f Y S U B S e h t n i a t a d g n i s s e c c a n e h w t i b Y S U B e h t e s U 1 n o i t a t n e m e r c n i e h t g n i r u d 1 o t t e s s i t i b s i h T s r e t s i g e r W o t S e h t f o e l c y c 1 S e h t o t s s e c c a 1 s i t i b Y S U B e h t n e h W e s i w r e h t o 0 o t t e s s i d n a s r e t s i g e r W o t 1 W o t d e t i b i h n i s i s r e t s i g e r S e h t g ...

Page 15: ...tting is needed If the 24 hour clock is selected the PM AM bit will always be 0 For details of how to set 12 hour or 24 hour clock see the section on the 24 12 bit on page 15 4 Y1 and Y10 registers The Y1 and Y10 registers can handle the last two digits of the year in the Gregorian calendar Leap years are automatically identified and this affects the handling of the month and day digits for Februa...

Page 16: ...is an internal status bit that corresponds to the status of the STD P pin output to indicate whether or not an interrupt request has been issued to the CPU When the STD P pin output is low the IRQ FLAG bit is 1 when the STD P pin output is open circuit the IRQ FLAG bit is 0 When writing data to the CD register keep the IRQ FLAG bit at 1 except when deliberately writing 0 to it Writing 0 to the IRQ...

Page 17: ...and minutes digits as shown below If the minutes digits have been incremented an upward carry is propagated Example The correction caused by the 30 seconds ADJ bit sets the time within the RTC to 00 00 00 if it was within the range of 00 00 00 to 00 00 29 or to 00 01 00 if it was within the range of 00 00 30 to 00 00 59 ii Access inhibited after 30 seconds correction For 76 3 mseconds after 1 is w...

Page 18: ...ng for fixed period pulse output or fixed period interrupts ii STD P pin output control The timing of STD P pin output is at the incrementation of the period specified by the t0 and t1 bits t1 t0 y c n e u q e r f d o i r e P s k r a m e R 0 0 z H 4 6 d n o c e s 4 6 1 t u p t u o n i p P D T S e h t e d o m t u p t u o e s l u p d o i r e p d e x i f n I s m 5 2 1 8 7 r o f w o l s i s m 5 2 1 8 ...

Page 19: ...256 seconds counter The reset continues for as long as the RESET bit is 1 End the reset by writing 0 to the RESET bit If the level of the CS1 pin goes low the RESET bit is automatically cleared to 0 2 STOP bit D1 Writing 1 to the STOP bit stops the clock of the internal counter from the 1 8192 second bit onward Writing 0 to the STOP bit restarts the clock This function can be used to create a cumu...

Page 20: ...3 1 Power on procedure initialization When power is turned on the contents of all registers and the output from the STD P pin are undefined Therefore all the registers must be initialized after power on Follow the procedure given below for initialization ...

Page 21: ...Page 17 A Starting the count B Checking the status of the BUSY bit C Stopping and resetting the counter Wait 250 µs C Stopping and resetting the counter ...

Page 22: ...r registers S1 to W cannot be accessed for 76 3 mseconds after this write Therefore follow one of the procedures shown below to use this function or Note The crystal unit could be damaged if subjected to excessive shock If the crystal unit should stop operating for such a reason the timer within the RTC will stop While the crystal unit is operating the BUSY bit is automatically reset every 190 mse...

Page 23: ...te in which a voltage lower than the RTC s rated range of operating supply voltage is applied 4 5 V to 2 0 V Under this condition the timer continues to operate under battery back up power but the interface between the interior and exterior of the RTC cannot be guaranteed 2 Timing 3 Note If the RTC is operated with timing conditions different from those shown above data within the RTC could be ove...

Page 24: ...lly check the AC timings of both the RTC and the microprocessor 1 Connection to multiplexed bus type The resistors on the RD and WR lines are not necessary if the CPU does not have a HALT or HOLD state 2 Connection to Z80 or compatible CPU 3 Connection to 68 series MPU Select IORQ or MEMRQ depending on whether the RTC maps I O or memory of the CPU ...

Page 25: ...e characteristics can be approximated by the following equation fT ppm α θT θX 2 2 To determine the overall clock accuracy add the frequency tolerance and the voltage characteristics f f ppm f f0 fT fV 3 Finding the daily deviation Daily error f f x 10 6 x 86400 The clock error is one second per day at 11 574 ppm θT 25 C Typ α 0 035ppm C2 Typ 2 Frequency voltage characteristics typical 3 Current c...

Page 26: ...72421 2 RTC 72423 Unless otherwise stated all units are mm Note The illustration is a general representation of the content and location of information on the label and is not a detailed specification of the typeface size or positioning of printing used on the label ...

Page 27: ... placing any device that generates high levels of electronic noise near the RTC 72421 RTC 72423 module Do not connect signal lines to the RTC 72421 RTC 72423 module within the area shown hatched in the figure on the right and if possible embed this area in a GND land 3 Voltage levels of input pins Apply signal levels that are as close as possible to VDD and ground to all pins except the CS1 pin Mi...

Page 28: ...at these curves are as gentle as possible 2 Mounting equipment While this module can be used with general purpose mounting equipment the internal crystal unit may be damaged in some circumstances depending on the equipment and conditions Therefore you should confirm that the module will survive the mounting process that will be used before actually using this module in full scale production In add...

Page 29: ...l Berkshire RG12 8PE England Phone 41 0 1 344 381700 Fax 41 0 1 344 381701 Les Conquerants Immeuble Fujiyama L P 915 1 Avenue de l Atlantique Z A de Courtaboeuf 2 91976 Les Ulis Cedex Phone 33 0 1 64 86 23 50 Fax 33 0 1 64 86 23 55 V le F lli Casiraghi 427 20099 Sesto San Giovanni Milan ITALY Phone 39 2 262331 Fax 39 2 2440750 20 F Harbour Centre 25 Harbour Road Wanchai HONG KONG Phone 852 2585 46...

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