RA4803SA
Page - 15
ETM38E-03
8.2.9. Capture
Buffer / Event control
(
Bank
3
)
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
1/100 S CP
80
40
20
10
8
4
2
1
1
SEC CP
40
20
10
8
4
2
1
F
Event Control
ECP
EHL
ET1
ET0
ERST
It is a register that sets it concerning the event detection.
1) ECP bit ( Event Capture enable )
It is specified whether to do the second and 1/100S data to the capture buffer in capture
when the event is detected.
ECP
Operation
0
Capture doesn't operate
1
Capture operation
2) EHL bit ( High/Low detection select )
The disregard level of the event input is specified.
The event is detected by maintaining the level specified by the EHL bit longer than the chattering removal
cycle.
EHL
Operation
0
"L" level detect
1
"H" level detect
3) ET1,ET0 bits ( Event chattering Time Set )
The removal cycle of the chattering removal function is set.
･
Chattering removal cycle
ET1
ET0
Cycle
0
0
not provided
0
1
3.9 ms
1
0
15.6 ms
1
1
125 ms
4) ERST bit
When this bit is made "1", the counter of the Clock&Calendar circuit (counter for 16KHz to 2Hz
and 1/100 seconds) at less than second is reset synchronizing with the external event detection.
ALL "0" is cleared to CP and the CP register of the second at the same time for 1/100 seconds.
Timing continues until the event is generated after "1" is written in the ERST bit.
The counter at less than second when an external event is detected is reset, and the ERST bit is
cleared.
Moreover, it is also possible to assume this reset action to be invalid by doing "0" writing
directly to the ERST bit before the event is generated.
When the highly accurate time suiting is done, this bit is used.
The time for the counter at less than second to be reset influences the operation of the alarm, the
fixed cycle timer, and the update interrupt of time, etc.
