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RA4803SA

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ETM38E-03

VLF

Data

Description

Write

0

The VLF bit is cleared to zero to prepare for the next status detection.

1

This bit is invalid after a "1" has been written to it.

Read

0

Data loss is not detected.

1

Data loss is detected. All registers must be initialized.
( This setting is retained until a "zero" is written to this bit. )

5) VDET ( Voltage Detection Flag ) bit

This flag bit indicates the status of temperature compensation. Its value changes from "0" to "1" when stop the
temperature compensation, such as due to a supply voltage drop. Once this flag bit's value is "1", its value is
retained until a "0" is written to it.
When after powering up from 0 V this bit's value is "1".

VDET

Data

Description

Write

0

The VDET bit is cleared to zero to prepare for the next low voltage detection.

1

The write access of "1" to this bit is invalid.

Read

0

Temperature compensation is normal.

1

Temperature compensation is stop detected.

8.2.7. Control register

Address

Function

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

F

Control Register

CSEL1

CSEL0

UIE

TIE

AIE

EIE



RESET

(Default)

(0)

(1)

(

−

)

(

−

)

(

−

)

(0)

(0)

(

−

)

∗

1)

The default value is the value that is read (or is set internally) after powering up from 0 V.

∗

2)

"o" indicates write-protected bits. A zero is always read from these bits.

∗

3)

"

−

" indicates no default value has been defined.

•

This register is used to control interrupt event output from the /INT pin and the stop/start status of clock and

calendar operations.

1) CSEL0,1 ( Compensation interval Select 0, 1 ) bits

The combination of these two bits is used to set the temperature compensation interval.

CSEL0,1

CSEL1

(bit 7)

CSEL0

(bit 6)

Compensation interval

Write/Read

0

0

0.5 s

0

1

2.0 s

∗

Default

1

0

10 s

1

1

30 s

2) UIE ( Update Interrupt Enable ) bit

When a time update interrupt event is generated (when the UF bit value changes from "0" to "1"), this bit's value
specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT
status remains Hi-Z).
When a "1"

is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an

interrupt event is generated.
When a "0"

is written to this bit, no interrupt signal is generated when an interrupt event occurs.

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Summary of Contents for RA4803SA

Page 1: ...ETM38E 03 Preliminary Application Manual Real Time Clock Module RA4803SA ...

Page 2: ...nd any technical information furnished if any for the development and or manufacture of weapon of mass destruction or for other military purposes You are also requested that you would not make the products available to any third party who may use the products for such prohibited purposes These products are intended for general use in electronic equipment When using them in specific applications th...

Page 3: ... C Bank 3 14 8 2 9 Capture Buffer Event control Bank 3 15 8 3 Fixed cycle Timer Interrupt Function 16 8 3 1 Diagram of fixed cycle timer interrupt function 16 8 3 2 Related registers for function of time update interrupts 17 8 3 3 Fixed cycle timer interrupt interval example 18 8 3 4 Fixed cycle timer start timing 18 8 4 Time Update Interrupt Function 19 8 4 1 Time update interrupt function diagra...

Page 4: ... is an serial interface real time clock which includes a 32 768 kHz DTCXO In addition to providing a calendar year month date day hour minute second function and a clock counter function this module provides an abundance of other functions including an alarm function fixed cycle timer function time update interrupt function and 32 768 kHz output function The devices in this module are fabricated v...

Page 5: ...ta output pin for serial data transfer FOUT Output This is the C MOS output pin with output control provided via the FOE pin When FOE H high level this pin outputs a 32 768 kHz signal When output is stopped the FOUT pin Hi Z high impedance FOE Input This is an input pin used to control the output mode of the FOUT pin When this pin s level is high the FOUT pin is in output mode When it is low outpu...

Page 6: ...ge VCLK 1 6 3 0 5 5 V Operating temperature TOPR No condensation 40 25 85 C 6 Frequency Characteristics GND 0 V Item Symbol Condition Rating Unit Frequency stability f f U A Ta 0 to 50 C VDD 3 0 V Ta 40 to 85 C VDD 3 0 V 1 9 1 3 4 2 10 ６ U B Ta 0 to 50 C VDD 3 0 V Ta 40 to 85 C VDD 3 0 V 3 8 3 5 0 4 U C Ta 0 to 50 C VDD 3 0 V Ta 30 to 70 C VDD 3 0 V 3 8 3 5 0 4 A A Ta 25 C VDD 3 0 V 5 5 0 5 Freque...

Page 7: ...7 1 85 Current consumption 9 IDD9 CE GND INT FOE GND FOUT output OFF High Z Compensation ON peak VDD 5 V 120 900 µA Current consumption 10 IDD10 VDD 3 V 115 350 High level input voltage VIH CE DI CLK FOE EVIN pins 0 8 VDD 5 5 V Low level input voltage VIL CE DI CLK FOE EVIN pins GND 0 3 0 2 VDD V High level output voltage VOH1 FOUT DO pins VDD 5 V IOH 1 mA 4 5 5 0 V VOH2 VDD 3 V IOH 1 mA 2 2 3 0 V...

Page 8: ... 300 200 ns CE enable time tWCE 0 95 0 95 s Write data setup time tDS 100 50 ns Write data hold time tDH 100 50 ns Read data delay time tRD CL 50 pF 200 150 ns DO output switching time tZR 50 20 ns DO output disable time tRZ CL 50 pF RL 10 kΩ 200 150 ns DI DO conflict avoiding time tZZ 0 0 ns FOUT duty tW t 50 VDD level 40 60 40 60 Timing chart CLK C E tCLKS tWH tWL tCH tCR Read D I tDS Write tDH ...

Page 9: ...larm 20 10 8 4 2 1 B Timer Counter 0 128 64 32 16 8 4 2 1 P P C Timer Counter 1 2048 1024 512 256 P P D Extension Register TEST WADA USEL TE FSEL1 FSEL0 TSEL1 TSEL0 P P E Flag Register UF TF AF EVF VLF VDET P P F Control Register CSEL1 CSEL0 UIE TIE AIE EIE RESET P P P Possible I Impossible Note When after the initial power up or when the result of read out the VLF bit is 1 initialize all register...

Page 10: ...Timer Counter 0 128 64 32 16 8 4 2 1 P P C Timer Counter 1 2048 1024 512 256 P P D Extension Register TEST WADA USEL TE FSEL1 FSEL0 TSEL1 TSEL0 P P E Flag Register UF TF AF EVF VLF VDET P P F Control Register CSEL1 CSEL0 UIE TIE AIE EIE RESET P P 1 100S Reg is cleared to 00 by writing in the SEC Reg or RESET bit and the ERST bit operation 8 1 4 Register table Bank3 Address Function bit 7 bit 6 bit...

Page 11: ...d counter Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 1 100 S 80 40 20 10 8 4 2 1 This second counter counts from 00 to 01 02 and up to 99 100 seconds after which it starts again from 00 seconds 2 Second counter Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 SEC 40 20 10 8 4 2 1 This second counter counts from 00 to 01 02 and up to 59 seconds after which ...

Page 12: ...hese bits The auto calendar function updates all dates months and years from January 1 2001 to December 31 2099 The data format is BCD format For example a date register value of 0011 0001 indicates the 31st Note with caution that writing non existent date data may interfere with normal operation of the calendar counter 2 Date counter Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit ...

Page 13: ...s the value that is read or is set internally after powering up from 0 V 2 o indicates write protected bits A zero is always read from these bits 3 indicates a default value is undefined This register is used to specify the target for the alarm function or time update interrupt function and to select or set operations such as fixed cycle timer operations 1 TEST bit This is the manufacturer s test ...

Page 14: ... Flag bit If set to 0 beforehand this flag bit s value changes from 0 to 1 when a time update interrupt event has occurred Once this flag bit s value is 1 its value is retained until a 0 is written to it For details see 8 4 Time Update Interrupt Function 2 TF Timer Flag bit If set to 0 beforehand this flag bit s value changes from 0 to 1 when a fixed cycle timer interrupt event has occurred Once t...

Page 15: ...t 3 bit 2 bit 1 bit 0 F Control Register CSEL1 CSEL0 UIE TIE AIE EIE RESET Default 0 1 0 0 1 The default value is the value that is read or is set internally after powering up from 0 V 2 o indicates write protected bits A zero is always read from these bits 3 indicates no default value has been defined This register is used to control interrupt event output from the INT pin and the stop start stat...

Page 16: ...emains Hi Z When a 1 is written to this bit an interrupt signal is generated INT status changes from Hi Z to low when an interrupt event is generated When a 0 is written to this bit no interrupt signal is generated when an interrupt event occurs AIE Data Function Write Read 0 When an alarm interrupt event occurs an interrupt signal is not generated or is canceled INT status changes from low to Hi ...

Page 17: ... 0 1 0 0 2 4 0 1 0 1 3 0 0 1 1 0 3 6 0 1 1 1 4 2 1 0 0 0 4 8 1 0 0 1 4 2 1 0 1 0 3 6 1 0 1 1 3 0 1 1 0 0 2 4 1 1 0 1 1 8 1 1 1 0 1 2 1 1 1 1 0 6 The OFS register affects the frequency stability Please refer to a lower graph Please be careful if you offset and adjust it The offset function is effective for frequency adjustment at the normal temperature Frequency Stability vs Temperature vs OSC Offs...

Page 18: ...et The removal cycle of the chattering removal function is set Chattering removal cycle ET1 ET0 Cycle 0 0 not provided 0 1 3 9 ms 1 0 15 6 ms 1 1 125 ms 4 ERST bit When this bit is made 1 the counter of the Clock Calendar circuit counter for 16KHz to 2Hz and 1 100 seconds at less than second is reset synchronizing with the external event detection ALL 0 is cleared to CP and the CP register of the ...

Page 19: ...is cleared to zero INT remains low during the tRTN time 1 When a 1 is written to the TE bit the fixed cycle timer countdown starts from the preset value 2 A fixed cycle timer interrupt event starts a countdown based on the countdown period source clock When the count value changes from 001h to 000h an interrupt event occurs After the interrupt event that occurs when the count value changes from 00...

Page 20: ... setting 2 When the source clock has been set to second update or minute update the timing of both countdown and interrupts is coordinated with the clock update timing 2 Fixed cycle Timer Control register Reg B to C This register is used to set the default preset value for the counter Any count value from 1 001 h to 4095 FFFh can be set The counter counts down based on the source clock s period an...

Page 21: ...3 3 Fixed cycle timer interrupt interval example Timer Counter setting Source clock 4096 Hz TSEL1 0 0 0 64 Hz TSEL1 0 0 1 Second update TSEL1 0 1 0 Minute update TSEL1 0 1 1 0 1 244 14 µs 15 625 ms 1 s 1 min 2 488 28 µs 31 25 ms 2 s 2 min 41 10 010 ms 640 63 ms 41 s 41 min 205 50 049 ms 3 203 s 205 s 205 min 410 100 10 ms 6 406 s 410 s 410 min 2048 500 00 ms 32 000 s 2048 s 2048 min 4095 0 9998 s ...

Page 22: ...ero Operation in RTC i i Write operation 1 2 3 4 1 5 6 7 1 A time update interrupt event occurs when the internal clock s value matches either the second update time or the minute update time The USEL bit s specification determines whether it is the second update time or the minute update time that must be matched 2 When a time update interrupt event occurs the UF bit value becomes 1 3 When the UF...

Page 23: ...m 0 to 1 when a time update interrupt event occurs When this flag bit 1 its value is retained until a 0 is written to it UF Data Description Write 0 The UF bit is cleared to zero to prepare for the next status detection Clearing this bit to zero does not enable the INT low output status to be cleared to Hi Z 1 This bit is invalid after a 1 has been written to it Read 0 Time update interrupt events...

Page 24: ...e is used as the setting the alarm will not occur until the counter counts up to the current date time i e an alarm will occur next time not immediately 2 When a time update interrupt event occurs the AF bit values becomes 1 3 When the AF bit 1 its value is retained until it is cleared to zero 4 If AIE 1 when an alarm interrupt occurs the INT pin output goes low When an alarm interrupt event occur...

Page 25: ... used to specify either WEEK or DAY as the target for alarm interrupt events WADA Data Description Write Read 0 Sets WEEK as target of alarm function DAY setting is ignored 1 Sets DAY as target of alarm function WEEK setting is ignored 2 Alarm registers Reg 8 to A Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 8 MIN Alarm AE 40 20 10 8 4 2 1 9 HOUR Alarm AE 20 10 8 4 2 1 A WEEK A...

Page 26: ... the AIE bit value is 0 another interrupt event may change the INT status to low or may hold INT L 1 When an alarm interrupt event occurs an interrupt signal is generated INT status changes from Hi Z to low When an alarm interrupt event occurs low level output from the INT pin occurs only when the AIE bit value is 1 This value is retained not automatically cleared until the AF bit is cleared to ze...

Page 27: ...de Address N Data N 2 Continuous writing CLK C E D I D O Hi Z 0 0 x A3 A2 A1 A0 D7 D6 D5 D1 D0 D7 D6 1 2 3 4 5 6 7 8 9 10 11 D1 D0 D7 D6 D1 D0 0 Mode Address N Data N Data N 1 Data N m When writing data the data needs to be entered in 8 bits units If the input of data in 8 bits unit is not completed before CE input falls the 8 bits data will not be written properly at the time CE input falls 8 6 2...

Page 28: ... Backup and Recovery VDD t F t R2 Back up t R1 VCLK 0 V VDET Item Symbol Condition Min Typ Max Unit Power supply detection voltage 1 VDET 2 2 V Power supply detection voltage 2 VLOW 1 6 V Power supply drop time t F 2 µs V Initial power up time t R1 10 ms V Clock maintenance power up time t R2 1 6V VDD 3 6V 5 µs V 1 6V VDD 3 6V 15 µs V Please control a power supply in the above agreement so that no...

Page 29: ... D I CLK INT FOUT FOE DO CE Note When using the seconding battery the diode is not required When using the primary battery the diode is required For detailed value on the resistance please consult a battery maker 8 10 When used as a clock source 32 kHz TCXO RA4803 VDD CE GND 0 1 µF FOUT INT D I DO CLK FOE VDD 32 768kHz O E TEST T2 EVIN ...

Page 30: ...ag of a readout result is 1 second at the maximum Read out method of 1 100 second digits to prevent mismatching of the time Method 1 Method to read two times of 1 100 second digits Step1 please read 1 100 second digits and time data and stored those Step2 Please read only 1 100 second digits again Please complete Step2 within 10ms from Step1 Step3 If two 1 100 second digits are same values please ...

Page 31: ... 1 0 2 5 0 7 4 0 2 14 8 7 1 1 27 1 2 0 05 Min 3 2 0 1 0 35 The cylinder of the crystal oscillator can be seen in this area front but it has no affect on the performance of the device 9 1 2 Marking layout RA4803 SA SOP 14pin Logo Type Production lot A 4803 A E A123B Frequency Stability UA A UB Blank UC C AA W Contents displayed indicate the general markings and display but are not the standards for...

Page 32: ...If the temperature within the package exceeds 260 C the characteristics of the crystal oscillator will be degraded and it may be damaged The reflow conditions within our reflow profile is recommended Therefore always check the mounting temperature and time before mounting this device Also check again if the mounting conditions are later changed See Fig 2 profile for our evaluation of Soldering hea...

Page 33: ...nghai Branch High Tech Building 900 Yishan Road Shanghai 200233 China Phone 86 21 5423 5577 Fax 86 21 5423 4677 Shenzhen Branch 12 F Dawning Mansion 12 Keji South Road Hi Tech Park Shenzhen China Phone 86 755 2699 3828 Fax 86 755 2699 3838 EPSON HONG KONG LTD Unit 715 723 7 F Trade Square 681 Cheung Sha Wan Road Kowloon Hong Kong Phone 86 755 2699 3828 Shenzhen Branch Fax 86 755 2699 3838 Shenzhen...

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