5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
Low Frequency Clock
VDDU1
AVDDU1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VMCU
VMCU
LFXTAL_N
(p 4)
HFXTAL_N
(p 4)
LFXTAL_P
(p 4)
HFXTAL_P
(p 4)
MCUDBG_#RESET
(p 9)
Size
Designed:
Revision
Sheet
of
Approved:
Sheet Created Date
Sheet Modified Date
Document number
Schematic Title
Design Created Date:
BOM Doc No:
Page Title
A03
BRD2001A
Tuesday, June 29, 2010
5
10
A3
GB
<OrgAddr2>
EFM32 Starter Kit
<Cage Code>
Tuesday, January 12, 2010
Wednesday, December 03, 2008
TOP
<Schematic Path>
EFM32 Power
Size
Designed:
Revision
Sheet
of
Approved:
Sheet Created Date
Sheet Modified Date
Document number
Schematic Title
Design Created Date:
BOM Doc No:
Page Title
A03
BRD2001A
Tuesday, June 29, 2010
5
10
A3
GB
<OrgAddr2>
EFM32 Starter Kit
<Cage Code>
Tuesday, January 12, 2010
Wednesday, December 03, 2008
TOP
<Schematic Path>
EFM32 Power
Size
Designed:
Revision
Sheet
of
Approved:
Sheet Created Date
Sheet Modified Date
Document number
Schematic Title
Design Created Date:
BOM Doc No:
Page Title
A03
BRD2001A
Tuesday, June 29, 2010
5
10
A3
GB
<OrgAddr2>
EFM32 Starter Kit
<Cage Code>
Tuesday, January 12, 2010
Wednesday, December 03, 2008
TOP
<Schematic Path>
EFM32 Power
TP400
TP400
C405
100N
C405
100N
C411
10N
C411
10N
C412
12P
C412
12P
C415
22P
C415
22P
C402
100N
C402
100N
C413
12P
C413
12P
C404
100N
C404
100N
C409
10U
C409
10U
C414
22P
C414
22P
L400
BLM21B102S
L400
BLM21B102S
1
2
C407
10U
C407
10U
C401
100N
C401
100N
X400
32.0MHz
X400
32.0MHz
2
1
X401
32.768kHz
X401
32.768kHz
2
1
C410
10N
C410
10N
U300C
EFM32G890F128
U300C
EFM32G890F128
RESETn
K6
VDD_DREG
F8
AVSS
L7
AVDD
K9
VDD
G4
VDD
L4
VDD
H7
VDD
D7
VDD
G8
VSS
K4
VSS
H6
VSS
G9
VSS
D4
VSS
C7
AVDD
L10
AVSS
K7
AVDD
K8
AVSS
K10
VDD
D5
VSS
G3
VSS
F9
DECOUPLING
F11
TP401
TP401
C408
100N
C408
100N
R400
1R
R400
1R
SW400
SW400
1
2
3
4
R401
100R
R401
100R
C403
100N
C403
100N
C400
1U
C400
1U
C406
100N
C406
100N