EMC Symmetrix DMX-3, Product Manual

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94 EMC Symmetrix DMX-3 Product Guide
Symmetrix DMX-3 Hardware
Symmetrix FICON
configurations
In addition to the standard direct-connect configuration, Symmetrix
DMX-3 FICON models support the use of Cascading and Open
Systems Intermix configurations. Cascading can be used to reduce
the number of FICON adapters and the amount of intersite cabling
required by making use of switch-to-switch communication.
Intermix allows FICON zones to be added to existing Open Systems
switches within a site and between sites. These two features help
reduce the overall costs while providing greater FICON connectivity,
backup, and recovery.
Note: For specific Cascading and Open System Intermix configuration
requirements, contact your local EMC Sales Representative.
FICON cascading configurations
Cascading provides greatly enhanced FICON connectivity within
local and remote sites through the use of switch-to-switch extensions
of the CPU to the DMX FICON network. These cascaded switches
communicate over long distances using a small number of high speed
lines called ISLs (InterSwitch Links). Up to a maximum of two
switches may be connected together within a path between the CPU
and the DMX.
Same switch vendors are required for a Cascaded configuration. The
EMC and IBM branded McDATA and INRANGE switches are
supported in pairs. To support Cascading, each vendor requires
specific models, hardware and software features, configuration
settings, and restrictions. Specific IBM CPU models, MVS release
levels, channel hardware, and microcode levels are also required.
FICON open systems Intermix configurations
Open Systems Intermix allows separate FICON zones to be defined
within new or existing open systems switches. These switches can
also be Cascaded to further enhance connectivity and remote backup
and recovery. The EMC and IBM branded McDATA and INRANGE
switches are supported. To support Open Systems Intermix, each
vendor requires specific models, hardware and software features,
configuration settings, and restrictions. Specific IBM CPU models,
MVS release levels, channel hardware, and microcode levels are also
required.