EMC Symmetrix DMX-3, Product Manual, Page: 179 / 326

Maintaining data integrity 179
Data Integrity, Availability, and Protection
In the mainframe host environment, the Symmetrix system reports
uncorrectable bit errors as Equipment Checks to the CPU. These
errors appear in the IBM EREP file.
Global memory
chip-level
redundancy Traditional cache systems usually provide for eight bits of parity
information to support bit error correction and detection in a 64-bit
long word. The global memory directors incorporate single-nibble
correction double-nibble detection capabilities. (A nibble is four
consecutive bits of information.) Global memory chip-level
redundancy is achieved by internally generating 16 bits of ECC parity
information and replacing the incoming parity information. This
enables the system to correct up to four bit errors associated with a
64-bit-long word and can detect up to eight bit errors. It also
interleaves 64 bits of information plus 16 global memory director
parity information (total 80 bits) across 20 memory chips on the
global memory director. This results in each memory chip storing
only a nibble of information corresponding to a word. So, a chip-level
error will disable access only to the nibble stored on that faulty chip.
However, the global memory director enables regeneration of data
from the faulty chip. This leads to chip-level redundancy, making
every chip on the global memory director redundant.
Redundant global
memory Symmetrix DMX-3 global memory director operations are redundant
by way of a primary and secondary global memory director working
as a pair. If an error is detected in one of the memory directors, no
writes are allowed to the board containing the error. The writes will
be made to the nonfailing memory director until the failed global
memory director is replaced.
Longitude
redundancy code
(LRC) Symmetrix global memory directors also incorporate sector-level
Longitudinal Redundancy Checks (LRCs), which further assure data
integrity. The check bytes are the XOR (exclusive OR) value of the
accumulated bytes in a 4 KB sector. LRC checking can detect both
data errors and incorrect block access problems.
Byte-level parity
checking All data paths and control paths have parity generating and checking
circuitry that verify data integrity at the byte or word level. All data
and command I/Os passed through the direct matrix interconnect,
and within each channel/disk director and global memory director,
include parity bits used to check integrity at each stage of the data
transfer. This provides a system-wide error checking capability.