19
LPC, SMBus and Digital I/O pin header: CN5
This single pin header allows the connection of LPC, SMBus
devices and the Digital Input and Output.
Pin
Signal
Pin
Signal
1
GND
2
LAD3
3
SIOOSC
4
LAD2
5
LPCCLK
6
LAD1
7
-LDRQ1
8
-LFRAME
9
SERIRQ
10
LAD0
11
-SIOSMI/-PME
12
-PCIRST1
13
SMB_CLK
14
SMB_DAT
15
+5V
16
+3.3V
17
GPO5/CSTATE1
18
GPI8/-RING
19
GPO6/-C4PSTOP
20
GPI9/-THRM
21
GPIO0/SMBDT2
22
GPI5/-EXTSMI
23
GPIO1/SMBCK2
24
GPI4/-BATLOW
25
GND
26
GND
Summary of Contents for EPIA-P720
Page 1: ...user manual EPIA P720 Pico ITX Mainboard Revision 1 00 100 09162009 1423 ...
Page 10: ...1 1 Product Overview ...
Page 17: ...8 ...
Page 35: ...26 ...
Page 36: ...27 3 Onboard Jumpers ...
Page 39: ...30 ...
Page 40: ...31 4 P720 A I O Module Installation ...
Page 43: ...34 ...
Page 44: ...35 5 BIOS Setup This chapter gives a detailed explanation of the BIOS setup functions ...
Page 49: ...40 CPU CONFIGURATION CMPXCHG8B instruction support Settings Enabled Disabled ...
Page 56: ...47 CHIPSET ACPI CONFIGURATION USB Device Wakeup Function Settings Disabled Enabled ...
Page 66: ...57 Interrupt 19 Capture Settings Disabled Enabled ...
Page 72: ...63 Rank Interleave Settings Disabled Enabled Bank Address Scramble Settings Disabled Enabled ...
Page 73: ...64 AGP P2P BRIDGE CONFIGURATION Primary Graphics Adapter Settings PCI AGP ...
Page 77: ...68 PCI Delay Transaction Settings Disabled Enabled WATCH DOG Settings Disabled Enabled ...
Page 79: ...70 ...