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LPC3131/41 Developer’s Kit - User’s Guide

Page 38

5.3.7

Booting via NAND Flash

NXP has written detailed instructions of how to use the u-boot or Apex bootloaders to program the

NAND flash on the LPC31xx OEM Boards with a bootable image. Please follow the links below for

more information.

Program NAND flash using u-boot

http://www.lpclinux.com/LPC313x/LPC313xUbootNand#Programming_NAND_flash_using_Uboot

Program NAND flash using Apex

http://www.lpclinux.com/LPC313x/LPC313xApexNand#Programming_NAND_flash_using_Apex

Summary of Contents for LPC3131

Page 1: ...3131 41 Developer s Kit User s Guide Copyright 2012 Embedded Artists AB EA2 USG 0901 Rev K LPC3131 41 Developer s Kit User s Guide Get Up and Running Quickly and Start Developing Your Applications On Day 1 ...

Page 2: ... written permission of Embedded Artists AB Disclaimer Embedded Artists AB makes no representation or warranties with respect to the contents hereof and specifically disclaim any implied warranties or merchantability or fitness for any particular purpose Information in this publication is subject to change without notice and does not represent a commitment on the part of Embedded Artists AB Feedbac...

Page 3: ... Mechanical Dimensions and Connector 15 3 4 Things to note about the LPC3131 41 OEM Board 15 3 4 1 NAND FLASH Bad Block 15 3 4 2 Brand of Memory Chips 15 4 LPC31xx Base Board Design 16 4 1 Usage of CPU Pins 16 4 2 Known Limitation Things to note about the LPC31xx Base Board 18 4 2 1 Codec Usage and Boot Mode 18 4 2 2 NAND Booting 18 4 2 3 SD MMC card detect 19 4 2 4 USB Host applications power sup...

Page 4: ...User s Guide Page 4 Copyright 2012 Embedded Artists AB 5 3 3 Booting via UART 35 5 3 4 Booting via SPI NOR flash 35 5 3 5 Booting via USB DFU class 36 5 3 6 LED on GPIO2 37 5 3 7 Booting via NAND Flash 38 6 Further Information 39 ...

Page 5: ...LCD Ethernet problem section 5 3 6 F 2009 11 27 Changed title of manual to Developer s Kit manual Updated OEM Board schematic to v1 2 Replaced earlier section 5 3 6 with new section about NAND boot and LCD Ethernet problem section 4 6 G 2010 07 05 Added information in section 4 2 about things to note about the LPC31xx Base Board UDA1380 I2C address SD card detect logic USB Host powering H 2010 11 ...

Page 6: ...ternal data memory 64 MB SDRAM 16 bit databus width External FLASH memories 256 MB 2Gbit NAND FLASH and 4 MB 32Mbit SPI NOR FLASH 12 0000 MHz crystal for maximum execution speed and standard serial bit rates including CAN and USB requirements 256 Kbit I2C E2PROM for storing non volatile parameters Buffered 16 bit data bus for external expansion 200 pos expansion connector SODIMM 200 format 0 6mm p...

Page 7: ...or a few seconds with both hands before touching any other parts of the boards That way you will have the same electrical potential as the board and therefore minimize the risk for ESD Never touch directly on the LPC3131 41 OEM Board and in general as little as possible on the LPC31xx Base Board The keys on the LPC31xx Base Board have grounded shields to minimize the effect of ESD Note that Embedd...

Page 8: ...d Externally connected cables are assumed to be less than 3 meters The general expansion connectors where internal signals are made available do not have any other ESD protection than from the chip themselves Observe ESD precaution Note that the LPC3131 41 OEM board is classified as a component and is hence not CE marked separately It can perform different functions in different integrations and i...

Page 9: ...adjusted as a power save feature By lowering the voltage the total power consumption can be lowered but the clock frequency of the core must then also be lowered This is a trade off that is important for hand held equipment Note that it is the user s responsibility not to program the LTC3447 to generate too high core voltage which is possible The LTC3447 can generate voltages up to 2V which by far...

Page 10: ...erface is a standard ARM compatible JTAG interface There is a special feature on the LPC3131 41 that can bypass the ARM core scan chain i e the debug access by pulling JTAGSEL low In that case the JTAG interface is used for boundary scan access The multiplexer U17 selects the different scan chain outputs depending on the JTAGSEL signal Normally this has no affect on the operation since the input s...

Page 11: ...s used in the LPC3131 41 OEM Board The LCD interface cannot be used and shall not be enabled in the cpu Also note that three different types of memories share the same bus interface Dynamic memories SDRAM Using signals RAS CAS DQM0 DQM1 CLOCKOUT CKE etc Static memories or general peripherals Using signals OE WE BLOUT0 BLOUT1 etc NAND Flash memories Using signals CLE ALE etc Many of the signals are...

Page 12: ...controls the direction of the data bus buffer During read operations the buffer acts as an input and during write operations it acts as an output Note that N_DBUF_EN must not be pulled low constantly In that case the buffer will collide with the board s internal data bus N_DBUF_EN must only be pulled low when an external memory IO device is accessed If only one of the static chip selects is used e...

Page 13: ...l used for chip select of SPI NOR flash U7 or U10 SPI_SCK SPI_MISO SPI_MOSI SPI_CS_IN Yes but note that SPI NOR flash is connected to SPI_SCK SPI_MISO SPI_MOSI UART_RXD UART_TXD UART_CTS SPI_CS_OUT1 UART_RTS SPI_CS_OUT2 Yes I2SRX_DATA0 I2SRX_WS0 I2SRX_BCK0 I2STX_DATA0 I2STX_WS0 I2STX_BCK0 Yes I2SRX_DATA1 I2SRX_WS1 I2SRX_BCK1 I2STX_DATA1 I2STX_WS1 I2STX_BCK1 Yes GPIO0 GPIO1 GPIO2 Yes but pull ups p...

Page 14: ...le via the address bus buffer EBI_DQM0 NOE EBI_NWE EBI_NCAS BLOUT0 EBI_NRAS BLOUT1 MLCD_CSB EBI_NSTCS0 MLCD_DB1 EBI_NSTCS1 Yes but only available via the buffer NAND_NCS0 MNAND_RYBN0 MCI_DATA4 No used for internal NAND flash memory NAND_NCS1 NAND_NCS2 NAND_NCS3 MNAND_RYBN1 MCI_DATA5 MNAND_RYBN2 MCI_DATA6 MNAND_RYBN3 MCI_DATA7 Yes MLCD_DB0 EBI_CLKOUT MLCD_RS EBI_NDYCS MLCD_RW_WR EBI_DQM1 MLCD_E_RD ...

Page 15: ...Micron and contains 2 GBit capacity The chip may include invalid blocks when shipped from factory A maximum of 40 invalid blocks may exist initially i e 2008 2048 valid blocks Additional invalid blocks may develop while being used Invalid blocks are defined as blocks that contain one or more bad bits Do not erase or program factory marked bad blocks More information about appropriate management of...

Page 16: ... 41 OEM Board 4 1 Usage of CPU Pins Almost all pins of the LPC3131 41 are directly available on the expansion connectors Only in a few cases are pins used for dedicated functionality like dynamic memory control signals and chip select signals Such pins are not available on the expansion connector The table below lists all pins and their possible restrictions Pin Usage on LPC31xx Base Board USB_VBU...

Page 17: ... be used as MCI_CMD MMC SD interface GPIO7 Can be used as MCI_DAT0 MMC SD interface GPIO8 Can be used as MCI_DAT1 MMC SD interface GPIO9 Can be used as MCI_DAT2 MMC SD interface GPIO10 Can be used as MCI_DAT3 MMC SD interface GPIO11 GPIO20 No usage PWM_DATA Can be used to control backlight intensity on QVGA display ADC10B_GPA0 X output from accelerometer ADC10B_GPA1 Y output from accelerometer ADC...

Page 18: ... over the I2S bus and command setting data over the I2C1 bus Transferring I2S data reliable from the codec to the LPC3131 41 requires booting from JTAG or USB UART and SPI booting can create an unreliable connection The problem is under investigation Transferring I2S data to the codec works The I2C address of the UDA1380 is also important to understand The default I2C slave address of LPC313x 4x 5...

Page 19: ... 5V for feeding external USB devices There is a status flag feedback signal from U3 If this is used for example by the latest Linux distribution a jumper must be inserted in J14 pin 9 10 This will bridge the status signal to pin I2SRX_WS0 This jumper is not inserted by default If the over current flag on VBUS circuit is not getting set in case of an over current situation it is a sign of too weak ...

Page 20: ...13 is removed due to fix on v1 1 boards Lower J10 select always enabled or controlled UART select J28 J30 J31 J32 Left pos to RS232 Right pos to XBee module QVGA interface config From left to right J36 J33 J35 J34 UART select J27 J29 Upper pos UART to RS232 XBee Lower pos UART to USB to serial bridge USB Host always J16 insert to always force USB Host UOS_VBAT J23 Select source for UOS_VBAT future...

Page 21: ...xx Base Board Default Jumper Positions 4 3 2 Illegal Jumper Combinations Note that some jumpers are mutual exclusive and should not be inserted simultaneously Note that the spi chip select on the QVGA display touch controller use the signal UART_CTS_SPI_CS_OUT1 Hence a jumper between pin 1 2 on J38 should not be inserted while a jumper on J31 is inserted since RTS from the RS232 interface or CTS f...

Page 22: ...ctors on the LPC31xx Base Board Figure 4 LPC31xx Base Board External Connectors Mic in J42 Line in 1 J44 Line in 2 Line out J48 Headphone J52 MMC SD J12 RS232 DSUB J26 XBee module U10 Power in J24 JTAG J9 USB Host J15 USB OTG J17 Battery connector X2 Expansion J7 Expansion J6 RJ45 Ethernet J56 Expansion J8 QVGA display J37 SODIMM connector X1 USB serial J25 ...

Page 23: ...ard for some important components in the design Figure 5 LPC31xx Base Board Important Components Reset push button and Reset LED Trimming potentiometer for analog input Accelerometer SD MMC Power LED LED5 12 Joystick SW3 Voltage measurement pads and Power LED LED13 USB to serial activity LEDs Current monitor outputs J2 J5 GPIO2 LED LED2 USB VBUS LED LED4 Play button SW1 ...

Page 24: ...D flash The problem is that signals N_STCS0 and N_STCS1 are low during NAND boot The signal DBUF_EN on the LPC31xx Base Board is formed by AND ing N_STCS0 and N_STCS1 This in turn enables the databus buffer U16 on LPC3131 41 OEM Board when the DBUF_EN jumper pin 1 2 on J40 is inserted on the LPC31xx Base Board See Figure 7 to locate DBUF_EN jumper on the LPC31xx Base Board After NAND flash boot is...

Page 25: ...igh when both inputs are low This will also solve the problem since the databus buffer U16 on LPC3131 41 OEM Board will not be enabled during NAND boot when both N_STCS0 and N_STCS1 are low Embedded Artists has created a small board with a XNOR gate that can be soldered to the LPC31xx Base Board This board can be ordered free of charge from the support page The board is delivered with a detailed i...

Page 26: ...a USB It is this serial channel that is the console interface to the system Special USB drivers must be installed on the PC in order for the virtual COM port to be created See Section 5 2 for a description of how to install the FTDI USB driver 5 2 FTDI USB Driver A USB driver must be installed on your PC computer in order to get the USB to UART chip FT232R to function Make sure to download the lat...

Page 27: ... User s Guide Page 27 Copyright 2012 Embedded Artists AB Figure 8 System Settings Dialog Then select the Device Manager and open the Ports list as illustrated in Figure 9 below Figure 9 Device Manager Dialog Ports Device Manager ...

Page 28: ...one flow control as illustrated in Figure 11 below Then select Advanced settings Please note that different application programs can use different baudrate settings for the serial channel Other baudrates can also be used depending on your specific application Also note that it is normally not needed to set the used baudrate at all The driver and FT232R chip will automatically handle different baud...

Page 29: ...eated the second time This problem may occur after every time you start i e power cycle your PC 5 3 Booting The processor will start its code execution from an internal ROM containing the boot code This code determines the boot mode by sampling the reset state of the pins GPIO0 GPIO1 and GPIO2 Multiple boot options are supported Booting from different sources SPI flash NAND flash SD SDHC MMC cards...

Page 30: ...ge since there is no flow control or handshake mechanism implemented in the UART protocol Note that no jumpers need to be set for this boot mode since this is the default However it is good practice to set the jumpers anyways since future revisions or special versions of the LPC3131 41 OEM Board might change default boot mode SPI NOR flash The boot image is stored on the SPI NOR flash A CRC check ...

Page 31: ...ibed GCC EWARM from IAR and uVision from Keil Note that similar settings can be done in IDE s from other vendors and should in general be no problem to implement 5 3 2 1 GCC The first step is to create a pure binary file This is normally done from the build output file often an elf or elf compatible file Under a GCC environment the command to create a binary file named lpc313x bin is arm elf objco...

Page 32: ...fies the input file An output file called lpc313x rom will be generated in the command line example above The normal procedure is to add these commands to the makefile This way no manual operations are needed to create the boot image 5 3 2 2 EWARM from IAR Under EWARM IAR s IDE it is easy to instruct the IDE to generate a binary file Figure 14 below illustrates project settings for automatically g...

Page 34: ...ly create the boot image when compiling building The example below illustrates how to configure a project in uVision the Keil IDE In the Options for Target window select the User tab Then configure the Run 1 and Run 2 options according to the picture below These commands lines are run after the application is built Run 1 creates a binary file named lpc313x bin Run 2 creates a CRC attached rom file...

Page 35: ... 41 5 3 4 Booting via SPI NOR flash When booting via SPI the boot image is downloaded from the SPI NOR flash into LPC3131 41 internal RAM immediately after reset Execution is also started immediately after download No message is sent to the UART channel Downloading a boot image into the SPI NOR flash is a two step process as explained below 1 First set the system to UART boot and download a SPI NO...

Page 36: ... to the LPC31xx Base Board Note that it is the LPC3131 41 USB connection that should be connected to not the UART to serial bridge on the LPC31xx Base Board See Figure 20 for an illustration where the correct USB connector can be found 2 Install DFU drivers available on the Embedded Artists support site 3 Start the DFU application DFUAPP exe The connected LPC3131 41 can be seen in the list of devi...

Page 37: ...oggling GPIO2 pin There is a LED connected to this pin for direct visual feedback The picture below illustrates the position of the LED in relation to the boot jumpers Typical errors could be that booting has timed out must be done within 2 minutes after reset wrong boot image format or CRC error detected in the downloaded boot image Figure 21 GPIO2 LED Position GPIO2 LED Step 4 select boot image ...

Page 38: ...oot or Apex bootloaders to program the NAND flash on the LPC31xx OEM Boards with a bootable image Please follow the links below for more information Program NAND flash using u boot http www lpclinux com LPC313x LPC313xUbootNand Programming_NAND_flash_using_Uboot Program NAND flash using Apex http www lpclinux com LPC313x LPC313xApexNand Programming_NAND_flash_using_Apex ...

Page 39: ...loper s Guide Designing and Optimizing System Software by A N Sloss D Symes C Wright Elsevier ISBN 1 55860 874 5 8 ARM9 vs ARM7 core comparison This document from ARM gives a good overview of the ARM9 core compared to the ARM7 core that for example is found in the LPC2xxx family http www arm com pdfs comparison arm7 arm9 v1 pdf 9 Embedded System Design on a Shoestring by Lewin Edwards Newnes ISBN ...

Page 40: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Embedded Artists EA OEM 315 ...

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