LPC3131/41 Developer’s Kit - User’s Guide
Page 10
Copyright 2012 © Embedded Artists AB
3.1.2
Page 3: LPC3131/41 CPU
Page 3 of the schematic contains the core part of the design, which of course is the LPC3131/41
microcontroller. It is an ARM926EJ-S cpu core with a lot of different peripheral units and on-chip
memory (192 KByte SRAM).
3.1.2.1
12MHx Crystal and PLLs
The microcontroller crystal frequency is 12.0000 MHz. This frequency is the recommended from NXP.
There is dual on-chip PLLs on the LPC3131/41 in order to generate different needed frequencies for
the chip.
Note that the clocking structure is very different from the LPC2xxx family. It is a more
complex structure but also much more versatile and flexible. There is no shortcut but to read
the LPC3131/41 User’s Manual in detail and understand the options and settings
.
The main thing differing between the LPC3131 and the LPC3141 is the maximum core frequency for
the processor. See datasheet for details.
3.1.2.2
Booting
The LPC3131/41 starts executing from an on-chip ROM, containing the bootloader. Note that the
LPC3131/41 does not contain any on-chip FLASH memory. Program code must be loaded from an
external source into the on-chip SRAM.
There are multiple boot options, as indicated in the schematic. The default is set to UART mode
booting. Normally the default boot option can be controlled/changed from the
LPC31xx Base Board
,
but the default resistors can also be changed for special orders of the board. The
LPC3131/41 OEM
Board
contains both SPI NOR flash and NAND flash in order to support stand alone booting.
Section 4.6
contains important information if NAND boot is used.
3.1.2.3
JTAG interface
The JTAG interface is a standard ARM-compatible JTAG interface. There is a special feature on the
LPC3131/41 that can bypass the ARM core scan chain (i.e. the debug access), by pulling JTAGSEL
low. In that case, the JTAG interface is used for boundary scan access. The multiplexer (U17) selects
the different scan chain outputs depending on the JTAGSEL signal. Normally this has no affect on the
operation since the input signal JTAG_DBGEN (connected to JTAGSEL) is held high.
3.1.2.4
SPI NOR FLASH
There is a 32Mbit (4 MByte) NOR flash connected to the SPI bus. There is an option to mount one of
two different manufacturers; either S25FL032 from Spansion or AT45DB321 from Atmel. Embedded
Artists can choose to mount any one of these chips (or similar) on the board and it depends on
component availability at the time of production. Both are compatible for the relevant commands. In
case special commands are used, it is possible to read out chip id and determine type.
3.1.2.5
Reset Generation
The reset generation is handled by a standard voltage supervisor chip, CAT811R from Catalyst
Semiconductor. The reset signal will be held active (i.e., low) until the supply voltages, +3.3V, is within
margins (above 2.63V). The reset duration is typically 200 mS (consult the CAT811R datasheet for
exact details). The output reset signal is push/pull output that is converted to an open-collector / open-
drain output via the 74LVC1G125 buffer. An external reset source can pull the reset signal low (with an
open-collector/open-drain output).
3.1.2.6
I2C E2PROM
There is a 256 kbit E
2
PROM accessible via the I
2
C interface. The LPC3131/41 has two on-chip I
2
C
communication channels. Channel #0 is used for communicating with the E
2
PROM. More peripheral
units are easily connected to the two-wire I
2
C bus, just as long as the addresses do not collide. The
address of the 256kbit E
2
PROM is 0xA0, which is also indicated in the schematic.
