SC9-TOCCATA • CompactPCI® Serial CPU Board • 11th Generation Intel® Processors
CompactPCI® Serial Backplane Connectors
The SC9-TOCCATA is provided with five high speed backplane connectors P1 - P5, compliant with
the CompactPCI® Serial specification (pin mapping for system boards with respect to
SC9-TOCCATA).
The PCI Express® links/lanes 1_PE_* to 2_PE_* are derived directly from the processor and
theoretically capable to transfer 16GT/s (PCIe® Gen4). Since only Gen1-3 is specified for
CompactPCI® Serial and the AirMax VS® backplane connectors J/P1-J/P6, the maximum Gen4
transfer rate cannot be guaranteed (depends e.g. on backplane characteristics and peripheral
card). For details of the connectors please visit Amphenol-ICC (formerly FCI).
The SC9-TOCCATA will be available also with AirMax VSe® backplane connectors for doubling the
data transfer rate to PCIe® Gen4, as VC1-TOCCATA. As of current the alternate connectors are part
of the PICMG® CompactPCI® Serial Extension (CPCI-SX®) working group.
The 1_PE and 2_PE links are assigned via the backplane to the CompactPCI® Serial fat pipe slots,
for a maximum link width of x8 each.
3_PE to 8_PE are 8GT/s (PCIe® Gen3) links. While the 3_PE link provides x4 support, the remaining
links 4_PE to 8_PE are organized x1.
The CompactPCI® Serial connector pin assignment distinguishes positive/negative (+/-) PCIe®
differential signals. However, polarity inversion may be used on several lanes for optimum PCB
routing. This is allowed according the PCI Express® Base Specification and has no effect on
function or performance of the respective link. The pin-out shown is as per specification.
If backplane Ethernet shall be supported, P6 is available as an option on a low profile mezzanine
module (S8* series), with up to 8 ports (switch based) or 4 ports (NICs). A pin assignment for P6 is
not part of this document. Instead, refer to the mezzanine modules Technical Information, e.g.
https://www.ekf.com/s/s80/s80.html or https://www.ekf.com/s/s82/s82.html.
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