SC9-TOCCATA • CompactPCI® Serial CPU Board • 11th Generation Intel® Processors
HSE1 Mezzanine Connector
High Speed Expansion HSE1
GND
a1
b1
GND
1_PCIE_TXP
a2
b2
3_PCIE_TXP
1_PCIE_TXN
a3
b3
3_PCIE_TXN
GND
a4
b4
GND
1_PCIE_RXN
a5
b5
3_PCIE_RXN
1_PCIE_RXP
a6
b6
3_PCIE_RXP
GND
a7
b7
GND
2_PCIE_TXP
a8
b8
4_PCIE_TXP
2_PCIE_TXN
a9
b9
4_PCIE_TXN
GND
a10
b10
GND
2_PCIE_RXN
a11
b11
4_PCIE_RXN
2_PCIE_RXP
a12
b12
4_PCIE_RXP
GND
a13
b13
GND
1_USB2_P
a14
b14
2_USB3_TXP
1_USB2_N
a15
b15
2_USB3_TXN
GND
a16
b16
GND
2_USB2_P
a17
b17
2_USB3_RXP
2_USB2_N
a18
b18
2_USB3_RXN
GND
a19
b19
GND
1_2_USB_OC#
a20
b20
PCIE_CLK_P
PLTRST#
a21
b21
PCIE_CLK_N
+3.3VS
1)
a22
b22
+5VS
1)
+3.3VS
1)
a23
b23
+5VS
1)
+3.3VA
3)
a24
b24
+5VPS
2)
+12VPS
2)
a25
b25
+12VPS
2)
1) Power rail switched on in S0 state only
2) Power rail switched on in S0-S4 state
3) Power always on
The HSE1 PCIe® lanes are derived from the Tiger Lake processor (Gen4 capable, fixed x4 link)
a1
s1
s9
s18
s10
a25 b25
b1
1.
00
mm
Pitch
High S
peed F
ema
le Con
ne
ctor
(H=8m
m
)
© EK
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