Trion T20 BGA256 Development Kit User Guide
Clock Sources
Two on-board oscillators, 50 MHz and 74.25 MHz, are available to drive the T20F256C PLL
input pin and clock input. Alternatively, you can disable the 50 MHz oscillator and use an
external clock source through the SMA input (J5). Set jumper J3 to use the 50 MHz or SMA
input as the clock source.
Clock Source
PLL Input Pin
Clock Input Pin
50 MHz oscillator or SMA input
GPIOR_157_PLLIN
GPIOR_125_CLK10
74.25 MHz oscillator
GPIOL_75_PLLIN1
–
You can supply a clock to the PLL or clock network in the FPGA through a board header.
Refer to H2, H3, and H4 under
on page 7 for the dedicated clock pins.
Headers
The board contains a variety of headers to provide power, inputs, and outputs, and to
communicate with external devices or boards.
Table 1: Trion
™
T20 BGA256 Development Board Headers
Reference Designator
Description
CON1
5 V DC power supply input jack
CON2
Micro-USB Type-AB receptacle
CON3
34-pin header for LVDS receiver (RX) and LVDS receiver clock (CLK)
CON4
34-pin header for LVDS transmitter (TX)
H1
SPI header
H2
36-pin header for bank 1D and 1E I/O
H3
36-pin header for bank 3 I/O
H4
36-pin header for bank 1B and 1C I/O
H6
JTAG header
H7
Selects 3.3 V, 2.5 V, or 1.8 V power for banks 1B and 1C
H8
Selects 3.3 V, 2.5 V, or 1.8 V power for banks 1D and 1E
J1
2-pin header for 5 V output
J3
3-pin header to select whether to use the on-board 50 MHz oscillator or SMA input
from external clock source
J5
SMA connector for external 3.3 V clock source input
Header CON1 (5 V Power)
CON1 is a 5 V DC power supply input jack. CON1 supplies power to regulators on the
board that power the T20F256C FPGA. The maximum current supply to this input jack is
4 A.
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