E.F. Johnson Company 5100 Series, Service Manual

Page: 43 / 173

CIRCUIT DESCRIPTION
5-16
loop divider's output signal with the signal from
U304 (that is divided down after it is applied to pin
14 of U302). The result of the signal comparison is
a pulsed DC signal which is applied to the charge
pump.
•
The charge pump outputs a current that is present at
pin 32 of U302. The loop filter (which consists of
capacitors C322, C317, C318, C329, C324, and
C315, and resistors R307, R305, and R314) trans-
forms this current into a voltage that is applied to
pins 1 and 7 of U307 to alter the VCO's output
frequency.
In order to modulate the PLL, the two-port modu-
lation method is utilized. The analog modulating
signal is applied to the A/D converter as well as the
balance attenuator, via U302, pin 5. The A/D converter
converts the low-frequency analog modulating signal
into a digital code that is applied to the loop divider,
thereby causing the carrier to deviate. The balance
attenuator is used to adjust the VCO's deviation sensi-
tivity to high-frequency modulating signals.
5.7.2 ANTENNA SWITCH
An electronic PIN diode switch steers RF
between the receiver and transmitter. The common
node of the switch is at capacitor C101. In the transmit
mode, RF is routed to the anode of diode CR104. In
receive mode, RF is routed to pin 1 of U201. In the
transmit mode, bias current sourced from U504, pin
21, is routed through PIN diodes CR104 and CR102
which biases them to a low-impedance state. Bias
current returns to ground through U504, pin 20. In
receive, U504, pin 21, is pulled down to ground and
pin 20 is pulled up to B+ which reverse-biases diodes
CR104 and CR102 to a high impedance.
5.7.3 RECEIVER FRONT END
The 800 MHz receiver front end converts the
received RF signal to the first IF frequency of 73.35
MHz and also provides spurious immunity and adja-
cent channel selectivity. The received RF signal is
passed through antenna switch input matching compo-
nents C101, L105, and C114, through tank compo-
nents C106 and L103 (which are anti-resonant at the
radios transmitter frequencies), and through output
matching components C103 and L104. Both pin
diodes CR102 and CR104 must be back-biased to
properly route the received signal.
The stage following the antenna switch is a 50-
ohm, inter-digitated, three-pole, stripline preselector
(U201). The preselector is positioned after the antenna
switch to provide the receiver preamp with some
protection against strong, out-of-band signals.
After the preselector (U201), the received signal
is processed through receiver preamp U202. The
preamp is a dual-gate, GaAs MESFET transistor
which has been internally biased for optimum IM, NF,
and gain performance. Components L201 and L202
match the input (gate 1) of the amp to the first prese-
lector, while at the same time connecting gate 1 to
ground potential. The output (drain) of the amp is pin
7, and is matched to the subsequent receiver stage by
L204 and C222. A supply voltage of 5V DC is
provided to pin 3 through RF choke L203 and bypass
capacitor C204. The 5-volt supply is also present at
pin 4, which connects to a voltage divider network that
biases gate 2 (pin 5) to a predefined quiescent voltage
of 1.2V DC. Resistor R202 and capacitor C203 are
connected to pin 5 to provide amp stability. The FET
source (pin 3) is internally biased at 0.55 to 0.7VDC
for proper operation with bypass capacitors C201 and
C202, connected to the same node.
The output of the amp is matched to a second
three-pole preselector (U203) of the type previously
discussed. The next stage in the receiver chain is first
mixer U205 which uses low-side injection to convert
the RF carrier to an intermediate frequency (IF) of
73.35 MHz.
Since low-side injection is used, the LO
frequency is offset below the RF carrier by 73.35
MHz, or fLO = fRF - 73.35 MHz. The mixer utilizes
GaAs FETs in a double-balanced, Gilbert Cell config-
uration. The LO port (pin 8) incorporates an internal
buffer and a phase shift network to eliminate the need
for a LO transformer. The LO buffer bypass capacitors
(C208, C221, and C216) are connected to pin 10 of
U205, and should exhibit a nominal DC voltage of 1.2
to 1.4V DC. Pin 11 of U205 is LO buffer Vdd (5V
DC), with associated bypass capacitors C226 and
C209 connected to the same node. An internal voltage
divider network within the LO buffer is bypassed to
virtual ground at pin 12 of U205 through bypass
800 MHz RF BOARD (VERSION A/B)