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XM_VATP_TX0/1_DCOUNT

[0x0418, 0x0430] TX FIFO Data Count Port (read only)

TX FIFO Data Count

Data Bit

Description

31-12

Spare

11-0

FIFO Data Words Stored

FIGURE 20

PMC-XM VIRTEX (ATP) CHANNEL TX FIFO COUNT PORT

These read-only register ports report the number of 32-bit data words in the
corresponding transmit FIFO (currently a maximum of 0xFFF).

XM_VATP_RX0/1_DCOUNT

[0x041C, 0x0434] RX FIFO Data Count Port (read only)

RX FIFO Data Count

Data Bit

Description

31-12

Spare

11-0

FIFO Data Words Stored

FIGURE 21

PMC-XM VIRTEX (ATP) CHANNEL RX FIFO COUNT PORT

These read-only register ports report the number of 32-bit data words in the
corresponding receive FIFO (currently a maximum of 0xFFF).

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Summary of Contents for PMC-XM-DIFF

Page 1: ...ttp www dyneng com sales dyneng com Est 1988 User Manual PMC XM DIFF Interface Module with Re configurable I O logic RS 485 or LVDS or mixed 34 Differential Pairs at Bezel 32 Differential Pairs at Pn4 Revision A Corresponding Hardware Revision A 10 2007 0201 Corresponding Firmware Revision A ...

Page 2: ...es in the product described in this document at any time and without notice Furthermore Dynamic Engineering assumes no liability arising out of the application or use of the device described herein The electronic equipment described herein generates uses and can radiate radio frequency energy Operation of this equipment in a residential area is likely to cause radio interference in which case the ...

Page 3: ...1_WR RD_DMA_PNTR 19 XM_CHAN0 1_FIFO 19 XM_CHAN0 1_TX_AMT_LVL 20 XM_CHAN0 1_RX_AFL_LVL 20 XM_CHAN0 1_TX RX_FIFO_COUNT 21 ADDRESS MAP VIRTEX ATP DESIGN 22 Register Definitions 23 XM_VATP_BASE 23 XM_VATP_STATUS 25 XM_VATP_CHAN0 1_CNTRL 26 XM_VATP_CHAN0 1_STATUS 27 XM_VATP_TX0 1_FIFO 28 XM_VATP_RX0 1_FIFO 28 XM_VATP_TX0 1_DCOUNT 29 XM_VATP_RX0 1_DCOUNT 29 VIRTEX PIN OUT 30 TRANSITION MODULE MECHANICAL...

Page 4: ...DULE CONNECTOR J2 41 APPLICATIONS GUIDE 42 Interfacing 42 Construction and Reliability 43 Thermal Considerations 43 WARRANTY AND REPAIR 44 Service Policy 44 Out of Warranty Repairs 44 For Service Contact 44 SPECIFICATIONS 45 ORDER INFORMATION 46 ...

Page 5: ...EMPTY PORT 20 FIGURE 11 PMC XM SPARTAN3 CHANNEL RX ALMOST FULL PORT 20 FIGURE 12 PMC XM SPARTAN3 CHANNEL TX RX FIFO COUNT PORT 21 FIGURE 13 PMC XM VIRTEX ATP XILINX ADDRESS MAP 22 FIGURE 14 PMC XM VIRTEX ATP BASE CONTROL REGISTER 23 FIGURE 15 PMC XM VIRTEX ATP BASE STATUS PORT 25 FIGURE 16 PMC XM VIRTEX ATP CHANNEL CONTROL REGISTER 26 FIGURE 17 PMC XM VIRTEX ATP CHANNEL STATUS PORT 27 FIGURE 18 PM...

Page 6: ...trolled and length matched within the mil 001 to allow for any user requirement Other features include on board PLL optional RAM 1Mx36 bit QDDRII RAM temperature sensor DIP Switch Built in DMA and user LED s PCI IF Data Flow Control FPGA 1M x 36 RAM DMA RX TX 4Kx32 FIFO 4Kx32 FIFO RX TX 4Kx32 FIFO 4Kx32 FIFO User Virtex PLL 34 LVDS RS 485 IO Programmable Terminations LEDs 4 DIPSWITCH TEMP SENSOR F...

Page 7: ...different designs loaded into the Virtex The user can change the design number and use the generic driver to access new features added to the clients implementation The Virtex can be loaded from FLASH and overwritten with software The reference package includes the Virtex load utilities PLL programming software and Temperature sensor read as well as IO loop back tests ...

Page 8: ...s accessible by the Virtex for intermediate processing of I O data and a 13 bit digital temperature sensor can be used to read the ambient temperature of the PMC XM environment Scatter gather DMA is accomplished by writing a list of memory descriptors to host memory Each descriptor consists of three long words the physical address of a block of contiguous user memory the length of that block and a...

Page 9: ...sNT there is a system registry which is used to identify the resident hardware To use DMA it will be necessary to acquire a block of non paged memory that is accessible from the PCI bus in which to store chaining descriptor list entries At Dynamic Engineering the PMC XM DIFF is tested in a Windows environment and we use the Dynamic Engineering Drivers to do the hardware accesses and manage the DMA...

Page 10: ...R_DMA_PNTR 0x0048 Channel 1 Write DMA physical address register XM_CHAN1_RD_DMA_PNTR 0x004C Channel 1 Read DMA physical address register XM_CHAN1_FIFO 0x0050 Channel 1 FIFO offset for single word access XM_CHAN1_TX_AMT_LVL 0x0054 Channel 1 TX almost empty level register offset XM_CHAN1_RX_AFL_LVL 0x0058 Channel 1 RX almost full level register offset XM_CHAN1_TX_FIFO_COUNT 0x005C Channel 1 TX FIFO ...

Page 11: ... is a 0 the interrupt is disabled Currently the only interrupt source for this portion of the design is the Force Interrupt bit Force Interrupt When this bit is 1 and the Master Interrupt Enable is 1 an interrupt will be generated This bit is useful for software development and debugging Flash Control When this bit is 1 the Flash Select bit controls which Flash Prom is connected to the JTAG port W...

Page 12: ...res from the on board flash Virtex Flash Enable When this bit is 0 and the Virtex Program Select bit is 1 the Virtex flash is disabled so that the Spartan3 can program the Virtex from a bit file Virtex Reset When this bit is 1 all the registers and FIFOs in the Virtex are reset When this bit is 0 the Virtex can resume normal operation Virtex Init When set to 1 this bit delays configuration when a ...

Page 13: ...TCH PORT Sw7 0 The user switch is read through this read only port The bits are read as the lowest byte Access the port as a long word and mask off the undefined bits The dip switch positions are defined in the silkscreen For example the switch figure below indicates a 0x12 Xilinx design revision number The value of the second byte of this port is the rev number of the Xilinx design currently 0x05...

Page 14: ... no local interrupt conditions are active Virtex Configuration Done When read as a 1 the Virtex FPGA has successfully configured When read as a 0 the Virtex configuration was not successful Virtex Init Status When read as a 1 after the Virtex configuration it indicates that a CRC error did not occur during the Virtex configuration When read as a 0 after the Virtex configuration it indicates that a...

Page 15: ... will be transferred to the receive FIFO as long as there is room in the receive FIFO This facilitates FIFO loop back testing When this bit is 0 data written to the transmit FIFO will remain in the FIFO until read by the data transfer state machine DMA Write Enable When this bit is 1 the write DMA interrupt is enabled for the referenced channel When this bit is 0 the write DMA interrupt is disable...

Page 16: ...s bit is 1 the corresponding Virtex interrupt VINT0 for channel 0 or VINT1 for channel 1 is enabled to cause a system interrupt when active When this bit is 0 the Virtex interrupt can not cause a system interrupt DMA Write Arbitration Priority Enable When this bit is 1 the write DMA for the referenced channel will receive priority if the TX FIFO has become almost empty as defined by the value stor...

Page 17: ...y When read as a 0 the FIFO has at least one word in it Transmit FIFO Almost Empty When read as a 1 the corresponding transmit FIFO is almost empty as determined by the value entered in the almost empty level register When read as a 0 there is more data in the FIFO than specified in the level register Transmit FIFO Full When read as a 1 the corresponding transmit FIFO is full When read as a 0 ther...

Page 18: ... 1 a write DMA interrupt is latched This indicates that the scatter gather list for the current write DMA has completed but the associated interrupt has yet to be completely processed When read as a 0 no write DMA interrupt is pending Read DMA Interrupt Active When read as a 1 a read DMA interrupt is latched This indicates that the scatter gather list for the current read DMA has completed but the...

Page 19: ... buffer the second is the length in bytes of that block and the third is the address of the next chaining descriptor in the list of buffer memory blocks This process is continued until a bit in one of the next pointer values read indicates that it is the end of the chain Note Writing a zero to one of these ports will abort the associated DMA if one is in progress XM_CHAN0 1_FIFO 0x0020 0x0050 Writ...

Page 20: ... number of data words in the transmit FIFO is less than or equal to this count the almost empty status will be asserted XM_CHAN0 1_RX_AFL_LVL 0x0028 0x0058 RX Almost Full Level Register read write RX Almost Full Level Register Data Bit Description 31 16 Spare 15 0 RX FIFO Almost Full Level FIGURE 11 PMC XM SPARTAN3 CHANNEL RX ALMOST FULL REGISTER This register specifies the level at which the rece...

Page 21: ...Data Count Data Bit Description 31 16 Spare 15 0 FIFO Data Words Stored FIGURE 12 PMC XM SPARTAN3 CHANNEL TX RX FIFO COUNT PORT These read only register ports report the number of 32 bit data words in the corresponding transmit receive FIFO and data pipeline currently a maximum of 0x1000 for the transmit and 0x1003 for the receive ...

Page 22: ...rt offset XM_VATP_RX0_DCOUNT 0x041C Channel 0 RX FIFO count read port offset XM_VATP_CHAN1_CNTRL 0x0420 Channel 1 Control register offset XM_VATP_CHAN1_STATUS 0x0424 Channel 1 Status read latch clear port offset XM_VATP_TX1_FIFO 0x0428 Channel 1 TX FIFO offset for single word access XM_VATP_RX1_FIFO 0x042C Channel 1 RX FIFO offset for single word access XM_VATP_TX1_DCOUNT 0x0430 Channel 1 TX FIFO ...

Page 23: ...upt 0 1 Enable When this bit is 1 the corresponding interrupt is enabled VINT0 or VINT1 When this bit is 0 the interrupt is disabled Force Interrupt 0 1 When this bit is 1 and the corresponding interrupt enable is set that interrupt will be asserted from the Virtex Reset DCM When this bit is 1 the DCM Digital Clock Manager will be manually reset When this bit is 0 the DCM will operate normally PLL...

Page 24: ...e and toggle the clock line and repeat The upper selection bit can be set in the register and directly driven to the PLL This allows the selection of alternative pre programmed clock frequencies To read over the I 2 C bus a command is first written and then the bus read for the response The I 2 C data input bit in the status register contains the state of the bus when read The software will toggle...

Page 25: ... the control status register configuration and which driver to use to communicate with the design DCM Locked When read as a 1 it indicates that the DCM is in a locked state and the clocks produced are functioning reliably When read as a 0 it indicates that the DCM is not locked and therefore the clocking is not reliable Intstat0 1 When read as a 1 it indicates that the corresponding interrupt is a...

Page 26: ...When this bit is 0 the interrupt is disabled This bit has a parallel function with the interrupt enable bits in the base control register Force Interrupt When this bit is 1 and the corresponding interrupt enable is set that interrupt will be asserted from the Virtex This bit has a parallel function with the force interrupt bits in the base control register Transmit FIFO Almost Empty Level This fie...

Page 27: ...a 0 there is more data in the FIFO than specified in the control register Transmit FIFO Almost Full When read as a 1 the corresponding transmit FIFO is almost full The almost full level is hard coded to 4080 words When read as a 0 there are less than this number of words in the FIFO Transmit FIFO Full When read as a 1 the corresponding transmit FIFO is full When read as a 0 there is room for at le...

Page 28: ...31 0 FIGURE 18 PMC XM VIRTEX ATP CHANNEL TX FIFO PORT Data written to this address is written into the transmit FIFO as long as the FIFO is not full When this address is read a data word is read from the transmit FIFO When the FIFO becomes empty the last data word that was in the FIFO will be returned XM_VATP_RX0 1_FIFO 0x0414 0x042C RX FIFO Port read write RX FIFO Port Data Bit Description 31 0 F...

Page 29: ...register ports report the number of 32 bit data words in the corresponding transmit FIFO currently a maximum of 0xFFF XM_VATP_RX0 1_DCOUNT 0x041C 0x0434 RX FIFO Data Count Port read only RX FIFO Data Count Data Bit Description 31 12 Spare 11 0 FIFO Data Words Stored FIGURE 21 PMC XM VIRTEX ATP CHANNEL RX FIFO COUNT PORT These read only register ports report the number of 32 bit data words in the c...

Page 30: ... V VD 7 B7 Bidir LVCMOS 3 3 V VD 8 A7 Bidir LVCMOS 3 3 V VD 9 B9 Bidir LVCMOS 3 3 V VD 10 A8 Bidir LVCMOS 3 3 V VD 11 B10 Bidir LVCMOS 3 3 V VD 12 A9 Bidir LVCMOS 3 3 V VD 13 B12 Bidir LVCMOS 3 3 V VD 14 A10 Bidir LVCMOS 3 3 V VD 15 B13 Bidir LVCMOS 3 3 V VD 16 A11 Bidir LVCMOS 3 3 V VD 17 B14 Bidir LVCMOS 3 3 V VD 18 A12 Bidir LVCMOS 3 3 V VD 19 B15 Bidir LVCMOS 3 3 V VD 20 A15 Bidir LVCMOS 3 3 V...

Page 31: ...3 3 V VDMA_RDY_W0 C17 Output LVCMOS 3 3 V VDMA_RDY_W1 C19 Output LVCMOS 3 3 V VDMA_RDY_R0 C15 Output LVCMOS 3 3 V VDMA_RDY_R1 C16 Output LVCMOS 3 3 V VDMA_MT_R0 C20 Output LVCMOS 3 3 V VDMA_MT_R1 C21 Output LVCMOS 3 3 V VINT0 D6 Output LVCMOS 3 3 V VINT1 D7 Output LVCMOS 3 3 V VSTAT 0 D9 Output LVCMOS 3 3 V VSTAT 1 D10 Output LVCMOS 3 3 V VSTAT 2 D11 Output LVCMOS 3 3 V VSTAT 3 D12 Output LVCMOS 3...

Page 32: ...VCMOS 3 3 V DOUT_TEMP AC26 Input LVCMOS 3 3 V SS_N N25 Output LVCMOS 2 5 V RF_RST J26 Output LVCMOS 2 5 V RF_PWC_PWM K25 Output LVCMOS 2 5 V RF_AGC_PWM M25 Output LVCMOS 2 5 V GPIO1 AE24 Input LVCMOS 3 3 V GPIO2 AF24 Input LVCMOS 3 3 V GPIO3 W23 Input LVCMOS 3 3 V GPIO4 AA23 Input LVCMOS 3 3 V DAC_PDWN W26 Output LVCMOS 3 3 V DAC_MUXSEL V21 Output LVCMOS 3 3 V DAC_WRT0 AC23 Output LVCMOS 3 3 V DAC...

Page 33: ...DC_DCS F20 Output LVCMOS 3 3 V ADC_DFS G23 Output LVCMOS 3 3 V ADC_MUXSEL G18 Output LVCMOS 3 3 V ADC_REFSEL E17 Output LVCMOS 3 3 V ADC_OTR0 F19 Input LVCMOS 3 3 V ADC_CLK0 H21 Output LVCMOS 3 3 V ADC_OEB0 G19 Output LVCMOS 3 3 V ADC_PDWN0 E18 Output LVCMOS 3 3 V ADC_OTR1 F18 Input LVCMOS 3 3 V ADC_CLK1 E21 Output LVCMOS 3 3 V ADC_OEB1 H20 Output LVCMOS 3 3 V ADC_PDWN1 G20 Output LVCMOS 3 3 V RX_...

Page 34: ... V RX_ADC_Q 13 F24 Input LVCMOS 3 3 V QDR_CQ U1 Input HSTL_I_DCI 1 8 V QDR_K P3 Output HSTL_I 1 8 V QDR_KN P2 Output HSTL_I 1 8 V QDR_W L4 Output HSTL_I 1 8 V QDR_R J7 Output HSTL_I 1 8 V QDR_BWN 0 K7 Output HSTL_I 1 8 V QDR_BWN 1 K4 Output HSTL_I 1 8 V QDR_BWN 2 K6 Output HSTL_I 1 8 V QDR_BWN 3 N2 Output HSTL_I 1 8 V QDR_IN 0 AD6 Input HSTL_I_DCI 1 8 V QDR_IN 1 AB5 Input HSTL_I_DCI 1 8 V QDR_IN 2...

Page 35: ...IN 30 R8 Input HSTL_I_DCI 1 8 V QDR_IN 31 U4 Input HSTL_I_DCI 1 8 V QDR_IN 32 V1 Input HSTL_I_DCI 1 8 V QDR_IN 33 T8 Input HSTL_I_DCI 1 8 V QDR_IN 34 W4 Input HSTL_I_DCI 1 8 V QDR_IN 35 AB1 Input HSTL_I_DCI 1 8 V QDR_OUT 0 AD4 Output HSTL_I 1 8 V QDR_OUT 1 AD5 Output HSTL_I 1 8 V QDR_OUT 2 AB6 Output HSTL_I 1 8 V QDR_OUT 3 Y6 Output HSTL_I 1 8 V QDR_OUT 4 V7 Output HSTL_I 1 8 V QDR_OUT 5 U7 Output...

Page 36: ..._I 1 8 V QDR_ADDR 0 M6 Output HSTL_I 1 8 V QDR_ADDR 1 J4 Output HSTL_I 1 8 V QDR_ADDR 2 J5 Output HSTL_I 1 8 V QDR_ADDR 3 K3 Output HSTL_I 1 8 V QDR_ADDR 4 M5 Output HSTL_I 1 8 V QDR_ADDR 5 AA4 Output HSTL_I 1 8 V QDR_ADDR 6 AC2 Output HSTL_I 1 8 V QDR_ADDR 7 AC3 Output HSTL_I 1 8 V QDR_ADDR 8 AB3 Output HSTL_I 1 8 V QDR_ADDR 9 AB4 Output HSTL_I 1 8 V QDR_ADDR 10 AE4 Output HSTL_I 1 8 V QDR_ADDR 1...

Page 37: ...ed Solutions Page 37 of 46 PLL_SDAT E1 Bidir LVCMOS 3 3 V PLL_CLKA D2 Input LVCMOS 3 3 V PLL_CLKB D1 Input LVCMOS 3 3 V D7_0 AF20 Output LVCMOS 3 3 V D7_1 AB20 Output LVCMOS 3 3 V D7_2 W21 Output LVCMOS 3 3 V ...

Page 38: ...CMOS 2 5 V D9_21 K21 Output LVCMOS 2 5 V D9_22 V25 Output LVCMOS 2 5 V D9_23 V26 Output LVCMOS 2 5 V D9_24 R23 Output LVCMOS 2 5 V D9_25 R24 Output LVCMOS 2 5 V D9_26 R25 Output LVCMOS 2 5 V D9_27 U22 Output LVCMOS 2 5 V D9_28 U23 Output LVCMOS 2 5 V D9_29 U24 Output LVCMOS 2 5 V D9_30 U25 Output LVCMOS 2 5 V I O Standard Acronyms LVCMOS Low Voltage Complimentary Metal Oxide Semiconductor HSTL_I H...

Page 39: ...Embedded Solutions Page 39 of 46 Transition Module Mechanical Drawing ...

Page 40: ...9 D9_16 RX_ADC_I5 31 70 D9_15 RX_ADC_I4 30 71 D9_14 RX_ADC_I3 29 72 D9_13 RX_ADC_I2 28 73 D9_12 RX_ADC_I1 27 74 GND RX_ADC_I0 26 75 ADC_OTR1 GND 25 76 GND RX_ADC_Q13 24 77 D9_11 RX_ADC_Q12 23 78 D9_10 RX_ADC_Q11 22 79 D9_9 RX_ADC_Q10 21 80 D9_8 RX_ADC_Q9 20 81 D9_7 RX_ADC_Q8 19 82 D9_6 RX_ADC_Q7 18 83 D9_5 RX_ADC_Q6 17 84 D9_4 RX_ADC_Q5 16 85 D9_3 RX_ADC_Q4 15 86 D9_2 RX_ADC_Q3 14 87 D9_1 RX_ADC_Q...

Page 41: ... GPIO4 GND 30 71 GPIO3 GND 29 72 GPIO2 GND 28 73 GPIO1 GND 27 74 D7_0 GND 26 75 GND GND 25 76 DAC_CLK1 GND 24 77 GND GND 23 78 DAC_WRT1 GND 22 79 GND GND 21 80 GND GND 20 81 TX_DAC_Q9 GND 19 82 TX_DAC_Q8 GND 18 83 TX_DAC_Q7 GND 17 84 TX_DAC_Q6 GND 16 85 TX_DAC_Q5 GND 15 86 TX_DAC_Q4 GND 14 87 TX_DAC_Q3 GND 13 88 TX_DAC_Q2 GND 12 89 TX_DAC_Q1 GND 11 90 TX_DAC_Q0 GND 10 91 GND GND 9 92 DAC_PDWN GND ...

Page 42: ...it Many BIOS will display the PCI devices found at boot up on a splash screen with the VendorID and CardId and an interrupt level Look quickly If the information is not available from the BIOS then a third party PCI device cataloging tool will be helpful We use PCIView Watch the system grounds All electrically connected equipment should have a fail safe common ground that is large enough to handle...

Page 43: ...ow temperature coefficient of 2 17 W C for uniform heat This is based upon the temperature coefficient of the base FR4 material of 0 31 W m C and taking into account the thickness and area of the PMC The coefficient means that if 2 17 Watts are applied uniformly on the component side then the temperature difference between the component side and solder side is one degree Celsius Thermal Considerat...

Page 44: ...ompany the return Dynamic Engineering will not be responsible for damages due to improper packaging of returned items For service on Dynamic Engineering Products not purchased directly from Dynamic Engineering contact your reseller Products returned to Dynamic Engineering for repair by other than the original customer will be treated as out of warranty Out of Warranty Repairs Out of warranty repai...

Page 45: ...ardware reset forces all registers to zero except as noted Access Modes All registers on long word boundary Standard target accesses read and write to registers and memory DMA access to memory Access Time No wait states in DMA modes One wait state in target access to Spartan3 Virtex accesses are user defined Interrupt One interrupt to the PCI bus is supported with multiple sources The interrupts a...

Page 46: ...nel standard XM timing and protocol PMC XM Eng 1 Engineering Kit for the PMC XM Board level schematics PDF and Sample Virtex design VHDL PMC XM Eng 2 Engineering Kit for the PMC XM Board level schematics PDF Sample Virtex Design VHDL Software Drivers and Sample Test Application All information provided is Copyright Dynamic Engineering ...

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