Embedded Solutions
Page 28 of 46
‘0’, there is less data in the FIFO than specified in the control register.
Receive FIFO Full: When read as a ‘1’, the corresponding receive FIFO is full. When
read as a ‘0’, there is room for at least one more word in the FIFO.
INT_STAT: When read as a ‘1’, the corresponding interrupt is active (VINT0 for channel
0 or VINT1 for channel 1). When read as a ‘0’, the interrupt is not active.
XM_VATP_TX0/1_FIFO
[0x0410, 0x0428] TX FIFO Port (read/write)
TX FIFO Port
Data Bit
Description
31-0
FIFO Data 31-0
FIGURE 18
PMC-XM VIRTEX (ATP) CHANNEL TX FIFO PORT
Data written to this address is written into the transmit FIFO as long as the FIFO is not
full. When this address is read a data-word is read from the transmit FIFO. When the
FIFO becomes empty, the last data-word that was in the FIFO will be returned.
XM_VATP_RX0/1_FIFO
[0x0414, 0x042C] RX FIFO Port (read/write)
RX FIFO Port
Data Bit
Description
31-0
FIFO Data 31-0
FIGURE 19
PMC-XM VIRTEX (ATP) CHANNEL RX FIFO PORT
Data written to this address is written into the receive FIFO as long as the FIFO is not
full. When this address is read a data-word is read from the receive FIFO. When the
FIFO becomes empty, the last data-word that was in the FIFO will be returned.
