Hardware and Software Design • Manufacturing Services
page 39
In Direct mode data is moved from the Input FIFO to the Output FIFO bypassing the SDRAM. The half-full flag is
used to determine when there is data in the Input FIFO. The clock rate and number of accepted samples will
determine the captured data rate. The Output FIFO may go empty between bursts on the PCI bus. The PLX device
will be held off until sufficient data is stored within the Output FIFO to start a new PCI burst. The PLX device will not
capture the PCI bus until the internal FIFO has data. [the hardware will not lock up the bus waiting for data] The PCI
bus has a 2x advantage over input data stream. If the data is not read in time from the Output FIFO to be able to
accept new data from the Input FIFO then data will be lost. The Output FIFO should never become Full. Status bits
are set [DMA status register] to provide error feedback from this potential condition.
The Hardware should be initialized DMA first, Output FIFO reset second, Address generator third, FE fourth, PLX
last. The PLX chip can be initialized all but the last step of enabling the DMA function before doing the Xilinx
definitions. Once the FE Xilinx’s are started the data can begin to flow through the board. The PLX device must be
ready to handle the data when it arrives to prevent an overflow condition. Direct mode mode only. In Direct mode
there will be [513 + 1023] x 2 x 40 nS = 122.88 uS to capture enough samples to cause overflow once the FE is
enabled. [1/2 + 1 at input FIFO, all but one in output FIFO, 2 samples per word, 25 mhz capture rate]. There is
plenty of time for the PLX to fetch the 4 parameters from main memory and to start-up in time to transfer the
data.
The PLX device should be programmed to start the DMA transfer with the first sample read from the DMA Xilinx
and to read new data whenever there is at least room for 8 data samples in the internal FIFO. The PLX will then
start-up when commanded, wait for the DMA Xilinx to respond [FIFO is half full on programmed channel and state-
machine has started up] then request the PCI bus when the first transfer has happened from the DMA Xilinx. The
Bus arbitration and start-up take 6 clocks, during which time 6 more samples will have been read from the DMA
Xilinx. Assuming that the PCI bus is not busy, delaying the start of the burst, the DMA Xilinx and the PCI bus will
be synchronized and data will flow from the Output FIFO through the DMA Xilinx and PLX device to the PCI bus. If
the PCI bus has an issue or the max time has expired the PLX device will issue a BLASTn signal to the DMA Xilinx
to halt the transfer. When there is room within the PLX FIFO the process will restart. The pipeline will retain the
previous state and begin again where it left off. If the PCI bus is not used by other devices; the only down time will
be the 6 clocks for arbitration plus an additional 3 within the DMA Xilinx to restart. 250 data samples per 250+9
clocks for an effective bandwidth of 127.4 Mbytes/Sec. The SDRAM can support the data rate in Retrieve mode.
