DIGITAL-LOGIC MICROSPACE MSM800SEV, Technical User'S Manual

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DIGITAL-LOGIC AG
MSM800 SEV Manual V1.0A
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4.9.2 ROM-BIOS Sockets
An EPROM socket with 8 Bit wide data access normally contains the board's AT compatible ROM-BIOS. The
socket takes a 29F020 EPROM (or equivalent) device. The board's wait-state control logic automatically in-
serts four memory wait states in all CPU accesses to this socket. The ROM-BIOS sockets occupies the
memory area from C0000H through FFFFFh; however, the board's ASIC logic reserves the entire area from
C0000h through FFFFFh for onboard devices, so that this area is already usable for ROM-DOS and BIOS
expansion modules. Consult the appropriate address map for the MICROSPACE PC-Product ROM-BIOS
sockets.
4.9.2.1 Standard BIOS ROM
DEVICE: FWH
MAP: E0000 - FFFFFh Core BIOS 128k
C0000 - CBFFFh VGA BIOS 48k
CC000 - CFFFFh reserved
4.9.3 EEPROM Memory for Setup
Not supported on this product.
4.9.4 BIOS CMOS Setup
If wrong setups are memorized in the CMOS-RAM, the default values will be loaded after resetting the
RTC/CMOS-RAM by desoldering the batterie.
If the battery is down, it is always possible to start the system with the default values from the BIOS.
WARNING:
On the next setup pages (switch with TAB) the values for special parameters are modifiable. Normally the
parameters are set correctly by DIGITAL-LOGIC AG. Be very careful in modifying any parameter since the
system could crash. Some parameters are dependent on the CPU type. The cache parameter is always
available, for example. So, if you select too few wait states, the system will not start until you reset the
CMOS-RAM, desoldering the batterie but the default values are reloaded. If you are not familiar with these
parameters, do not change anything!