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N S 9 7 5 0 B - A 1 E r r a t a , R e v . F 0 9 / 2 0 0 6
L i n k e d E t h e r n e t T X b u f f e r d e s c r i p t o r s d o n ’ t w o r k w i t h l a t e c o l l i s i o n s
Linked Ethernet TX buffer descriptors don’t work with late collisions
If the Ethernet transmitter locks up when a late collision occurs while transmitting an Ethernet
package consisting of multiple linked buffer descriptors, one of these situations occurs:
The WRAP bit in the last entry of the embedded TXBD RAM is cleared.
The WRAP bit is set in both the first and last entries in the TXBD RAM.
Workaround: Software keeps a shadow copy of the TXBD RAM flags in main memory, and updates
the copy only when the CPU accesses the TXBD RAM. When the CPU receives an Ethernet TX ERROR
interrupt of any kind (that is, the TXERR bit is set in the Ethernet Interrupt Status register), which
includes a late collision, the CPU takes this action:
Reads the TX Error Buffer Descriptor Pointer register (TXERBD), which, in the case of the logic
error, points to the location that has the bad WRAP bit.
Copies the flags from the shadow TXBD RAM to the real TXBD RAM starting at the location
pointed to by the TXERBD and ending at the first shadow location that has the LAST bit set,
indicating the last buffer descriptor for the packet. This corrects the WRAP bit errors.
Summary of Contents for Errata NS9750B-A1
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