w w w . d i g i . c o m
3
U A R T C T S - r e l a t e d t r a n s m i t d a t a e r r o r s
Limitations:
The TMODE bit in the Bit-rate register must be cleared.
Baud rates are limited to those available in x16 mode
Baud rates with a divisor of 0 are not possible for all CPU frequencies. This translates to a
maximum baud rate of 460k in x16 mode.
Baud rates with a divisor of 1 are not possible for CPU frequencies below 147MHz. This
translates to a baud rate of 230k in x16 mode.
The buffer and character gaps must be an even multiple of the sample clock period. For a
96000bps UART in x16 UART mode, the equation is:
Timer increment
= ((1/9600) / 16) x 2 = 13.020us
One GPIO per UART is required to output the baud clock. The baud clock can be output on the
RI pin on each UART. This function is controlled by the RXEXT bit (27) in each Serial Bit-rate
register.
If multiple UARTs are running at the same baud rate, one baud clock can be used for the multiple
UARTs.
UART CTS-related transmit data errors
A problem occurs with the CTS flow control signal is de-asserted during the BCLK that begins
processing a new character. This problem causes the previous character to be resent instead of
getting the next character from the transmit FIFO.
Software workarounds:
Modify these bits in Serial Channel Control register A:
–
Set the CTSTX bit (bit 23) to 0 to disable hardware-controlled CTSTX.
–
Set the ERXCTS bit (bit 4) to enable the software CTS signal change interrupt.
–
Update the serial transmit ISR to handle the CTS signal change.
RXD[n]
Add R1 instead of U1 to bypass this circuit
RXCLK[n]
3.3V
3.3V
RXD_mod[n]
74LV74
U1A
D
Q
CLK
Q
PR
CL
UART GAP Timer
workaround
RESET
RXD[n]
74LV74
U1B
D
Q
CLK
Q
PR
CL
0 OHM
R1
Summary of Contents for Errata NS9750B-A1
Page 7: ......
