w w w . d i g i . c o m
5
P C I a r b i t e r s e n s e s f a l s e r e q u e s t
The USB PWR (power) control output requires additional external logic and GPIO to prevent USB
power from being enabled from the time power is valid until the code has set the USB registers and
selected gpio[17] to mode 00. The polarity of USB PWR is true high. Pulling down GPIO[17] to
disable the USB power control changes the CPU bus speed because this pin is also bootstrap — ND4.
Designs that add the additional GPIO to prevent USB power-on during startup would require the
BSP, as a final step, to set this GPIO to output a 1.
This figure shows a recommended logic workaround:
PCI arbiter senses false request
For complete information and workarounds for this issue, see the related application note at
http://www.digi.com/support/productdetl.jsp
.
Ethernet receive data FIFO overflow (Ethernet receiver stall)
The Ethernet receiver intermittently locks up in 100 Mbps half-duplex applications due to an
overflow in the RX data FIFO.
Workaround: Reset the RX Ethernet logic when an RX_OVFL_DATA interrupt is generated. Go to
http://www.digi.com/support/productdetl.jsp
to read the related application note for
instructions for doing this.
1284 nibble ID negotiation problem
The NS9750B-A1 should set the Xflag (Select) line low at event #6 (see the IEEE 1284 standards
specification). Instead, this signal is being driven high. The host uses this signal to determine
whether the requested mode is supported. Therefore, the host incorrectly concludes that the
NS9775 does not support nibble ID mode.
Workaround: None.
O
USB Power
Controller
2.4K
NS97xx
INV
GPIO[xy]
Rpull-up
RC filter = 500uS
Cfilter
Rfilter
NAND2
ENABLE_n
OVERCUR_n
3.3V
This circuit is required to prevent USB
power being enabled before code has set
GPIO[17] to mode 00. Pulling down
GPIO[17] effects CPU speed.
USB_PWR,
GPIO[17],
BOOTST_ND4
USB_OVR
GPIO[16]
O
Summary of Contents for Errata NS9750B-A1
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