Diamond Systems Athena II User Manual Download

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Note 1: Page 0, registers 0-11 are accessible when Page 1 or Page 2 are selected.

Note 2: In the following tables, blank bits are not used. Writes to a blank bit have no effect and
reads from a blank bit return a value of zero.

Register Map Bit Summary

Page 0 Write Register Summary

Base +

STRTAD

RSTBRD

RSTDA

RSTFIFO CLRDMA

CLRT

CLRD

CLRA

SCANEN

CKSEL1

CKFRQ1

CKFRQ0

ADCLK

DMAEN

TINTE

DINTE

AINTE

FT5

FT4

FT3

FT2

FT1

FT0

DA7-DA0

DACH1

DACH0

DA11

DA10

DA9

DA8

DIOCTR

DIRA

DIRCH

DIRB

DIRCL

D15

D14

D13

D12

D11

D10

CTRNO

LATCH

GTDIS

GTEN

CTDIS

CTEN

LOAD

CLR

Page 0 Read Register Summary

Base +

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

AD15

AD14

AD13

AD12

AD11

AD10

AD9

AD8

STS

WAIT

DACBSY

OVF

SCANEN

CKSEL1

CKFRQ1

CKFRQ0

ADCLK

DMAEN

TINTE

DINTE

AINTE

FT5

FT4

FT3

FT2

FT1

FT0

FD5-FD0

DMAINT

TINT

DINT

AINT

ADCH3

ADCH2

ADCH1

ADCH0

DIOCTR

DIRA

DIRCH

DIRB

DIRCL

D15

D14

D13

D12

D11

D10

REV7

REV6

REV5

REV4

REV3

REV2

REV1

REV0

Diamond Systems Corporation

Athena II User Manual

Page 52

Summary of Contents for Athena II

Page 1: ...al High Integration SBC with Ethernet and Data Acquisition User Manual v1 00 Copyright 2008 Diamond Systems Corporation 1255 Terra Bella Ave Mountain View CA 94043 Tel 650 810 2500 Fax 650 810 2525 www diamondsystems com ...

Page 2: ... Interfaces 13 Power Supply 14 Battery Backup 14 Watchdog Timer 14 Board Description 15 Board Layout 15 Connector Summary 16 Jumper Summary 16 Connectors 17 PC 104 ISA Bus J1 J2 17 Main I O J3 17 Ethernet J4 21 USB J5 J21 21 Watchdog Timer J6 22 USB0 J7 22 IDE J8 23 External Battery J9 24 Input Power J11 25 External Auxiliary Power Output J12 26 Data Acquisition Digital I O J14 27 Speaker J15 28 A...

Page 3: ...tchdog Timer 40 Flash Memory 41 Backup Battery 41 System Reset 41 On Board Video 42 BIOS 43 BIOS Settings 43 Serial Ports 43 Parallel Port 43 LCD Video Settings 43 Miscellaneous Settings 43 BIOS Console Redirection Settings 44 System I O 46 Ethernet 46 Serial Ports 46 PS 2 Ports 46 USB Ports 47 Notes on Operating Systems and Booting Procedures 48 Windows Operating System Installation Issues 48 Dri...

Page 4: ...rical data to a meaningful value 73 Conversion Formula for Bipolar Input Ranges 73 Conversion Formula for Unipolar Input Ranges 74 A D Scan Interrupt and FIFO Operation 75 Digital to Analog Output Ranges and Resolution 77 Description 77 Resolution 77 Output Range Selection 77 D A Conversion Formulas and Tables 77 D A Conversion Formulas for Unipolar Output Ranges 78 D A Conversion Formulas for Bip...

Page 5: ...Specifications Data Acquisition units only 90 Analog Inputs 90 Analog Outputs 90 Digital I O 90 Counter Timers 90 FlashDisk Module 91 Installing the FlashDisk Module 91 Configuration 91 Using the FlashDisk with Another IDE Drive 92 Power Supply 92 FlashDisk Programmer Board 93 I O Cables 94 Quick Start Guide 95 General Setup 95 IDE Configuration 95 Booting into MS DOS FreeDOS or ROM DOS 96 Booting...

Page 6: ...Access Connector 22 Figure 7 J7 USB0 Connector end view 23 Figure 8 J8 IDE Connector 23 Figure 9 J9 External Battery Connector end view 24 Figure 10 J11 Input Power Connector 25 Figure 11 J12 Auxiliary Power Output Connector end on view 26 Figure 12 J14 Digital I O Connector 27 Figure 13 J15 Speaker Connector 28 Figure 14 J24 LCD Panel Connector 29 Figure 15 J25 VGA Connector 30 Figure 16 J27 CPU ...

Page 7: ...gle ended Differential Selection 37 Figure 25 A D Unipolar Bipolar Selection 37 Figure 26 Analog Output Configuration Selection 38 Figure 27 J18 Jumper Block 38 Figure 28 Watchdog Timer Block Diagram 40 Figure 29 Athena II Data Acquisition Block Diagram 50 Figure 30 FlashDisk Module 91 Figure 31 FlashDisk Programmer Board Layout 93 Figure 32 Cable Kit C ATH KIT 94 Diamond Systems Corporation Athen...

Page 8: ...rocessor Speed RAM Size Data Acquisistion ATHM500 256A 500 MHz 256MB Yes ATHM500 256N 500 MHz 256MB No ATHM800 256A 800 MHz 256MB Yes ATHM800 256N 800 MHz 256MB No The Athena II CPU uses the ISA bus internally to connect serial ports 1 through 4 and the data acquisition circuit to the processor The ISA bus is brought out to an expansion connector to mate with add on boards Diamond Systems Corporat...

Page 9: ...z maximum aggregate A D sampling rate Programmable input ranges gains with maximum range of 10V 0 10V Both bipolar and unipolar input ranges 10 ppm C drift accuracy Internal and external A D triggering 2KB sample FIFO for reliable high speed sampling and scan operation Analog Output 4 analog outputs 12 bit resolution 10V and 0 10V output ranges available 5V and 0 5V output range optional Digital I...

Page 10: ...rminal mode On board lithium backup battery for real time clock and CMOS RAM ATX power switching capability Programmable watchdog timer Power supply 5VDC operation from the PC 104 bus or a power connector Extended temperature range operation 40 to 85 C Diamond Systems Corporation Athena II User Manual Page 10 ...

Page 11: ...Block Diagram Figure 1 shows the Athena II functional blocks Diamond Systems Corporation Athena II User Manual Page 11 Figure 1 Athena II Block Diagram ...

Page 12: ...or additional memory The board also includes flash memory for BIOS and user program storage Flash memory is accessible through the on board ISA bus Video Features Video circuitry is provided by the VIA Mark chipset Audio The design provides AC97 audio support derived from the Southbridge chip The Via VT1612A CODEC provides audio processing Audio I O includes Stereo line in Stereo line out Mono mic...

Page 13: ...1 1 ports IDE ports One 44 pin connector for HDD or compact flashdisk socket Athena II contains four serial ports Each port is capable of transmitting at speeds of up to 115 2Kbaud and uses a dedicated RS 232 transceiver with ESD protection Ports COM1 and COM2 are built into the standard chipset consisting of standard 16550 type UARTs with 16 byte FIFOs Ports COM3 and COM4 are derived from a dual ...

Page 14: ...4 bus or from the on board connectors The power supply includes ATX power switching and ACPI power management support Note The ATX power switch does not control the master 5V on the board Battery Backup Athena II contains a backup battery for the real time clock and BIOS settings The battery is directly soldered to the board and provides a minimum 7 year backup lifetime at 25oC The on board batter...

Page 15: ...escription Board Layout Figure 2 shows the Athena II board layout including connectors jumper blocks and mounting holes Diamond Systems Corporation Athena II User Manual Page 15 Figure 2 Athena II Board Layout ...

Page 16: ...4 pin laptop J9 External Battery J11 Input Power J12 External Auxiliary Power output J14 Data Acquisition I O J15 Audio I O J17 Auto calibration Reference Voltage J21 USB 2 3 J24 LVDS LCD J25 VGA J27 CPU Fan J28 LCD Backlight Power J30 CD Input Jumper Summary The following table lists the jumpers on the Athena II board Jumper Description J10 System configuration CPU features J13 Data acquisition c...

Page 17: ...D8 DACK0 IOCHRDY A10 B10 Key MEMR C9 D9 DRQ0 AEN A11 B11 SMEMW MEMW C10 D10 DACK5 SA19 A12 B12 SMEMR SD8 C11 D11 DRQ5 SA18 A13 B13 IOW SD9 C12 D12 DACK6 SA17 A14 B14 IOR SD10 C13 D13 DRQ6 SA16 A15 B15 DACK3 SD11 C14 D14 DACK7 SA15 A16 B16 DRQ3 SD12 C15 D15 DRQ7 SA14 A17 B17 DACK1 SD13 C16 D16 5 SA13 A18 B18 DRQ1 SD14 C17 D17 MASTER SA12 A19 B19 REFRESH SD15 C18 D18 Ground SA11 A20 B20 SYSCLK Key C...

Page 18: ... PS 2 keyboard PS 2 mouse IrDA port ATX Power switch Reset switch Power and HDD LEDs Diamond Systems Corporation Athena II User Manual Page 18 Figure 3 J3 Main I O Connector ...

Page 19: ...3 19 19 ACK DSR3 20 20 GND RXD3 21 21 BUSY RTS3 22 22 GND TXD3 23 23 PE CTS3 24 24 GND DTR3 25 25 SLCT RI3 26 26 KB Clk KYBD GND 27 27 KB MS V COM4 DCD4 28 28 KB Data DSR4 29 29 KB MS V RXD4 30 30 MS Clk Mouse RTS4 31 31 KB MS V TXD4 32 32 MS Data CTS4 33 33 KB MS V DTR4 34 34 GND Utilities B RI4 35 35 Reset GND 36 36 ATX Power Utilities A 5V Out 37 37 KB Lock Speaker Out 38 38 IR RX IDE Drive LED...

Page 20: ...Connect a speaker between this pin and 5V Out IDE Drive LED Referenced to 5V Out Does not require a series resistor Connect LED directly between this pin and 5V Out Power LED Referenced to 5V Out Does not require a series resistor Connect LED directly between this pin and 5V Out Utilities B Reset Connection between this pin and Ground will generate a Reset condition ATX Power When ATX is enabled a...

Page 21: ...ion to standard CAT5 network cables 1 Common 2 RX 3 Common 4 RX 5 TX 6 TX USB J5 J21 Connectors J5 USB 0 1 and J21 USB 2 3 provide four USB 2 0 ports J5 only Key pin cut 1 2 Shield J5 only GND 3 4 GND USB1 3 D 5 6 USB0 2 D USB1 3 D 7 8 USB0 2 D USB1 3 VCC 9 10 USB0 2 VCC Diamond Systems Corporation Athena II User Manual Page 21 Figure 5 J5 J21 USB Connectors Figure 4 J4 Ethernet Connector ...

Page 22: ...2 WDI 3 WDO Signal Definition WDI Watchdog Timer Input WDO Watchdog Timer Output GND 0V ground power return path Note The watchdog timer circuit may be programmed either directly as described in this manual or with the Diamond Systems Corporation Universal Driver software USB0 J7 Connector J7 USB0 is a mini USB connector that provides a single quick and simple on board USB connection for simple te...

Page 23: ...ircuitry Do not connect USB devices to both USB0 and J5 IDE J8 Connector J8 is a 2x22 pin header used for an IDE connection An associated mounting hole is provided to install a flash disk module Diamond Systems Corporation Athena II User Manual Page 23 Figure 7 J7 USB0 Connector end view Figure 8 J8 IDE Connector ...

Page 24: ...e 44 pin connector includes power and mates directly with notebook drives and flash disk modules To use a standard format hard disk or CD ROM drive with a 40 pin connector an adapter PCB such as Diamond Systems CorporationACC IDEEXT is required Note Connector J8 supports only up to ATA 33 UDMA 2 It does not support ATA 66 UDMA 3 to 5 transfer modes External Battery J9 Connector J9 is used to conne...

Page 25: ...X function Make sure that the power supply used has enough current capacity to drive your system The Athena CPU requires up to 2A on the 5V line for the 500Mhz configuration 3 0A for the 800Mhz configuration If you have a disk drive or other modules connected you need additional power In particular many disk drives need extra current during startup If your system fails to boot properly or if disk ...

Page 26: ...s enabled the power is switched ON and OFF with the ATX input switch If ATX is not enabled the power is switched ON and OFF in conjunction with the external power 1 5V switched 2 GND 3 GND 4 12V switched Signal Definition 5V This is provided by the on board power supply derived from the input power It is switched off when the board is powered down 12V This is provided by the 12V input pin on the m...

Page 27: ...15 16 DIO B7 DIO C0 17 18 DIO C1 DIO C2 19 20 DIO C3 DIO C4 GATE0 21 22 DIO C5 GATE1 DIO C6 CLK1 23 24 DIO C7 OUT0 EXTTRIG 25 26 TOUT1 5V out 27 28 DGND VOUT0 29 30 VOUT1 VOUT2 31 32 VOUT3 AGND Vout 33 34 AGND Vin VIN0 35 36 VIN8 VIN1 37 38 VIN9 VIN2 39 40 VIN10 VIN3 41 42 VIN11 VIN4 43 44 VIN12 VIN5 45 46 VIN13 VIN6 47 48 VIN14 VIN7 49 50 VIN15 Diamond Systems Corporation Athena II User Manual Pa...

Page 28: ...igital circuitry only AGND Analog ground used for analog circuitry only Vout pin is for analog outputs Vin pin is for analog inputs Diamond Systems Corporation cable no C 50 18 provides a standard 50 pin connector at each end and mates with this header Speaker J15 Connector J15 is a 2x5 pin header used to connect speakers Left headphone line out 1 2 Right headphone line out Audio ground 3 4 Line i...

Page 29: ...ion AutoCal routines read the exact voltage calibration values from the AutoCal Flash There are four analog values that need to be measured and stored in the AutoCal flash during manufacturing test Those values are produced from a very stable power source The values stored to AutoCal flash can be measured at header J17 where pin 1 is ground and pin 2 is one of the positive values shown in the foll...

Page 30: ...ay Signal Definition LCD1 Data 0 2 Primary Data Channel bits 0 2 LVDS Differential signaling LCD1 Clock Primary Data Channel Clock LVDS Differential signaling LCD2 Data 0 2 Secondary Data Channel bits 0 2 LVDS Differential signaling LCD2 Clock Secondary Data Channel Clock LVDS Differential signaling VDD 3 3V Switched Power Supply for LCD display only powered up when LCD display is active Ground Po...

Page 31: ...nitor ID pins are also not used Diamond Systems Corporation Cable Assembly 698024 provides a female DB15 connection to interface with a standard RGB monitor CPU Fan J27 Connector J27 is used to connect to the CPU fan 1 Fan RPM 2 GND 3 5v Signal Definition Fan RPM TTL signal input that pulses with each revolution of the fan 5 Power Supply for optional CPU Fan if necessary GND Ground LCD Backlight J...

Page 32: ...used to allow the system to power down the backlight when the system enables monitor power down during its power management control A 12V power supply must be provided either on the J11 input power connector or on the 12V pin on the PC 104 connector for the LCD backlight to operated This voltage is not generated internally CD Input J30 The J30 connector is for a PC standard CD input cable which pr...

Page 33: ...common in most desktop Personal Computers Note that the left and right grounds are decoupled but are also tied together on board This input is intended for CD input only i e no amplified or microphone inputs Diamond Systems Corporation Athena II User Manual Page 33 ...

Page 34: ... used to configure IRQ levels ATX power control and CMOS RAM J10 Pin Label Function BAT Battery connected in battery connected CMOS RAM settings preserved out battery not connected CMOS RAM settings erased ATX ATX power control in ATX like power control out standard powers up immediately 3 4 5 6 9 15 IRQ 3 selectable for COM3 COM4 IRQ 4 selectable for COM3 ADC IRQ 5 selectable for COM3 ADC IRQ 6 s...

Page 35: ...an only be used for A D if it is not already used for COM3 It is possible to set up all three circuits to share either IRQ4 or IRQ5 However only one device can use the shared IRQ at a time the ability for all three devices to run simultaneously is not supported Configure the IRQ options as shown in the following jumper settings Diamond Systems Corporation Athena II User Manual Page 35 Figure 20 IR...

Page 36: ...normally and an external momentary switch may be used to turn power ON and OFF A quick contact turns the power ON and a long contact greater than four seconds turns the power OFF If the ATX jumper is in the ATX function is bypassed and the system powers up as soon as power is connected This is the default setting as shown in Figure 22 If the ATX jumper is removed the battery backup for CMOS does n...

Page 37: ...differential input Athena II can be configured for either 16 single ended inputs or eight differential inputs as shown below The default setting is single ended mode If you have a combination of single ended and differential input signals select differential mode Then to measure the single ended signals connect the signal to the plus input and connect analog ground to the minus input WARNING The m...

Page 38: ...y the D A is configured to power up to 0V When the power is turned on the device connected to the analog output does not see a step change in voltage Therefore for unipolar mode the outputs should normally be configured for zero scale reset and for bipolar mode the outputs should be configured for mid scale reset because 0V is halfway between 10V and 10V for the 10V range RS 485 Mode Selection J18...

Page 39: ...y also vary depending on what other devices are present in the system For example adding a PC 104 Plus card may change the on board Ethernet resources The serial port settings for COM3 and COM4 are jumper selectable J10 whereas the settings for COM1 and COM2 are entirely software configured in the BIOS Console Redirection to a Serial Port In many applications without a local display and keyboard i...

Page 40: ...made If you selected COMA or COMB continue with the configuration as follows 1 For Console Type select PC ANSI 2 You can modify the baud rate and flow control here if desired 3 At the bottom for Continue C R after POST select Off default to turn off after POST or select On to remain on always 4 Exit the BIOS and save your settings Watchdog Timer Athena II contains a watchdog timer circuit consisti...

Page 41: ... Universal Driver software version 5 7 and later Flash Memory Athena II contains a 512KB 16 bit wide flash memory chip for storage of BIOS and other system configuration data Backup Battery Athena II contains an integrated RTC CMOS RAM backup battery This battery has a capacity of 120mAH and will last over three years in power off state The on board battery is activated for the first time during i...

Page 42: ...tion of 200 msec On Board Video Using the the on board VIA Mark processor Athena II integrates all of the support needed for modern media Refer to the VIA Technologies Inc documentation for the Mark processor listed in the Additional Information section of this document Diamond Systems Corporation Athena II User Manual Page 42 ...

Page 43: ...f no RGB monitor is detected the system enables LCD support If you choose to use the LCD display regardless of standard monitor connection i e with both connected at once set Boot Video Device to Both Panel Type This setting defaults to 7 Do not alter this setting unless specifically instructed to do so This setting affects the LCD display modes supported mode 7 is the only setting currently suppo...

Page 44: ...nt mode supported by the system is Power On Suspend Other suspend modes are not supported and should not be used under any OS Examples of unsupported suspend modes include Hibernate under Windows and Suspend to Disk or Suspend to RAM Memory Shadow These parameters should only be modified by advanced users These settings can adversely affect system performance and reliability BIOS Console Redirecti...

Page 45: ...ction If the OS enables video and starts using direct video functions which would be the case with a Linux X terminal or Windows for example Console Redirection has no effect and video is then required Diamond Systems Corporation Athena II User Manual Page 45 ...

Page 46: ...COM3 and COM4 are derived from an Exar 16C2850 dual UART chip and include 128 byte FIFOs These ports may be operated at speeds to 1 5Mbaud with installation of high speed drivers as a custom option The serial ports use the following default system resources Port I O Address Range IRQ COM1 0x3F8 0x3FF 4 COM2 0x2F8 0x2FF 3 COM3 0x3E8 0x3EF 3 4 5 6 9 COM4 0x2E8 0x2EF 3 15 The COM1 and COM2 settings m...

Page 47: ...e should function Keyboard Mouse USB Floppy Drive This is required for Crisis Recovery of boot ROM USB flash disk The BIOS supports the USB keyboard during BIOS initialization screens and legacy emulation for DOS based applications The USB ports can be used for keyboard and mouse at the same time that the PS 2 keyboard and mouse are connected Diamond Systems Corporation Athena II User Manual Page ...

Page 48: ... CompactFlash Under Windows CompactFlash is not directly supported by Windows 98 A special driver may be available see the vendor of your specific CompactFlash card for details Without special drivers Windows 98 does not recognize the CompactFlash CompactFlash support is built into Windows 2000 and XP DOS Operating Systems Installation Issues User the following sequence to install DOS operating sy...

Page 49: ...g system files on CompactFlash CompactFlash with FreeDOS The FreeDOS FDISK or FORMAT utility do not work with CompactFlash However the FreeDOS SYS utility is functional with CompactFlash CompactFlash with MS DOS The MS DOS FDISK FORMAT and SYS utilities are not functional when used with CompactFlash The MS DOS operating system files cannot be installed on CompactFlash flash Diamond Systems Corpora...

Page 50: ...errupts and a FIFO The FIFO is used to store a user selected number of samples and the interrupt occurs when the FIFO reaches this threshold Once the interrupt occurs an interrupt routine runs and reads the data out of the FIFO In this way the interrupt rate is reduced by a factor equal to the size of the FIFO threshold enabling a faster A D sampling rate The circuit can operate at sampling rates ...

Page 51: ...ion 0 Command A D LSB 1 Not used A D MSB 2 A D channel A D channel 3 A D gain page select scan settings A D gain and status 4 Interrupt DMA counter control Interrupt DMA counter control 5 FIFO threshold FIFO threshold 6 DAC LSB A D Channel and FIFO status 7 DAC MSB channel no Analog operation status 8 Digital I O port A Digital I O port A 9 Digital I O port B Digital I O port B 10 Digital I O port...

Page 52: ...C0 11 DIOCTR DIRA DIRCH DIRB DIRCL 12 D7 D6 D5 D4 D3 D2 D1 D0 13 D15 D14 D13 D12 D11 D10 D9 D8 14 23 22 21 20 19 18 17 16 15 CTRNO LATCH GTDIS GTEN CTDIS CTEN LOAD CLR Page 0 Read Register Summary Base 7 6 5 4 3 2 1 0 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 1 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 2 H3 H2 H1 H0 L3 L2 L1 L0 3 STS SD WAIT DACBSY OVF SCANEN G1 G0 4 CKSEL1 CKFRQ1 CKFRQ0 ADCLK DMAEN TINTE DIN...

Page 53: ... Read Register Summary Base 7 6 5 4 3 2 1 0 12 EEM_D7 EEM_D0 13 EEM_CA7 EEM_CA0 14 0 TDABSY EEMBSY ADCMEN 15 PG1ID Page 2 Write Register Summary Base 7 6 5 4 3 2 1 0 12 0 0 0 0 0 0 0 ADCEXF 13 0 0 0 0 UNIBIDI UNIBIOE SEDIFDI SEDIFOE 14 15 Page 2 Read Register Summary Base 7 6 5 4 3 2 1 0 12 0 0 0 0 0 0 0 ADCEXF 13 0 0 0 0 UNIBIDI UNIBIOE SEDIFDI SEDIFOE 14 15 PG2ID Diamond Systems Corporation Athe...

Page 54: ...eset is provided for the D A so that the user may reset the board if needed without affecting the circuitry connected to the analog outputs RSTFIFO Reset the FIFO depth to 0 This clears the FIFO allowing additional A D conversions to be stored in the FIFO starting at address 0 CLRDMA Writing a 1 to this bit resets the DMA interrupt request flip flop CLRT Writing a 1 to this bit resets the timer in...

Page 55: ...value is converted to the corresponding input voltage and or the engineering units represented by that voltage by applying additional application specific formulas Both conversions conversion to volts and conversion to engineering units may be combined into a single formula for efficiency A D MSB Base 1 Read Bit 7 6 5 4 3 2 1 0 Name AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD15 AD8 A D MSB data The A...

Page 56: ...ew gain setting Base 3 the WAIT bit is also set and the program must monitor the bit prior to starting an A D conversion The channel and gain registers can be written to in succession without waiting for the intervening WAIT signal Only one WAIT period must be observed between the last triggering condition write to Base 2 or Base 3 and the start of an A D conversion The A D circuit is designed to ...

Page 57: ...e seen by the A D converter and the voltage applied to the input pin The gain setting is the same for all input channels When this register is written the WAIT bit Read Base 3 bit 6 goes high for 10 microseconds to indicate that the analog input circuit is settling During this time an A D conversion should not be performed because the data will be inaccurate After writing a new gain setting the pr...

Page 58: ...AC is busy updating indicator approx 30 µS 1 Busy 0 Idle Do not attempt to write to the DAC Base 6 and Base 7 while the value of this bit is 1 OVF FIFO Overflow bit This bit indicates that the FIFO has overflowed meaning that the A D circuit has attempted to write data to a full FIFO This condition occurs when data is written into the FIFO faster than the FIFO is read When overflow occurs the FIFO...

Page 59: ...nput EXTTRIG DMAEN Enable DMA operation 1 Enable 0 Disable TINTE Enable timer interrupts 1 Enable 0 Disable DINTE Enable digital I O interrupts 1 Enable 0 Disable AINTE Enable analog input interrupts 1 Enable 0 Disable NOTE When AINTE 1 the A D cannot be triggered by writing to Base 0 Analog output interrupts are not supported on this board Multiple interrupt operations may be performed simultaneo...

Page 60: ...her sampling rates a higher threshold should be used to reduce the interrupt rate However remember that the higher the FIFO threshold the smaller the amount of FIFO space remaining to store data while waiting for the interrupt routine to respond If a FIFO overflow condition occurs lower the FIFO threshold and or lower the A D sampling rate DAC LSB Base 6 Write Bit 7 6 5 4 3 2 1 0 Name DA7 DA0 DA7 ...

Page 61: ...T DINT AINT ADCH3 ADCH2 ADCH1 ADCH0 DMAINT DMA interrupt status 1 interrupt pending 0 interrupt not pending TINT Timer interrupt status 1 interrupt pending 0 interrupt not pending DINT Digital I O interrupt status 1 interrupt pending 0 interrupt not pending AINT Analog input interrupt status 1 interrupt pending 0 interrupt not pending ADCH0 3 Current A D channel This is the channel sampled on the ...

Page 62: ...B Base 9 Read Write Bit 7 6 5 4 3 2 1 0 Name B7 B6 B5 B4 B3 B2 B1 B0 B0 B7 Port B data The register direction is controlled by bits in the register Base 11 below Digital I O Port C Base 10 Read Write Bit 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 C0 C0 C7 Port Cdata The register direction is controlled by bits in the register Base 11 below Diamond Systems Corporation Athena II User Manual Page 62 ...

Page 63: ... 0 output 1 input DIRCH Port C bits 7 4 direction 0 output 1 input DIRB Port B direction 0 output 1 input DIRCL Port C bits 0 3 direction 0 output 1 input Counter Timer Bits 0 7 Base 12 Read Write Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 D0 D7 LSB for counter 0 and counter 1 When writing to this register an internal load register is loaded Upon issuing a Load command using Base 15 the sele...

Page 64: ...ch command is returned Note The value returned is NOT the value written to this register Counter Timer Bits 16 23 Base 14 Read Write Bit 7 6 5 4 3 2 1 0 Name 23 22 21 20 19 18 17 16 D16 D23 This register is used for 24 bit wide Counter 0 only When writing to this register an internal load register is loaded Upon issuing a Load command using Base 15 for Counter 0 the counter s MSB register is loade...

Page 65: ...abled CTDIS Disable counting on the selected counter The counter ignores input pulses CTEN Enable counting on the selected counter The counter decrements with each input pulse LOAD Load the selected counter with the data written to Base 12 through Base 14 or Base 12 and Base 13 depending on which counter is being loaded CLR Clear the current counter setting its value to 0 This register is used to ...

Page 66: ...se 14 is not set TrimDAC address can be written by writing to this register or through the EEM mode EEM WriteTDA_Data The reset value is zero EEM_CD7 EEM_CD0 Data for the command data for the EEPROM Data can only be written when EEMBSY base 14 is cleared EEM Data Base 12 Read Bit 7 6 5 4 3 2 1 0 Name EEM_D7 EEM_D0 EEM_D7 EEM_D0 EEM data pointed to by EEPROM command address register base 13 Diamond...

Page 67: ...F fine adjustment 2 Q3 DAC3 ADCFUL range adjustment 3 Q4 DAC4 ADCFUL fine adjustment 4 Q5 DAC5 DACOFF range adjustment 5 Q6 DAC6 DACOFF fine adjustment 6 Q7 DAC7 DACFUL range adjustment 7 Q8 DAC8 DACFUL fine adjustment TrimDAC address can be written by writing to this register or through the EEM mode TrimDAC data can only be written when TDABSY base 14 is not set Reset value is zero EEM Command Ad...

Page 68: ... address ahs been written Trim DAC EEM Auto CAL Status Base 14 Read Bit 7 6 5 4 3 2 1 0 Name 0 TDABSY EEMBSY ADCMEN TDABSY TrimDAC busy flag 1 TrimDAC registers do not accept data address or the start command EEMBSY EEPROM busy flag 1 EEPROM busy ADCMEN Multiplexer auto calibrate mode 1 auto calibrate enabled Write Enable Base 15 Write Bit 7 6 5 4 3 2 1 0 Name WREN7 WREN0 WREN7 0 EEPROM write enab...

Page 69: ...3 2 1 0 Name 0 0 0 0 UNIBIDI UNIBIOE SEDIFDI SEDIFOE UNIBIDI Controls unipolar bipolar mode setting When set this overrides the jumper setting UNIBIOE Output enable When set the UNIBIDI value is gated to the output SEDIFDI Controls single ended differential mode setting When set this overrides the jumper setting SEDIFOE Output enable When set the SEDIFDI value is gated to the output Page 2 Select ...

Page 70: ...re they reach the A D converter The gain setting is controlled in software which allows it to be changed on a channel by channel basis In general you should select the highest gain smallest input range that allows the A D converter to read the full range of voltages over which the input signals will vary However a gain that is too high causes the A D converter to clip at either the high end or low...

Page 71: ...bered channels you do not need to write the input channel prior to each conversion For example to read from channels 0 2 write 0x20 to base 2 The first conversion is on channel 0 the second will be on channel 1 and the third will be on channel 2 The channel counter wraps around to the beginning so the fourth conversion will be on channel 0 again If you are sampling the same channel repeatedly set ...

Page 72: ...t as shown below int checkstatus returns 0 if ok 1 if error int i for i 0 i 10000 i if inp base 3 0x80 then return 0 conversion completed return 1 conversion did not complete Read the Data from the Board Once the conversion is complete you can read the data back from the A D converter The data is a 16 bit value and is read back in two 8 bit bytes The LSB must be read from the board before the MSB ...

Page 73: ... described However you can combine both transformations into a single formula if desired To convert the A D value to the corresponding input voltage use the following formulas Conversion Formula for Bipolar Input Ranges Input voltage A D value 32768 Full scale input range Example Given Input range is 5V and A D value is 17761 Therefore Input voltage 17761 32768 5V 2 710V For a bipolar input range ...

Page 74: ...ange 1 LSB 1 65536 Full scale voltage The following table illustrates the relationship between A D code and input voltage for a unipolar input range VFS Full scale input voltage A D Code Input Voltage Symbolic Formula Input Voltage for 0 5V Range 32768 0V 0 0000V 32767 1 LSB VFS 65536 0 000076V 1 VFS 2 1 LSB 2 4999V 0 VFS 2 2 5000V 1 VFS 2 1 LSB 2 5001V 32767 VFS 1 LSB 4 9999V Diamond Systems Corp...

Page 75: ...is 8 channels the FIFO threshold should be set to 8 16 24 32 40 or 48 but not less than 8 This way the interrupt will occur at the end of the scan and the interrupt routine can read in a complete scan or set of scans each time it runs In non scan mode SCANEN 0 the FIFO threshold should be set to a level that minimizes the interrupt rate but leaves enough time for the interrupt routine to respond b...

Page 76: ... D data when STS goes low 1 0 Single A D conversions are triggered by the source selected with ADCLK Base 4 bit 4 STS stays high during the A D conversion A D interrupt occurs when the FIFO reaches its programmed threshold The interrupt routine reads the number of samples equal to the FIFO threshold Base 5 bits 0 5 1 1 A D scans are triggered by the source selected with ADCLK Base 4 bit 4 STS stay...

Page 77: ...rce Resolution The resolution is the smallest possible change in output voltage For a 12 bit DAC the resolution is 1 212 or 1 4096 of the full scale output range This smallest change results from an increase or decrease of 1 in the D A code so this change is referred to as 1 least significant bit 1 LSB The value of this LSB is calculated as follows 1 LSB Output voltage range 4096 Example For Outpu...

Page 78: ... D A code 2 000V 10V 4096 819 2 819 Note the output code is always an integer For the unipolar output range 0 10V 1 LSB 1 4096 10V 2 44mV The following table illustrates the relationship between D A code and output voltage for a unipolar output range VREF Reference voltage D A Code Output Voltage Symbolic Formula Output Voltage for 0 10V Range 0 0V 0 0000V 1 1 LSB VREF 4096 0 0024V 2047 VREF 2 1 L...

Page 79: ...ode 2V 10V 2048 2048 2457 6 2458 For the bipolar output range 10V 1 LSB 1 4096 20V or 4 88mV The following table illustrates the relationship between D A code and output voltage for a bipolar output range VREF Reference voltage D A Code Output Voltage Symbolic Formula Output Voltage for 10V Range 0 VREF 10 0000V 1 VREF 1 LSB 9 9951V 2047 1 LSB 0 0049V 2048 0 0 0000V 2049 1 LSB 0 0049V 4095 VREF 1 ...

Page 80: ...The maximum output value is 4095 Therefore the maximum possible output voltage is always 1 LSB less than the full scale reference voltage Write the Value to the Selected Output Channel Registers Use the following formulas to compute the LSB and MSB values LSB D A Code 255 keep only the low 8 bits MSB int D A code 256 strip off low 8 bits keep 4 high bits Example For Output code 1776 Compute LSB 17...

Page 81: ...the D A chip and update the D A circuit in the chip During this period no attempt should be made to write to any other channel in the D A through addresses Base 6 or Base 7 The status bit DACBUSY Base 3 bit 4 indicates if the D A is busy updating 1 or idle 0 After writing to the D A monitor DACBUSY until it is zero before continuing with the next D A operation Diamond Systems Corporation Athena II...

Page 82: ...he circuit for Unipolar A D mode The gain setting and single ended vs differential mode do not matter Input 0V to any input channel and perform A D conversions on that channel Adjust R67 until the A D value is 0 1 To eliminate the effects of noise it is best to take a number of readings and average the values A D Full scale Potentiometer R74 ADFS is used for this adjustment Configure the circuit f...

Page 83: ...are 3 3V and 5V logic compatible Each output is capable of supplying 8mA in logic 1 state and 12mA in logic 0 state DIRA DIRB DIRCH and DIRCL control the direction of ports A B C4 7 and C0 3 A direction value of 0 means output and 1 means input All ports power up to input mode and the output registers are cleared to zero When a port direction is changed to output its output register is cleared to ...

Page 84: ...e and an output These signals may be user provided on the I O header when DIOCTR is 0 or the input may come from the on board clock generator When the on board clock generator is used the clock frequency is either 10MHz or 100KHz as determined by control Base 4 register bit CKFRQ1 The output is a positive going pulse that appears on pin 26 of the I O header The output pulse occurs when the counter...

Page 85: ...2 low outp base 13 middle outp base 13 high outp base 14 high 2 Load the counter Counter 0 Counter 1 outp base 15 0x02 outp base 15 0x82 3 Enable the gate if desired The gating may be enabled or disabled at any time When gating is disabled the counter counts all incoming edges When gating is enabled if the gate is high the counter counts all incoming edges and if the gate is low the counter ignore...

Page 86: ... counter is only cleared after stopping disabling and reading the counter If you clear a counter while it is enabled it continues to count incoming pulses so the counter value may not remain at zero 1 Stop disable the counter Counter 0 Counter 1 outp base 15 0x08 outp base 15 0x88 2 Read the data optional The value is returned in 3 bytes low middle and high 2 bytes for counter 1 Counter 0 Counter ...

Page 87: ...imer is supported in the DSC Universal Driver software version 5 7 and later Watchdog Timer Register Details The registers in the following table are used to program the watchdog timer I O Address Write Function Read Function 0x25C WDT trigger None write only 0x25D WDT counter None write only 0x25E Watchdog control Readback 0x25F Chip select enable disable Readback the last bits written In the tab...

Page 88: ...ead Write Bit 7 6 5 4 3 2 1 0 Name COM4EN COM3EN FPGAEN WDEN COM4EN COM4 chip select enable 1 Enable COM4 CS 0 Disable COM4 CS COM3EN COM3 chip select enable 1 Enable COM3 CS 0 Disable COM3 CS FPGAEN FPGA chip select enable 1 Enable FPGA CS 0 Disable FPGA CS WDEN Watchdog enable 1 Watchdog timer counter enable 0 Watchdog timer counter disable WDO disable WDI disable CPURST disable EXTSMI disable T...

Page 89: ... on an external pulse to constantly trigger watchdog timer A If the external stream of pulses ever halts timer A decrements to zero and starts timer B Once timer B decrements to 0 the board resets In this example we will make use of the T 1 feature of timer A to automatically reset itself unless a physical connection is broken The physical connection must be made between WDO and WDI on the data ac...

Page 90: ...eshold Analog Outputs No of outputs 4 D A resolution 12 bits 1 4096 of full scale Output ranges Unipolar 0 10V or user programmable Bipolar 10V or user programmable Output current 5mA max per channel Settling time 4µS max to 1 2 LSB Relative accuracy 1 LSB Nonlinearity 1 LSB monotonic Digital I O No of lines 24 Compatibility 3 3V and 5V logic compatible Input voltage Logic 0 0 5V min 0 8V max Logi...

Page 91: ...rectly on the IDE connector J16 and is held down with a spacer and two screws onto a mounting hole on the board The FlashDisk module contains a jumper for master slave configuration For master mode install the jumper over pins 1 and 2 For slave mode install the jumper over pins 2 and 3 Configuration To configure the CPU to work with the FlashDisk module enter the BIOS by pressing F2 during startup...

Page 92: ...e FlashDisk and a notebook drive the Diamond Systems Corporation ACC IDEEXT adapter and cables are required Power Supply The 44 pin cable carries power from the CPU to the adapter board and powers the FlashDisk module and any drive using a 44 pin connector such as a notebook hard drive A drive utilizing a 40 pin connector such as a CD ROM or full size hard drive requires an external power source t...

Page 93: ... ROM drive A dedicated connector J2 is provided for the FlashDisk module Any two devices may be connected simultaneously using this board with proper master slave jumper configurations on the devices The FlashDisk Programmer Board comes with a 44 wire cable no DSC no 698004 and a 40 wire cable no DSC no C 40 18 for connection to external drives The FlashDisk module is sold separately The 44 pin co...

Page 94: ... USB cable ports 0 1 3 698009 Power input cable 4 698006 Power output cable 5 C PRZ 01 80 wire 2 cable breakout cable assembly with serial parallel PS 2 mouse keyboard power reset speaker LED connectors 6 C PRZ 02 Ethernet cable 7 698030 VGA cable 8 698031 Audio cable 9 C 50 18 Data acquisition 50 conductor 1 ribbon cable 10 698004 IDE 44 conductor 2mm ribbon cable Diamond Systems Corporation Athe...

Page 95: ... supply out of its packaging Do not plug it into the wall yet Plug the 9 pin connector into the J11 connector on the board immediately below the PC 104 bus Be sure the red wire 5 VDC goes to pin 1 6 Optional for Ethernet Plug cable C PRZ 02 into connector J4 You can use the RJ 45 socket on the C PRZ 02 cable to patch Athena II into your network 7 Optional for USB Devices You will need to connect t...

Page 96: ...w to setup the Athena II board in preparation for a Linux or Windows install from an installation CD ROM onto a laptop IDE hard drive 1 Connect the IDE FashDisk programmer board to J8 2 Connect a CD ROM drive jumpered for the slave position to the IDE FlashDisk programmer board through the 40 pin cable 3 Connect power to the CD ROM drive using cable 698006 attached to J12 Be sure that an external ...

Page 97: ... bias current 100pA max Protection 35V on any analog input without damage Input Impedance 1013 ohms Nonlinearity 3LSB no missing codes Conversion rate 250 000 samples sec max On board FIFO 1024 samples programmable threshold A D and D A Calibration Automatic using on board microcontroller and temp sensor Analog Outputs 4 12 bit resolution Output ranges 5V 10V 0 5V 0 10V Output current 5mA max per ...

Page 98: ...Power Supply Input Voltage 5VDC 5 General Dimensions 4 528 x 6 496 115mm x 165mm Weight TBD Diamond Systems Corporation Athena II User Manual Page 98 ...

Page 99: ... websites 1 Diamond Systems Corporation http www diamondsystems com 2 VIA Technologies Inc http www via com tw en products processors corefusion mark index jsp 3 National Semiconductor Corporation http www national com Diamond Systems Corporation Athena II User Manual Page 99 ...

Page 100: ...Function F1 Help Esc Exit current screen up down arrow Select setup item left right arrow Select menu item plus minus symbols Change values Enter Execute command F9 Save default values F10 Save changes and exit BIOS setup mode At any time select Exit to exit BIOS setup mode Use the up down arrow keys followed by carriage return to apply one of the following exit actions Exit Action Description Exi...

Page 101: ...4 hour format System Date 00 00 00 Month day year Legacy Diskette A DISABLED ENABLED Legacy Diskette B DISABLED ENABLED X Primary Master See Primary Master HDD Setup Primary Slave See Primary Slave HDD Setup Secondary Master See Secondary Master HDD Setup X Secondary Slave See Secondary Slave HDD Setup X Memory Shadow See Memory Shadow Setup Memory Cache See Memory Cache Setup Quick Boot Mode ENAB...

Page 102: ... format Always calculated by the BIOS X Multi Sector Transfers DISABLE X LBA Mode Control DISABLE X 32 bit I O DISABLE ENABLE Transfer Mode DISABLE X Ultra DMA Mode DISABLE X Smart Monitoring DISABLE X Primary Slave HDD Setup This screen is the same as the Primary Master HDD Setup screen Secondary Master HDD Setup This screen is the same as the Primary Master HDD Setup screen Secondary Slave HDD S...

Page 103: ...te Back Uncached Write Through Write Protect Cache A000 AFFF Disabled USWC Write Through Write Protect Write Back Cache B000 BFFF Disabled USWC Write Through Write Protect Write Back Cache C800 CBFF Disabled USWC Write Through Write Protect Write Back Cache CC00 CFFF Disabled USWC Write Through Write Protect Write Back Cache D000 D3FF Disabled USWC Write Through Write Protect Write Back Cache D400...

Page 104: ...Protect Write Back Cache E000 E3FF Disabled USWC Write Through Write Protect Write Back Cache E400 E7FF Disabled USWC Write Through Write Protect Write Back Cache E800 EBFF Disabled USWC Write Through Write Protect Write Back Cache EC00 EFFF Disabled USWC Write Through Write Protect Write Back Diamond Systems Corporation Athena II User Manual Page 104 ...

Page 105: ... 2 Mouse Auto Detect Disabled Enabled LAN Disabled Enabled FPGA Mode Disabled Enabled Boot Video Device Auto Both LCD Panel Type 7 0 F Local Bus IDE Adapter Both Disabled Primary Secondary Legacy USB Support Enabled Disabled On chip Multi function Device See On chip Multi function Device Large Disk Access Mode DOS Other Installed O S Win98 Other Win95 WinME Win2000 Reset Configuration Data No Yes ...

Page 106: ...10 11 12 13 14 15 PCI IRQ Line 2 Disabled Auto Select 3 4 5 6 7 8 9 10 11 12 13 14 15 PCI IRQ Line 3 Disabled Auto Select 3 4 5 6 7 8 9 10 11 12 13 14 15 PCI IRQ Line 4 Disabled Auto Select 3 4 5 6 7 8 9 10 11 12 13 14 15 PCI PNP ISA UMB Region Exclusion Configuration Item Default Value or User Entry Optional Values Comments Change Not Allowed C800 CBFF Available Reserved CC00 CFFF Available Reser...

Page 107: ...Q10 Available Reserved IRQ11 Available Reserved IRQ15 Available Reserved PCI PNP ISA DMA Resource Exclusion Configuration Item Default Value or User Entry Optional Values Comments Change Not Allowed DMA0 Available Reserved DMA1 Available Reserved DMA2 Available Reserved DMA3 Available Reserved DMA4 Available Reserved DMA5 Available Reserved DMA6 Available Reserved DMA7 Available Reserved Diamond S...

Page 108: ...tem Default Value or User Entry Optional Values Comments Change Not Allowed Serial Port 1 Enabled Auto Disabled Base I O Address 3F8 2F8 3E8 2E8 Interrupt IRQ4 IRQ3 Mode Normal IrDA ASK_IR Serial Port 2 Enabled Auto Disabled Base I O Address 2F8 3F8 3E8 2E8 Interrupt IRQ3 IRQ4 Mode Normal IrDA ASK_IR Serial Port 3 Enabled Disabled Base I O Address 3E8 X Interrupt IRQ9 IRQ3 IRQ4 IRQ5 IRQ6 Mode RS23...

Page 109: ...A1 Data Acquisition IRQ IRQ5 Disabled IRQ4 IRQ6 On chip Multi function Device Configuration Item Default Value or User Entry Optional Values Comments Change Not Allowed On Chip USB 2 Device Enabled Disabled USB ports 2 and 3 Onboard Audio Enabled Disabled Legacy Audio Disabled Enabled Sound Blaster Disabled Enabled MPU 401 Disabled Enabled Joystick Disabled Enabled Diamond Systems Corporation Athe...

Page 110: ...2 of Video Pages to Support 1 2 8 Hardware Monitor Configuration Item Default Value or User Entry Optional Values Comments Change Not Allowed Vcore xx xx V Set by CPU X V 2 5V xx xx V Set by CPU X V 3 3V xx xx V Set by CPU X CPUTEMP1 Set by CPU X CPU FAN SPEED RPM Set by CPU X Security Configuration Item Default Value or User Entry Optional Values Comments Change Not Allowed Supervisor Password Is...

Page 111: ...c 1 2 4 6 8 10 15 min Video Timeout Disabled 10 15 30 45 sec 1 2 4 6 8 10 15 min Resume on LAN On Off Only active when LAN is enabled Resume on Time Off On Resume Time 00 00 00 Boot Configuration Item Default Value or User Entry Optional Values Comments Change Not Allowed Power Savings Disabled Customized Max Power Savings Boot Sequence Hard Drive CD ROM USB HDD Floppy Disk Removable Device The or...

Page 112: ...cal Support For technical support please email support diamondsystems com or contact Diamond Systems Corporation technical support at 1 650 810 2500 Diamond Systems Corporation Athena II User Manual Page 112 ...

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