Note 1: Page 0, registers 0-11 are accessible when Page 1 or Page 2 are selected.
Note 2: In the following tables, blank bits are not used. Writes to a blank bit have no effect and
reads from a blank bit return a value of zero.
Register Map Bit Summary
Page 0 Write Register Summary
Base +
7
6
5
4
3
2
1
0
0
STRTAD
RSTBRD
RSTDA
RSTFIFO CLRDMA
CLRT
CLRD
CLRA
1
-
-
-
-
-
-
-
-
2
H3
H2
H1
H0
L3
L2
L1
L0
3
-
-
-
-
-
SCANEN
G1
G0
4
CKSEL1
CKFRQ1
CKFRQ0
ADCLK
DMAEN
TINTE
DINTE
AINTE
5
-
-
FT5
FT4
FT3
FT2
FT1
FT0
6
DA7-DA0
7
DACH1
DACH0
-
-
DA11
DA10
DA9
DA8
8
A7
A6
A5
A4
A3
A2
A1
A0
9
B7
B6
B5
B4
B3
B2
B1
B0
10
C7
C6
C5
C4
C3
C2
C1
C0
11
DIOCTR
-
-
DIRA
DIRCH
-
DIRB
DIRCL
12
D7
D6
D5
D4
D3
D2
D1
D0
13
D15
D14
D13
D12
D11
D10
D9
D8
14
23
22
21
20
19
18
17
16
15
CTRNO
LATCH
GTDIS
GTEN
CTDIS
CTEN
LOAD
CLR
Page 0 Read Register Summary
Base +
7
6
5
4
3
2
1
0
0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
1
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
2
H3
H2
H1
H0
L3
L2
L1
L0
3
STS
SD
WAIT
DACBSY
OVF
SCANEN
G1
G0
4
CKSEL1
CKFRQ1
CKFRQ0
ADCLK
DMAEN
TINTE
DINTE
AINTE
5
-
-
FT5
FT4
FT3
FT2
FT1
FT0
6
-
-
FD5-FD0
7
DMAINT
TINT
DINT
AINT
ADCH3
ADCH2
ADCH1
ADCH0
8
A7
A6
A5
A4
A3
A2
A1
A0
9
B7
B6
B5
B4
B3
B2
B1
B0
10
C7
C6
C5
C4
C3
C2
C1
C0
11
DIOCTR
-
-
DIRA
DIRCH
-
DIRB
DIRCL
12
D7
D6
D5
D4
D3
D2
D1
D0
13
D15
D14
D13
D12
D11
D10
D9
D8
14
23
22
21
20
19
18
17
16
15
REV7
REV6
REV5
REV4
REV3
REV2
REV1
REV0
Diamond Systems Corporation
Athena II User Manual
Page 52