UM-B-093
DA1469x PRO Development Kit
User Manual
Revision 1.1
19-Feb-2019
CFR0012
15 of 22
© 2019 Dialog Semiconductor
Figure 19: Voltage Level Translation Circuit
VDDIO is a buffered version of the voltage used in the I/O from DA1469x side. This powers a triple
buffer gate (U22) with the direction from mainboard to DA1469x pins and also the single bidirectional
transceiver used for SWDIO (U21) on the DA1469x side.
The direction of signals from DA1469x to the mainboard is handled by U23 powered from the
mainboard 3.3 V.
The DA1469x debugging pins can be disconnected by the associated main board peripherals
through the multiple DIP-switch S1.
The daughterboard can be placed on top of the mainboard via two low-profile SMD connectors,
which are specified for a limited number of mating cycles (50).
Table 2: Mainboard/Daughterboard Mating Connectors
Main Board
Daughter Board
Amphenol FCI
10132797-055100LF
Amphenol FCI
10132798-052100LF
NOTE: The connectors have no polarity feature, so please be careful not to connect the
daughterboard rotated by 180°. Small arrows on the top silk screens of both boards are added to
indicate a properly aligned placement (
Figure 20
). The arrows on the mainboard must point to the
arrows on the daughterboard.
VOLTAGE LEVEL TRANSLATION
R72
33
VDDIO
VDDIO
BRSTn
VDDIO
M33_SWDIO
R149
100.0k
T_SWDIO
3.3V
U21
NTB0101GW_125
1
VCCA
A
3
2
GND
OE
5
B
4
6
VCCB
C3
1.0nF
C4
100nF
R4
0
R148
Mohm: 10M
LP11
500mA_470 OHM
C116
1.0nF
R1
NP
3.3V
R147
NP
UCTS
URX
T_SWCLK
U_CTS
U_RX
TP49
TP54
TP52
TP48
TP50
TP51
R3
100.0k
U22
NC7NZ34K8X
1A
1
GND
4
2A
3
2Y
5
VCC
8
1Y
7
3A
6
3Y
2
P0_11
P0_10
M33_SWCLK
M33_SWDIO
S1
97C06SRT
1
2
3
4
12
11
10
9
5
8
6
7
P0_9
P1_0
P0_8
URX
URTS
P0_7
UTX
UCTS
M33_SWCLK
V30
VREF
-
+
U1
LMV321AS5X
1
3
4
5
2
C1
100nF
5.0V
BRSTn
3.3V
RSTn
C117
100nF
U_TX
U_RTS
UTX
URTS
U23
NC7NZ34K8X
1A
1
GND
4
2A
3
2Y
5
VCC
8
1Y
7
3A
6
3Y
2
TP44
VDDIO
