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Award BIOS Setup Utility
SDRAM RAS Precharge Time
If there is insufficient number of cycles for the RAS to accumulate its
charge before DRAM refresh, the refresh may be incomplete and the
DRAM may fail to retain data.
System BIOS Cacheable
When this option is enabled, accesses to the system BIOS ROM
addressed at F0000H-FFFFFH are cached, provided that the cache
controller is enabled. The larger the range of the Cache RAM, the
higher the efficiency of the system.
Video BIOS Cacheable
As with caching the system BIOS, enabling the Video BIOS cache will
allow access to video BIOS addresssed at C0000H to C7FFFH to
be cached, if the cache controller is also enabled. The larger the range
of the Cache RAM, the faster the video performance.
Delayed Transaction
When enabled, this function frees up the PCI bus for other PCI
masters during the PCI-to-ISA transactions. This allows PCI and ISA
buses to be used more efficiently and prevents degradation of
performance on the PCI bus when ISA accesses are made.
