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3
BIOS Setup
AGP Fast Write
Select Enabled to support the AGP Fast Write function.
AGP Master 1 WS Write
Set this field to Enabled to add one clock tick to AGP write
operations.
AGP Master 1 WS Read
Set this field to Enabled to add one clock tick to AGP read op-
erations.
AGP 3.0 Calibration Cycle
Set this field to Enabled to support the AGP 3.0 calibration cycle
operations.
DBI Output for AGP Trans.
This field, when enabled, will provide better stability to the entire
system. The default is Enabled.
3.1.3.3 PCI1 Master 0 WS Write and PCI2 Master 0 WS Write
When enabled, writes to the PCI bus are executed with zero
wait state.
3.1.3.4 PCI1 Post Write and PCI2 Post Write
The options are Enabled and Disabled.
3.1.3.5 VLink 8x Support
Enabled
VLink’s speed which links the Nor th Bridge and
South Bridge is 8x.
Disabled
VLink’s speed which links the Nor th Bridge and
South Bridge is 4x.