DFI E586-ICP, User Manual, Page: 23 / 96

E586-ICP/E586-IPE
Cache Configuration
The E586-ICP/E586-IPE system board can be config-
ured to two different cache sizes: 256KB and 512KB.
256KB of cache memory is the default size.
The system board supports direct map write-back or
write-through cache subsystem with tag RAM integrated
into the chipset.
The E586-ICP uses Burst SRAM for fast 3-1-1-1 Level
2 cache access. The E586-IPE uses Async SRAM for
3-2-2-2 Level 2 cache access.
82433LX 82433LX
82434
82375
82374
SL82C101P
SRAM
SRAM
SRAM
SRAM
ZIF
Socket
Locations of the SRAMs on the E586-ICP System Board
Installation Overview
u
2-13