Denon CEOL Piccolo DRA-N5, Service Manual

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TAS5142DKD (AMP : IC118)
TAS5142 Pin Discriptions
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GENERAL INFORMATION
Terminal Assignment
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18 36
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GVDD_B
OTW
SD
PWM_A
RESET_AB
PWM_B
OC_ADJ
GND
AGND
VREG
M3
M2
M1
PWM_C
RESET_CD
PWM_D
VDD
GVDD_C
GVDD_A
BST_A
PVDD_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
PVDD_D
BST_D
GVDD_D
DKD PACKAGE
(TOP VIEW)
P0018-01
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GVDD_B
OTW
NC
NC
SD
PWM_A
RESET_AB
PWM_B
OC_ADJ
GND
AGND
VREG
M3
M2
M1
PWM_C
RESET_CD
PWM_D
NC
NC
VDD
GVDD_C
DDV PACKAGE
(TOP VIEW)
GVDD_A
BST_A
NC
PVDD_A
PVDD_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
PVDD_D
PVDD_D
NC
BST_D
GVDD_D
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P0016-02
TAS5142
SLES126B–DECEMBER 2004–REVISED MAY 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
The TAS5142 is available in two thermally enhanced packages:
• 36-pin PSOP3 package (DKD)
• 44-pin HTSSOP PowerPad™ package (DDV)
Both package types contain a heat slug that is located on the top side of the device for convenient thermal
coupling to the heatsink.
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Terminal Functions
TAS5142
SLES126B–DECEMBER 2004–REVISED MAY 2005
TERMINAL
FUNCTION
(1)
DESCRIPTION
NAME DKD NO. DDV NO.
AGND 9 11 P Analog ground
BST_A 35 43 P HS bootstrap supply (BST), external capacitor to OUT_A required
BST_B 28 34 P HS bootstrap supply (BST), external capacitor to OUT_B required
BST_C 27 33 P HS bootstrap supply (BST), external capacitor to OUT_C required
BST_D 20 24 P HS bootstrap supply (BST), external capacitor to OUT_D required
GND 8 10 P Ground
GND_A 32 38 P Power ground for half-bridge A
GND_B 31 37 P Power ground for half-bridge B
GND_C 24 30 P Power ground for half-bridge C
GND_D 23 29 P Power ground for half-bridge D
GVDD_A 36 44 P Gate-drive voltage supply requires 0.1- µ F capacitor to AGND
GVDD_B 1 1 P Gate-drive voltage supply requires 0.1- µ F capacitor to AGND
GVDD_C 18 22 P Gate-drive voltage supply requires 0.1- µ F capacitor to AGND
GVDD_D 19 23 P Gate-drive voltage supply requires 0.1- µ F capacitor to AGND
M1 13 15 I Mode selection pin
M2 12 14 I Mode selection pin
M3 11 13 I Mode selection pin
NC – 3, 4, 19, 20, 25, – No connect. Pins may be grounded.
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OC_ADJ 7 9 O Analog overcurrent programming pin requires resistor to ground
OTW 2 2 O Overtemperature warning signal, open-drain, active-low
OUT_A 33 39 O Output, half-bridge A
OUT_B 30 36 O Output, half-bridge B
OUT_C 25 31 O Output, half-bridge C
OUT_D 22 28 O Output, half-bridge D
PVDD_A 34 40, 41 P Power supply input for half-bridge A requires close decoupling of
0.1- µ F capacitor to GND_A.
PVDD_B 29 35 P Power supply input for half-bridge B requires close decoupling of
0.1- µ F capacitor to GND_B.
PVDD_C 26 32 P Power supply input for half-bridge C requires close decoupling of
0.1- µ F capacitor to GND_C.
PVDD_D 21 26, 27 P Power supply input for half-bridge D requires close decoupling of
0.1- µ F capacitor to GND_D.
PWM_A 4 6 I Input signal for half-bridge A
PWM_B 6 8 I Input signal for half-bridge B
PWM_C 14 16 I Input signal for half-bridge C
PWM_D 16 18 I Input signal for half-bridge D
RESET_AB 5 7 I Reset signal for half-bridge A and half-bridge B, active-low
RESET_CD 15 17 I Reset signal for half-bridge C and half-bridge D, active-low
SD 3 5 O Shutdown signal, open-drain, active-low
VDD 17 21 P Power supply for digital voltage regulator requires 0.1- µ F capacitor
to GND.
VREG 10 12 P Digital regulator supply filter pin requires 0.1- µ F capacitor to AGND.
(1) I = input, O = output, P = power
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