3U Turbo CPU Board for UMAC Turbo and Turbo Stack
3U Turbo CPU Board Configuration
5
BOARD CONFIGURATION
The base version of the 3U Turbo PMAC2 CPU board provides a 1-slot 3U-format Eurocard board with:
•
80 MHz DSP56303 CPU (120 MHz PMAC equivalent)
•
128k x 24 SRAM compiled/assembled program memory (Opt. 5C0)
•
128k x 24 SRAM user data memory (Opt. 5C0)
•
1M x 8 flash memory for user backup & firmware (Opt. 5C0)
•
Latest released firmware version
•
RS-232/422 serial interface
•
Inter-board stack connectors for piggyback servo and I/O accessory boards
•
Backplane UBUS expansion connector for pack servo and I/O accessory boards
If the 3A0 part prefix for the CPU board is ordered, the board comes with a standard Eurocard front plate
with top and bottom installation screws. (Top and bottom plates are provided with the Acc-Px pack
frame.
Option 2: Bus Interfaces
The 3U Turbo PMAC2 CPU board comes standard only with a serial interface. Option 2 provides a faster
bus interface for high-speed communications. The interface is PC/104 bus compatible (mechanical,
electrical, and software), so it is software-compatible with the ISA bus. However, the board is not
PC/104 form-factor compliant, and it can only be placed on top of a PC/104 stack.
•
Option 2: PC/104 interface, stacking connectors from solder side of CPU board
•
Option 2B: 32k x 16 bank of on-board dual-ported RAM (requires Option 2)
Option 4: CPU Type
The Turbo PMAC2-3U CPU board comes standard with a DSP56303 CPU IC as component U1. This
CPU has enough internal memory to process the servo and commutation for the first 15 motors entirely
from internal memory; these algorithms for the last 17 motors must be processed from slower external
memory. The optional DSP56309 CPU has additional internal memory, so the processing of these motors
is significantly improved. The processor type in the board is reported on receipt of the
CPU
command.
•
Option 4C: 80 MHz DSP56309 CPU IC. Recommended for control of more than 16 axes, especially
with PMAC-based commutation. Not compatible with any Option 5Dx.
•
Option 4D: 100 MHz DSP56309 CPU IC. Recommended for control of more than 16 axes,
especially with PMAC-based commutation. Not compatible with any option 5Cx
Option 5: CPU and Memory Configurations
The various versions of Option 5 provide different CPU speeds and main memory sizes on the piggyback
CPU board. Only one Option 5xx may be selected for the board.
The CPU is a DSP5630x IC as component U1. It is currently available only as an 80 MHz or 100 MHz
device (with computational power equivalent to a 120 MHz or 150 MHz non-Turbo PMAC, respectively),
but higher speed versions will be available shortly.
The compiled/assembled-program P memory SRAM ICs are located in U14, U15, and U16. These ICs
form the active memory for the firmware, compiled PLCs, and user-written phase/servo algorithms.
These can be 128k x 8 ICs (for a 128k x 24 bank), fitting in the smaller footprint, or they can be the larger
512k x 8 ICs (for a 512k x 24 bank), fitting in the full footprint.
The user-data memory (x/y) SRAM ICs are located in U11, U12, and U13. These ICs form the active
memory for user motion programs, uncompiled PLC programs, and user tables and buffers. These can be
128k x 8 ICs (for a 128k x 24 bank), fitting in the smaller footprint, or they can be the larger 512k x 8 ICs
(for a 512k x 24 bank), fitting in the full footprint.
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