DW1000 User Manual
© Decawave Ltd 2017
Version 2.12
Page 91 of 242
Field
Description of fields within Register file: 0x0F – System Event Status Register
HPDWARN
reg:0F:00
bit:27
Half Period Delay Warning. This event status bit relates to the use of delayed transmit and
delayed receive functionality. It indicates the delay is more than half a period of the system
clock.
For delayed send/receive the send/receive time is programmed into
and then the delayed sending/receiving is initiated by the
Register file: 0x0D – System Control Register
. The delayed transmit
and receive functionality is described in detail in sections
4.2 –
The HPDWARN event status flag gets set if the time left to actually beginning transmission /
reception is more than half a period of the system clock (
Register file: 0x06 – System Time
) away. Assuming that the intent was not to schedule transmission/reception at a
time that is over 8 seconds in the future, the HPDWARN status flag can be polled after the
TXDLYS/RXDLYE is commanded, to check whether the delayed send/ receive invocation was
given in time (HPDWARN ==0) or not (HPDWARN == 1).
Typically when the HPDWARN event is detected the host controller will abort the delayed
TX/RX by issuing a TRXOFF transceiver off command and then take whatever remedial action is
deemed appropriate for the application.
The HPDWARN event status flag is READ ONLY. It will clear when the delayed TX/RX is
cancelled or when the delay remaining is no longer greater than half a period of the system
clock.
HPDWARN events are counted in
Sub-Register 0x2F:18 – Half Period Warning Counter
assuming counting is enabled by the EVC_EN bit in
Sub-Register 0x2F:00 – Event Counter
TXBERR
reg:0F:00
bit:28
Transmit Buffer Error. The TXBERR event status flag bit indicates that a write to a transmitted
data buffer location has occurred whilst CRC was suppressed. Section
describes the DW1000 features for maximising data throughput. One technique
involves writing the frame data to the TX buffer after initiating the transmission of that frame.
During this data writing then, CRC sending is temporarily suppressed to protect against sending
the wrong data as a good frame (with good CRC). This CRC suppression is cancelled when all
the frame data has been written. If the frame data has been written to the buffer in good time
then the frame will be sent and a good CRC will be appended. If the data is written late, (i.e.
the host writes to the buffer area that is part of the TX frame after the DW1000 has already
consumed data from that area), then this is detected and flagged here in this TXBERR event
status flag bit. In this case CRC suppression cannot be cancelled (so no CRC is appended). This
will prevent transmission of a “bad” data frame with a good CRC. The TXBERR bit is cleared by
writing a 1 to it.
AFFREJ
reg:0F:00
bit:29
Automatic Frame Filtering rejection. The AFFREJ event status flag bit is set to indicate when a
frame has been rejected in receiver due to it not passing through the frame filtering. See
section
for details of the operation of frame filtering. The AFFREJ event
status bit can be cleared explicitly by writing a 1 to it. It is also automatically cleared by the
next receiver enable, including those caused by the RXAUTR auto-re-enable. Frame Filtering
rejection events are also counted in
Sub-Register 0x2F:0C – Frame Filter Rejection Counter
assuming counting is enabled by the EVC_EN bit in
