decaWave DW1000, User Manual, Page: 74 / 242

DW1000 User Manual
© Decawave Ltd 2017 Version 2.12 Page 74 of 242
7.2.8 Register file: 0x06
– System Time Counter
ID
Length
(octets)
Type Mnemonic Description
0x06 5 RO SYS_TIME System Time Counter (40-bit)
Register map register file 0x06 is the System Time Counter register. System time and time stamps are
designed to be based on the time units which are nominally at 64 GHz, or more precisely 499.2 MHz × 128
which is 63.8976 GHz. In line with this when the DW1000 is in idle mode with the digital PLL enabled, the
System Time Counter is incremented at a rate of 125 MHz in units of 512. The nine low-order bits of this
register are thus always zero. The counter wrap period of the clock is then: 2
40
÷ (128×499.2e6) = 17.2074
seconds.
Notes (a) On power up, before the digital PLL is enabled, the System Time Counter increments are still in
units of 512 however the increment rate is half the external crystal frequency, (e.g. at 19.2 MHz
for the 38.4 MHz crystal). The counter wrap period is then: 2
31
÷ 19.2e6 = 111.8481 seconds.
(b) In sleep modes the system time counter is disabled and this register is not updated.
7.2.9 Register file: 0x07
– Reserved
ID
Length
(octets)
Type Mnemonic Description
0x07 - - - Reserved – this register file is reserved
Register map register file 0x07 is reserved for future use. Please take care not to write to this register as
doing so may cause the DW1000 to malfunction.
7.2.10 Register file: 0x08
– Transmit Frame Control
ID
Length
(octets)
Type Mnemonic Description
0x08 5 RW TX_FCTRL Transmit Frame Control
Register map register file 0x08, the transmit frame control register, contains a number of TX control fields.
Each field is separately identified and described below. (For a general discussion of transmission please refer
to section 3
– Message Transmission .
REG:08:00 – TX_FCTRL – Transmit Frame Control (Octets 0 to 3, 32-bits)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXBOFFS PE TXPSR TXPRF TR TXBR R TFLE TFLEN
0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0
REG:08:04 – TX_FCTRL – Transmit Frame Control (Octet 4, 8-bits)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IFSDELAY
0 0 0 0 0 0 0 0